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ehci_pci.c revision 1.67
      1  1.67   msaitoh /*	$NetBSD: ehci_pci.c,v 1.67 2018/05/10 03:41:00 msaitoh Exp $	*/
      2   1.1  augustss 
      3   1.1  augustss /*
      4   1.8  augustss  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
      5   1.1  augustss  * All rights reserved.
      6   1.1  augustss  *
      7   1.1  augustss  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1  augustss  * by Lennart Augustsson (lennart (at) augustsson.net).
      9   1.1  augustss  *
     10   1.1  augustss  * Redistribution and use in source and binary forms, with or without
     11   1.1  augustss  * modification, are permitted provided that the following conditions
     12   1.1  augustss  * are met:
     13   1.1  augustss  * 1. Redistributions of source code must retain the above copyright
     14   1.1  augustss  *    notice, this list of conditions and the following disclaimer.
     15   1.1  augustss  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1  augustss  *    notice, this list of conditions and the following disclaimer in the
     17   1.1  augustss  *    documentation and/or other materials provided with the distribution.
     18   1.1  augustss  *
     19   1.1  augustss  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20   1.1  augustss  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21   1.1  augustss  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22   1.1  augustss  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23   1.1  augustss  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24   1.1  augustss  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25   1.1  augustss  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26   1.1  augustss  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27   1.1  augustss  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28   1.1  augustss  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29   1.1  augustss  * POSSIBILITY OF SUCH DAMAGE.
     30   1.1  augustss  */
     31   1.6     lukem 
     32   1.6     lukem #include <sys/cdefs.h>
     33  1.67   msaitoh __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.67 2018/05/10 03:41:00 msaitoh Exp $");
     34   1.1  augustss 
     35   1.1  augustss #include <sys/param.h>
     36   1.1  augustss #include <sys/systm.h>
     37   1.1  augustss #include <sys/kernel.h>
     38   1.1  augustss #include <sys/device.h>
     39   1.1  augustss #include <sys/proc.h>
     40   1.1  augustss #include <sys/queue.h>
     41   1.1  augustss 
     42  1.31        ad #include <sys/bus.h>
     43   1.1  augustss 
     44  1.22   xtraeme #include <dev/pci/pcidevs.h>
     45   1.1  augustss #include <dev/pci/pcivar.h>
     46   1.4  augustss #include <dev/pci/usb_pci.h>
     47   1.1  augustss 
     48   1.1  augustss #include <dev/usb/usb.h>
     49   1.1  augustss #include <dev/usb/usbdi.h>
     50   1.1  augustss #include <dev/usb/usbdivar.h>
     51   1.1  augustss #include <dev/usb/usb_mem.h>
     52   1.1  augustss 
     53   1.1  augustss #include <dev/usb/ehcireg.h>
     54   1.1  augustss #include <dev/usb/ehcivar.h>
     55   1.1  augustss 
     56   1.5  augustss #ifdef EHCI_DEBUG
     57   1.5  augustss #define DPRINTF(x)	if (ehcidebug) printf x
     58   1.5  augustss extern int ehcidebug;
     59   1.5  augustss #else
     60   1.5  augustss #define DPRINTF(x)
     61   1.5  augustss #endif
     62   1.5  augustss 
     63  1.45    cegger enum ehci_pci_quirk_flags {
     64  1.45    cegger 	EHCI_PCI_QUIRK_AMD_SB600 = 0x1,	/* always need a quirk */
     65  1.45    cegger 	EHCI_PCI_QUIRK_AMD_SB700 = 0x2,	/* depends on the SMB revision */
     66  1.45    cegger };
     67  1.45    cegger 
     68  1.45    cegger static const struct pci_quirkdata ehci_pci_quirks[] = {
     69  1.45    cegger 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI,
     70  1.45    cegger 	    EHCI_PCI_QUIRK_AMD_SB600 },
     71  1.45    cegger 	{ PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI,
     72  1.45    cegger 	    EHCI_PCI_QUIRK_AMD_SB700 },
     73  1.45    cegger };
     74  1.45    cegger 
     75  1.34  jmcneill static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc,
     76  1.34  jmcneill 				   pcitag_t tag);
     77  1.19  augustss static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc,
     78  1.19  augustss 			       pcitag_t tag);
     79  1.47    dyoung static bool ehci_pci_suspend(device_t, const pmf_qual_t *);
     80  1.47    dyoung static bool ehci_pci_resume(device_t, const pmf_qual_t *);
     81  1.19  augustss 
     82   1.1  augustss struct ehci_pci_softc {
     83   1.1  augustss 	ehci_softc_t		sc;
     84   1.1  augustss 	pci_chipset_tag_t	sc_pc;
     85   1.1  augustss 	pcitag_t		sc_tag;
     86   1.1  augustss 	void 			*sc_ih;		/* interrupt vectoring */
     87   1.1  augustss };
     88   1.1  augustss 
     89  1.51    dyoung static int ehci_sb700_match(const struct pci_attach_args *pa);
     90  1.45    cegger static int ehci_apply_amd_quirks(struct ehci_pci_softc *sc);
     91  1.45    cegger enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t,
     92  1.45    cegger 	pci_product_id_t);
     93  1.45    cegger 
     94  1.53  jmcneill #define EHCI_MAX_BIOS_WAIT		100 /* ms*10 */
     95  1.45    cegger #define EHCI_SBx00_WORKAROUND_REG	0x50
     96  1.45    cegger #define EHCI_SBx00_WORKAROUND_ENABLE	__BIT(27)
     97  1.45    cegger 
     98  1.19  augustss 
     99  1.18   thorpej static int
    100  1.41    dyoung ehci_pci_match(device_t parent, cfdata_t match, void *aux)
    101   1.1  augustss {
    102   1.1  augustss 	struct pci_attach_args *pa = (struct pci_attach_args *) aux;
    103   1.1  augustss 
    104   1.1  augustss 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
    105   1.1  augustss 	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
    106   1.1  augustss 	    PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI)
    107  1.41    dyoung 		return 1;
    108  1.17     perry 
    109  1.41    dyoung 	return 0;
    110   1.1  augustss }
    111   1.1  augustss 
    112  1.18   thorpej static void
    113  1.41    dyoung ehci_pci_attach(device_t parent, device_t self, void *aux)
    114   1.1  augustss {
    115  1.37  drochner 	struct ehci_pci_softc *sc = device_private(self);
    116   1.1  augustss 	struct pci_attach_args *pa = (struct pci_attach_args *)aux;
    117   1.1  augustss 	pci_chipset_tag_t pc = pa->pa_pc;
    118   1.1  augustss 	pcitag_t tag = pa->pa_tag;
    119   1.1  augustss 	char const *intrstr;
    120   1.1  augustss 	pci_intr_handle_t ih;
    121   1.1  augustss 	pcireg_t csr;
    122   1.5  augustss 	int ncomp;
    123   1.5  augustss 	struct usb_pci *up;
    124  1.45    cegger 	int quirk;
    125  1.58  christos 	char intrbuf[PCI_INTRSTR_LEN];
    126   1.1  augustss 
    127  1.37  drochner 	sc->sc.sc_dev = self;
    128  1.63     skrll 	sc->sc.sc_bus.ub_hcpriv = sc;
    129  1.37  drochner 
    130  1.54  drochner 	pci_aprint_devinfo(pa, "USB controller");
    131   1.1  augustss 
    132  1.45    cegger 	/* Check for quirks */
    133  1.45    cegger 	quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id),
    134  1.45    cegger 					   PCI_PRODUCT(pa->pa_id));
    135  1.45    cegger 
    136   1.1  augustss 	/* Map I/O registers */
    137   1.1  augustss 	if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0,
    138   1.1  augustss 			   &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) {
    139  1.43    cegger 		sc->sc.sc_size = 0;
    140  1.43    cegger 		aprint_error_dev(self, "can't map memory space\n");
    141   1.1  augustss 		return;
    142   1.1  augustss 	}
    143   1.1  augustss 
    144  1.60   msaitoh 	sc->sc_pc = pc;
    145  1.60   msaitoh 	sc->sc_tag = tag;
    146  1.63     skrll 	sc->sc.sc_bus.ub_dmatag = pa->pa_dmat;
    147  1.60   msaitoh 
    148  1.43    cegger 	/* Disable interrupts, so we don't get any spurious ones. */
    149  1.43    cegger 	sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
    150  1.43    cegger 	DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs));
    151  1.56       uwe 	EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
    152  1.43    cegger 
    153  1.45    cegger 	/* Handle quirks */
    154  1.45    cegger 	switch (quirk) {
    155  1.45    cegger 	case EHCI_PCI_QUIRK_AMD_SB600:
    156  1.45    cegger 		ehci_apply_amd_quirks(sc);
    157  1.45    cegger 		break;
    158  1.45    cegger 	case EHCI_PCI_QUIRK_AMD_SB700:
    159  1.45    cegger 		if (pci_find_device(NULL, ehci_sb700_match))
    160  1.45    cegger 			ehci_apply_amd_quirks(sc);
    161  1.45    cegger 		break;
    162  1.45    cegger 	}
    163  1.45    cegger 
    164  1.65  sborrill 	pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
    165  1.65  sborrill 	int pin = PCI_INTERRUPT_PIN(intr);
    166  1.65  sborrill 
    167   1.1  augustss 	/* Enable the device. */
    168   1.1  augustss 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
    169  1.65  sborrill 	csr |= PCI_COMMAND_MASTER_ENABLE;
    170  1.65  sborrill 	csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0);
    171  1.65  sborrill 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
    172   1.1  augustss 
    173   1.1  augustss 	/* Map and establish the interrupt. */
    174   1.3  sommerfe 	if (pci_intr_map(pa, &ih)) {
    175  1.43    cegger 		aprint_error_dev(self, "couldn't map interrupt\n");
    176  1.43    cegger 		goto fail;
    177   1.1  augustss 	}
    178  1.43    cegger 
    179  1.43    cegger 	/*
    180  1.43    cegger 	 * Allocate IRQ
    181  1.43    cegger 	 */
    182  1.58  christos 	intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
    183  1.64  jdolecek 	sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_USB, ehci_intr, sc,
    184  1.64  jdolecek 	    device_xname(self));
    185   1.1  augustss 	if (sc->sc_ih == NULL) {
    186  1.43    cegger 		aprint_error_dev(self, "couldn't establish interrupt");
    187   1.1  augustss 		if (intrstr != NULL)
    188  1.43    cegger 			aprint_error(" at %s", intrstr);
    189  1.43    cegger 		aprint_error("\n");
    190  1.62     skrll 		goto fail;
    191   1.1  augustss 	}
    192  1.43    cegger 	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
    193   1.1  augustss 
    194  1.67   msaitoh 	switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) {
    195   1.1  augustss 	case PCI_USBREV_PRE_1_0:
    196   1.1  augustss 	case PCI_USBREV_1_0:
    197   1.1  augustss 	case PCI_USBREV_1_1:
    198  1.63     skrll 		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
    199  1.43    cegger 		aprint_verbose_dev(self, "pre-2.0 USB rev\n");
    200  1.62     skrll 		goto fail;
    201   1.1  augustss 	case PCI_USBREV_2_0:
    202  1.63     skrll 		sc->sc.sc_bus.ub_revision = USBREV_2_0;
    203   1.1  augustss 		break;
    204   1.1  augustss 	default:
    205  1.63     skrll 		sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN;
    206   1.1  augustss 		break;
    207   1.1  augustss 	}
    208   1.1  augustss 
    209  1.22   xtraeme 	/* Enable workaround for dropped interrupts as required */
    210  1.66  jakllsch 	switch (PCI_VENDOR(pa->pa_id)) {
    211  1.30   tsutsui 	case PCI_VENDOR_ATI:
    212  1.30   tsutsui 	case PCI_VENDOR_VIATECH:
    213  1.22   xtraeme 		sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND;
    214  1.43    cegger 		aprint_normal_dev(self, "dropped intr workaround enabled\n");
    215  1.30   tsutsui 		break;
    216  1.30   tsutsui 	default:
    217  1.30   tsutsui 		break;
    218  1.30   tsutsui 	}
    219  1.22   xtraeme 
    220   1.5  augustss 	/*
    221   1.5  augustss 	 * Find companion controllers.  According to the spec they always
    222   1.5  augustss 	 * have lower function numbers so they should be enumerated already.
    223   1.5  augustss 	 */
    224  1.50      matt 	const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS));
    225  1.50      matt 	KASSERT(maxncomp <= EHCI_COMPANION_MAX);
    226   1.5  augustss 	ncomp = 0;
    227   1.5  augustss 	TAILQ_FOREACH(up, &ehci_pci_alldevs, next) {
    228  1.50      matt 		if (up->bus == pa->pa_bus && up->device == pa->pa_device
    229  1.50      matt 		    && !up->claimed) {
    230   1.5  augustss 			DPRINTF(("ehci_pci_attach: companion %s\n",
    231  1.37  drochner 				 device_xname(up->usb)));
    232   1.5  augustss 			sc->sc.sc_comps[ncomp++] = up->usb;
    233  1.50      matt 			up->claimed = true;
    234  1.50      matt 			if (ncomp == maxncomp)
    235   1.5  augustss 				break;
    236   1.5  augustss 		}
    237   1.5  augustss 	}
    238   1.5  augustss 	sc->sc.sc_ncomp = ncomp;
    239   1.5  augustss 
    240  1.19  augustss 	ehci_get_ownership(&sc->sc, pc, tag);
    241  1.19  augustss 
    242  1.63     skrll 	int err = ehci_init(&sc->sc);
    243  1.63     skrll 	if (err) {
    244  1.63     skrll 		aprint_error_dev(self, "init failed, error=%d\n", err);
    245  1.43    cegger 		goto fail;
    246   1.1  augustss 	}
    247   1.1  augustss 
    248  1.36    dyoung 	if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume,
    249  1.36    dyoung 	                          ehci_shutdown))
    250  1.32  jmcneill 		aprint_error_dev(self, "couldn't establish power handler\n");
    251  1.32  jmcneill 
    252   1.1  augustss 	/* Attach usb device. */
    253  1.37  drochner 	sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
    254  1.43    cegger 	return;
    255  1.43    cegger 
    256  1.43    cegger fail:
    257  1.43    cegger 	if (sc->sc_ih) {
    258  1.43    cegger 		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
    259  1.43    cegger 		sc->sc_ih = NULL;
    260  1.43    cegger 	}
    261  1.43    cegger 	if (sc->sc.sc_size) {
    262  1.43    cegger 		ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
    263  1.43    cegger 		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
    264  1.43    cegger 		sc->sc.sc_size = 0;
    265  1.43    cegger 	}
    266  1.43    cegger 	return;
    267   1.1  augustss }
    268   1.1  augustss 
    269  1.18   thorpej static int
    270  1.41    dyoung ehci_pci_detach(device_t self, int flags)
    271   1.1  augustss {
    272  1.37  drochner 	struct ehci_pci_softc *sc = device_private(self);
    273   1.1  augustss 	int rv;
    274   1.1  augustss 
    275   1.1  augustss 	rv = ehci_detach(&sc->sc, flags);
    276   1.1  augustss 	if (rv)
    277  1.41    dyoung 		return rv;
    278  1.40    dyoung 
    279  1.52    dyoung 	pmf_device_deregister(self);
    280  1.52    dyoung 	ehci_shutdown(self, flags);
    281  1.52    dyoung 
    282  1.40    dyoung 	/* disable interrupts */
    283  1.56       uwe 	EOWRITE4(&sc->sc, EHCI_USBINTR, 0);
    284  1.40    dyoung 	/* XXX grotty hack to flush the write */
    285  1.56       uwe 	(void)EOREAD4(&sc->sc, EHCI_USBINTR);
    286  1.40    dyoung 
    287   1.1  augustss 	if (sc->sc_ih != NULL) {
    288   1.1  augustss 		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
    289   1.1  augustss 		sc->sc_ih = NULL;
    290   1.1  augustss 	}
    291   1.1  augustss 	if (sc->sc.sc_size) {
    292  1.34  jmcneill 		ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
    293   1.1  augustss 		bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
    294   1.1  augustss 		sc->sc.sc_size = 0;
    295   1.1  augustss 	}
    296  1.34  jmcneill 
    297  1.55       mrg #if 1
    298  1.55       mrg 	/* XXX created in ehci.c */
    299  1.55       mrg 	mutex_destroy(&sc->sc.sc_lock);
    300  1.55       mrg 	mutex_destroy(&sc->sc.sc_intr_lock);
    301  1.55       mrg 
    302  1.55       mrg 	softint_disestablish(sc->sc.sc_doorbell_si);
    303  1.55       mrg 	softint_disestablish(sc->sc.sc_pcd_si);
    304  1.55       mrg #endif
    305  1.55       mrg 
    306  1.41    dyoung 	return 0;
    307   1.1  augustss }
    308  1.18   thorpej 
    309  1.39    dyoung CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc),
    310  1.35    dyoung     ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL,
    311  1.39    dyoung     ehci_childdet, DVF_DETACH_SHUTDOWN);
    312  1.19  augustss 
    313  1.19  augustss #ifdef EHCI_DEBUG
    314  1.19  augustss static void
    315  1.19  augustss ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
    316  1.19  augustss {
    317  1.44    cegger 	uint32_t cparams, legctlsts, addr, cap, id;
    318  1.19  augustss 	int maxdump = 10;
    319  1.19  augustss 
    320  1.19  augustss 	cparams = EREAD4(sc, EHCI_HCCPARAMS);
    321  1.19  augustss 	addr = EHCI_HCC_EECP(cparams);
    322  1.19  augustss 	while (addr != 0) {
    323  1.19  augustss 		cap = pci_conf_read(pc, tag, addr);
    324  1.19  augustss 		id = EHCI_CAP_GET_ID(cap);
    325  1.19  augustss 		switch (id) {
    326  1.19  augustss 		case EHCI_CAP_ID_LEGACY:
    327  1.19  augustss 			legctlsts = pci_conf_read(pc, tag,
    328  1.60   msaitoh 			    addr + PCI_EHCI_USBLEGCTLSTS);
    329  1.20  augustss 			printf("ehci_dump_caps: legsup=0x%08x "
    330  1.20  augustss 			       "legctlsts=0x%08x\n", cap, legctlsts);
    331  1.19  augustss 			break;
    332  1.19  augustss 		default:
    333  1.20  augustss 			printf("ehci_dump_caps: cap=0x%08x\n", cap);
    334  1.19  augustss 			break;
    335  1.19  augustss 		}
    336  1.19  augustss 		if (--maxdump < 0)
    337  1.19  augustss 			break;
    338  1.19  augustss 		addr = EHCI_CAP_GET_NEXT(cap);
    339  1.19  augustss 	}
    340  1.19  augustss }
    341  1.19  augustss #endif
    342  1.19  augustss 
    343  1.19  augustss static void
    344  1.34  jmcneill ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
    345  1.34  jmcneill {
    346  1.37  drochner 	const char *devname = device_xname(sc->sc_dev);
    347  1.44    cegger 	uint32_t cparams, addr, cap;
    348  1.34  jmcneill 	pcireg_t legsup;
    349  1.34  jmcneill 	int maxcap = 10;
    350  1.34  jmcneill 
    351  1.34  jmcneill 	cparams = EREAD4(sc, EHCI_HCCPARAMS);
    352  1.34  jmcneill 	addr = EHCI_HCC_EECP(cparams);
    353  1.34  jmcneill 	while (addr != 0) {
    354  1.34  jmcneill 		cap = pci_conf_read(pc, tag, addr);
    355  1.34  jmcneill 		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
    356  1.34  jmcneill 			goto next;
    357  1.34  jmcneill 		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
    358  1.34  jmcneill 		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
    359  1.34  jmcneill 		    legsup & ~EHCI_LEG_HC_OS_OWNED);
    360  1.34  jmcneill 
    361  1.34  jmcneill next:
    362  1.34  jmcneill 		if (--maxcap < 0) {
    363  1.34  jmcneill 			aprint_normal("%s: broken extended capabilities "
    364  1.34  jmcneill 				      "ignored\n", devname);
    365  1.34  jmcneill 			return;
    366  1.34  jmcneill 		}
    367  1.34  jmcneill 		addr = EHCI_CAP_GET_NEXT(cap);
    368  1.34  jmcneill 	}
    369  1.34  jmcneill }
    370  1.34  jmcneill 
    371  1.34  jmcneill static void
    372  1.19  augustss ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag)
    373  1.19  augustss {
    374  1.37  drochner 	const char *devname = device_xname(sc->sc_dev);
    375  1.44    cegger 	uint32_t cparams, addr, cap;
    376  1.33  jmcneill 	pcireg_t legsup;
    377  1.19  augustss 	int maxcap = 10;
    378  1.19  augustss 	int ms;
    379  1.19  augustss 
    380  1.19  augustss #ifdef EHCI_DEBUG
    381  1.20  augustss 	if (ehcidebug)
    382  1.20  augustss 		ehci_dump_caps(sc, pc, tag);
    383  1.19  augustss #endif
    384  1.19  augustss 	cparams = EREAD4(sc, EHCI_HCCPARAMS);
    385  1.19  augustss 	addr = EHCI_HCC_EECP(cparams);
    386  1.19  augustss 	while (addr != 0) {
    387  1.19  augustss 		cap = pci_conf_read(pc, tag, addr);
    388  1.34  jmcneill 		if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY)
    389  1.34  jmcneill 			goto next;
    390  1.34  jmcneill 		legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP);
    391  1.34  jmcneill 		if (legsup & EHCI_LEG_HC_BIOS_OWNED) {
    392  1.53  jmcneill 			/* Ask BIOS to give up ownership */
    393  1.53  jmcneill 			pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP,
    394  1.57   tsutsui 			    legsup | EHCI_LEG_HC_OS_OWNED);
    395  1.34  jmcneill 			for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) {
    396  1.34  jmcneill 				legsup = pci_conf_read(pc, tag,
    397  1.34  jmcneill 				    addr + PCI_EHCI_USBLEGSUP);
    398  1.34  jmcneill 				if (!(legsup & EHCI_LEG_HC_BIOS_OWNED))
    399  1.34  jmcneill 					break;
    400  1.53  jmcneill 				delay(10000);
    401  1.34  jmcneill 			}
    402  1.34  jmcneill 			if (ms == EHCI_MAX_BIOS_WAIT) {
    403  1.34  jmcneill 				aprint_normal("%s: BIOS refuses to give up "
    404  1.34  jmcneill 				    "ownership, using force\n", devname);
    405  1.34  jmcneill 				pci_conf_write(pc, tag,
    406  1.34  jmcneill 				    addr + PCI_EHCI_USBLEGSUP, 0);
    407  1.34  jmcneill 			} else
    408  1.34  jmcneill 				aprint_verbose("%s: BIOS has given up "
    409  1.34  jmcneill 				    "ownership\n", devname);
    410  1.34  jmcneill 		}
    411  1.34  jmcneill 
    412  1.34  jmcneill 		/* Disable SMIs */
    413  1.53  jmcneill 		pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0);
    414  1.34  jmcneill 
    415  1.34  jmcneill next:
    416  1.21  augustss 		if (--maxcap < 0) {
    417  1.21  augustss 			aprint_normal("%s: broken extended capabilities "
    418  1.21  augustss 				      "ignored\n", devname);
    419  1.19  augustss 			return;
    420  1.21  augustss 		}
    421  1.19  augustss 		addr = EHCI_CAP_GET_NEXT(cap);
    422  1.19  augustss 	}
    423  1.19  augustss 
    424  1.34  jmcneill }
    425  1.34  jmcneill 
    426  1.34  jmcneill static bool
    427  1.47    dyoung ehci_pci_suspend(device_t dv, const pmf_qual_t *qual)
    428  1.34  jmcneill {
    429  1.34  jmcneill 	struct ehci_pci_softc *sc = device_private(dv);
    430  1.28  jmcneill 
    431  1.46    dyoung 	ehci_suspend(dv, qual);
    432  1.34  jmcneill 	ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
    433  1.33  jmcneill 
    434  1.34  jmcneill 	return true;
    435  1.19  augustss }
    436  1.23  jmcneill 
    437  1.32  jmcneill static bool
    438  1.47    dyoung ehci_pci_resume(device_t dv, const pmf_qual_t *qual)
    439  1.23  jmcneill {
    440  1.32  jmcneill 	struct ehci_pci_softc *sc = device_private(dv);
    441  1.23  jmcneill 
    442  1.32  jmcneill 	ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag);
    443  1.46    dyoung 	return ehci_resume(dv, qual);
    444  1.23  jmcneill }
    445  1.45    cegger 
    446  1.45    cegger static int
    447  1.51    dyoung ehci_sb700_match(const struct pci_attach_args *pa)
    448  1.45    cegger {
    449  1.45    cegger 	if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
    450  1.45    cegger 	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB))
    451  1.45    cegger 		return 0;
    452  1.45    cegger 
    453  1.45    cegger 	switch (PCI_REVISION(pa->pa_class)) {
    454  1.45    cegger 	case 0x3a:
    455  1.45    cegger 	case 0x3b:
    456  1.45    cegger 		return 1;
    457  1.45    cegger 	}
    458  1.45    cegger 
    459  1.45    cegger 	return 0;
    460  1.45    cegger }
    461  1.45    cegger 
    462  1.45    cegger static int
    463  1.45    cegger ehci_apply_amd_quirks(struct ehci_pci_softc *sc)
    464  1.45    cegger {
    465  1.45    cegger 	pcireg_t value;
    466  1.63     skrll 
    467  1.45    cegger 	aprint_normal_dev(sc->sc.sc_dev,
    468  1.45    cegger 	    "applying AMD SB600/SB700 USB freeze workaround\n");
    469  1.45    cegger 	value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG);
    470  1.45    cegger 	pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG,
    471  1.45    cegger 	    value | EHCI_SBx00_WORKAROUND_ENABLE);
    472  1.45    cegger 
    473  1.45    cegger 	return 0;
    474  1.45    cegger }
    475  1.45    cegger 
    476  1.45    cegger enum ehci_pci_quirk_flags
    477  1.45    cegger ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product)
    478  1.45    cegger {
    479  1.45    cegger 	int i;
    480  1.45    cegger 
    481  1.45    cegger 	for (i = 0; i < __arraycount(ehci_pci_quirks); i++) {
    482  1.45    cegger 		if (vendor == ehci_pci_quirks[i].vendor &&
    483  1.45    cegger 		    product == ehci_pci_quirks[i].product)
    484  1.45    cegger 			return ehci_pci_quirks[i].quirks;
    485  1.45    cegger 	}
    486  1.45    cegger 	return 0;
    487  1.45    cegger }
    488  1.45    cegger 
    489