ehci_pci.c revision 1.31.2.1
1 /* $NetBSD: ehci_pci.c,v 1.31.2.1 2008/02/18 21:05:56 mjf Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.31.2.1 2008/02/18 21:05:56 mjf Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/proc.h> 47 #include <sys/queue.h> 48 49 #include <sys/bus.h> 50 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/usb_pci.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdivar.h> 58 #include <dev/usb/usb_mem.h> 59 60 #include <dev/usb/ehcireg.h> 61 #include <dev/usb/ehcivar.h> 62 63 #ifdef EHCI_DEBUG 64 #define DPRINTF(x) if (ehcidebug) printf x 65 extern int ehcidebug; 66 #else 67 #define DPRINTF(x) 68 #endif 69 70 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 71 pcitag_t tag); 72 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 73 pcitag_t tag); 74 static bool ehci_pci_suspend(device_t); 75 static bool ehci_pci_resume(device_t); 76 77 struct ehci_pci_softc { 78 ehci_softc_t sc; 79 pci_chipset_tag_t sc_pc; 80 pcitag_t sc_tag; 81 void *sc_ih; /* interrupt vectoring */ 82 83 void *sc_powerhook; 84 struct pci_conf_state sc_pciconf; 85 }; 86 87 #define EHCI_MAX_BIOS_WAIT 1000 /* ms */ 88 89 static int 90 ehci_pci_match(struct device *parent, struct cfdata *match, 91 void *aux) 92 { 93 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 94 95 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 96 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 97 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 98 return (1); 99 100 return (0); 101 } 102 103 static void 104 ehci_pci_attach(struct device *parent, struct device *self, void *aux) 105 { 106 struct ehci_pci_softc *sc = (struct ehci_pci_softc *)self; 107 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 108 pci_chipset_tag_t pc = pa->pa_pc; 109 pcitag_t tag = pa->pa_tag; 110 char const *intrstr; 111 pci_intr_handle_t ih; 112 pcireg_t csr; 113 const char *vendor; 114 const char *devname = sc->sc.sc_bus.bdev.dv_xname; 115 char devinfo[256]; 116 usbd_status r; 117 int ncomp; 118 struct usb_pci *up; 119 120 aprint_naive(": USB controller\n"); 121 122 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 123 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 124 PCI_REVISION(pa->pa_class)); 125 126 /* Map I/O registers */ 127 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 128 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 129 aprint_error("%s: can't map memory space\n", devname); 130 return; 131 } 132 133 sc->sc_pc = pc; 134 sc->sc_tag = tag; 135 sc->sc.sc_bus.dmatag = pa->pa_dmat; 136 137 /* Enable the device. */ 138 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 139 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 140 csr | PCI_COMMAND_MASTER_ENABLE); 141 142 /* Disable interrupts, so we don't get any spurious ones. */ 143 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 144 DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs)); 145 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 146 147 /* Map and establish the interrupt. */ 148 if (pci_intr_map(pa, &ih)) { 149 aprint_error("%s: couldn't map interrupt\n", devname); 150 return; 151 } 152 intrstr = pci_intr_string(pc, ih); 153 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 154 if (sc->sc_ih == NULL) { 155 aprint_error("%s: couldn't establish interrupt", devname); 156 if (intrstr != NULL) 157 aprint_normal(" at %s", intrstr); 158 aprint_normal("\n"); 159 return; 160 } 161 aprint_normal("%s: interrupting at %s\n", devname, intrstr); 162 163 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 164 case PCI_USBREV_PRE_1_0: 165 case PCI_USBREV_1_0: 166 case PCI_USBREV_1_1: 167 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 168 aprint_verbose("%s: pre-2.0 USB rev\n", devname); 169 return; 170 case PCI_USBREV_2_0: 171 sc->sc.sc_bus.usbrev = USBREV_2_0; 172 break; 173 default: 174 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 175 break; 176 } 177 178 /* Figure out vendor for root hub descriptor. */ 179 vendor = pci_findvendor(pa->pa_id); 180 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 181 if (vendor) 182 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 183 else 184 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 185 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 186 187 /* Enable workaround for dropped interrupts as required */ 188 switch (sc->sc.sc_id_vendor) { 189 case PCI_VENDOR_ATI: 190 case PCI_VENDOR_VIATECH: 191 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 192 aprint_normal("%s: dropped intr workaround enabled\n", devname); 193 break; 194 default: 195 break; 196 } 197 198 /* 199 * Find companion controllers. According to the spec they always 200 * have lower function numbers so they should be enumerated already. 201 */ 202 ncomp = 0; 203 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 204 if (up->bus == pa->pa_bus && up->device == pa->pa_device) { 205 DPRINTF(("ehci_pci_attach: companion %s\n", 206 USBDEVNAME(up->usb->bdev))); 207 sc->sc.sc_comps[ncomp++] = up->usb; 208 if (ncomp >= EHCI_COMPANION_MAX) 209 break; 210 } 211 } 212 sc->sc.sc_ncomp = ncomp; 213 214 ehci_get_ownership(&sc->sc, pc, tag); 215 216 /* 217 * Establish our powerhook before ehci_init() does its powerhook. 218 */ 219 sc->sc_powerhook = powerhook_establish( 220 USBDEVNAME(sc->sc.sc_bus.bdev) , ehci_pci_powerhook, sc); 221 if (sc->sc_powerhook == NULL) 222 aprint_error("%s: couldn't establish powerhook\n", 223 devname); 224 225 r = ehci_init(&sc->sc); 226 if (r != USBD_NORMAL_COMPLETION) { 227 aprint_error("%s: init failed, error=%d\n", devname, r); 228 return; 229 } 230 231 if (!pmf_device_register(self, ehci_pci_suspend, ehci_pci_resume)) 232 aprint_error_dev(self, "couldn't establish power handler\n"); 233 234 /* Attach usb device. */ 235 sc->sc.sc_child = config_found((void *)sc, &sc->sc.sc_bus, 236 usbctlprint); 237 } 238 239 static int 240 ehci_pci_detach(device_ptr_t self, int flags) 241 { 242 struct ehci_pci_softc *sc = (struct ehci_pci_softc *)self; 243 int rv; 244 245 if (sc->sc_powerhook != NULL) 246 powerhook_disestablish(sc->sc_powerhook); 247 248 rv = ehci_detach(&sc->sc, flags); 249 if (rv) 250 return (rv); 251 if (sc->sc_ih != NULL) { 252 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 253 sc->sc_ih = NULL; 254 } 255 if (sc->sc.sc_size) { 256 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 257 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 258 sc->sc.sc_size = 0; 259 } 260 261 return (0); 262 } 263 264 CFATTACH_DECL(ehci_pci, sizeof(struct ehci_pci_softc), 265 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate); 266 267 #ifdef EHCI_DEBUG 268 static void 269 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 270 { 271 u_int32_t cparams, legctlsts, addr, cap, id; 272 int maxdump = 10; 273 274 cparams = EREAD4(sc, EHCI_HCCPARAMS); 275 addr = EHCI_HCC_EECP(cparams); 276 while (addr != 0) { 277 cap = pci_conf_read(pc, tag, addr); 278 id = EHCI_CAP_GET_ID(cap); 279 switch (id) { 280 case EHCI_CAP_ID_LEGACY: 281 legctlsts = pci_conf_read(pc, tag, 282 addr + PCI_EHCI_USBLEGCTLSTS); 283 printf("ehci_dump_caps: legsup=0x%08x " 284 "legctlsts=0x%08x\n", cap, legctlsts); 285 break; 286 default: 287 printf("ehci_dump_caps: cap=0x%08x\n", cap); 288 break; 289 } 290 if (--maxdump < 0) 291 break; 292 addr = EHCI_CAP_GET_NEXT(cap); 293 } 294 } 295 #endif 296 297 static void 298 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 299 { 300 const char *devname = sc->sc_bus.bdev.dv_xname; 301 u_int32_t cparams, addr, cap; 302 pcireg_t legsup; 303 int maxcap = 10; 304 305 cparams = EREAD4(sc, EHCI_HCCPARAMS); 306 addr = EHCI_HCC_EECP(cparams); 307 while (addr != 0) { 308 cap = pci_conf_read(pc, tag, addr); 309 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 310 goto next; 311 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 312 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 313 legsup & ~EHCI_LEG_HC_OS_OWNED); 314 315 next: 316 if (--maxcap < 0) { 317 aprint_normal("%s: broken extended capabilities " 318 "ignored\n", devname); 319 return; 320 } 321 addr = EHCI_CAP_GET_NEXT(cap); 322 } 323 } 324 325 static void 326 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 327 { 328 const char *devname = sc->sc_bus.bdev.dv_xname; 329 u_int32_t cparams, addr, cap; 330 pcireg_t legsup; 331 int maxcap = 10; 332 int ms; 333 334 #ifdef EHCI_DEBUG 335 if (ehcidebug) 336 ehci_dump_caps(sc, pc, tag); 337 #endif 338 cparams = EREAD4(sc, EHCI_HCCPARAMS); 339 addr = EHCI_HCC_EECP(cparams); 340 while (addr != 0) { 341 cap = pci_conf_read(pc, tag, addr); 342 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 343 goto next; 344 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 345 /* Ask BIOS to give up ownership */ 346 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 347 legsup | EHCI_LEG_HC_OS_OWNED); 348 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 349 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 350 legsup = pci_conf_read(pc, tag, 351 addr + PCI_EHCI_USBLEGSUP); 352 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 353 break; 354 delay(1000); 355 } 356 if (ms == EHCI_MAX_BIOS_WAIT) { 357 aprint_normal("%s: BIOS refuses to give up " 358 "ownership, using force\n", devname); 359 pci_conf_write(pc, tag, 360 addr + PCI_EHCI_USBLEGSUP, 0); 361 } else 362 aprint_verbose("%s: BIOS has given up " 363 "ownership\n", devname); 364 } 365 366 /* Disable SMIs */ 367 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 368 EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD | 369 EHCI_LEG_EXT_SMI_OS_CHANGE); 370 371 next: 372 if (--maxcap < 0) { 373 aprint_normal("%s: broken extended capabilities " 374 "ignored\n", devname); 375 return; 376 } 377 addr = EHCI_CAP_GET_NEXT(cap); 378 } 379 380 } 381 382 static bool 383 ehci_pci_suspend(device_t dv) 384 { 385 struct ehci_pci_softc *sc = device_private(dv); 386 387 ehci_suspend(dv); 388 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 389 390 return true; 391 } 392 393 static void 394 ehci_pci_powerhook(int why, void *opaque) 395 { 396 struct ehci_pci_softc *sc; 397 pci_chipset_tag_t pc; 398 pcitag_t tag; 399 400 sc = (struct ehci_pci_softc *)opaque; 401 pc = sc->sc_pc; 402 tag = sc->sc_tag; 403 404 switch (why) { 405 case PWR_STANDBY: 406 case PWR_SUSPEND: 407 pci_conf_capture(pc, tag, &sc->sc_pciconf); 408 break; 409 case PWR_RESUME: 410 pci_conf_restore(pc, tag, &sc->sc_pciconf); 411 ehci_get_ownership(&sc->sc, pc, tag); 412 break; 413 } 414 415 return; 416 } 417
Indexes created Sat Oct 11 14:09:46 GMT 2025