ehci_pci.c revision 1.37
1 /* $NetBSD: ehci_pci.c,v 1.37 2008/03/28 17:14:45 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.37 2008/03/28 17:14:45 drochner Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/proc.h> 47 #include <sys/queue.h> 48 49 #include <sys/bus.h> 50 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/usb_pci.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdivar.h> 58 #include <dev/usb/usb_mem.h> 59 60 #include <dev/usb/ehcireg.h> 61 #include <dev/usb/ehcivar.h> 62 63 #ifdef EHCI_DEBUG 64 #define DPRINTF(x) if (ehcidebug) printf x 65 extern int ehcidebug; 66 #else 67 #define DPRINTF(x) 68 #endif 69 70 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 71 pcitag_t tag); 72 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 73 pcitag_t tag); 74 static bool ehci_pci_suspend(device_t PMF_FN_PROTO); 75 static bool ehci_pci_resume(device_t PMF_FN_PROTO); 76 77 struct ehci_pci_softc { 78 ehci_softc_t sc; 79 pci_chipset_tag_t sc_pc; 80 pcitag_t sc_tag; 81 void *sc_ih; /* interrupt vectoring */ 82 }; 83 84 #define EHCI_MAX_BIOS_WAIT 1000 /* ms */ 85 86 static int 87 ehci_pci_match(struct device *parent, struct cfdata *match, 88 void *aux) 89 { 90 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 91 92 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 93 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 94 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 95 return (1); 96 97 return (0); 98 } 99 100 static void 101 ehci_pci_attach(struct device *parent, struct device *self, void *aux) 102 { 103 struct ehci_pci_softc *sc = device_private(self); 104 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 105 pci_chipset_tag_t pc = pa->pa_pc; 106 pcitag_t tag = pa->pa_tag; 107 char const *intrstr; 108 pci_intr_handle_t ih; 109 pcireg_t csr; 110 const char *vendor; 111 const char *devname = device_xname(self); 112 char devinfo[256]; 113 usbd_status r; 114 int ncomp; 115 struct usb_pci *up; 116 117 sc->sc.sc_dev = self; 118 sc->sc.sc_bus.hci_private = sc; 119 120 aprint_naive(": USB controller\n"); 121 122 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 123 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 124 PCI_REVISION(pa->pa_class)); 125 126 /* Map I/O registers */ 127 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 128 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 129 aprint_error("%s: can't map memory space\n", devname); 130 return; 131 } 132 133 sc->sc_pc = pc; 134 sc->sc_tag = tag; 135 sc->sc.sc_bus.dmatag = pa->pa_dmat; 136 137 /* Enable the device. */ 138 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 139 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 140 csr | PCI_COMMAND_MASTER_ENABLE); 141 142 /* Disable interrupts, so we don't get any spurious ones. */ 143 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 144 DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs)); 145 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 146 147 /* Map and establish the interrupt. */ 148 if (pci_intr_map(pa, &ih)) { 149 aprint_error("%s: couldn't map interrupt\n", devname); 150 return; 151 } 152 intrstr = pci_intr_string(pc, ih); 153 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 154 if (sc->sc_ih == NULL) { 155 aprint_error("%s: couldn't establish interrupt", devname); 156 if (intrstr != NULL) 157 aprint_normal(" at %s", intrstr); 158 aprint_normal("\n"); 159 return; 160 } 161 aprint_normal("%s: interrupting at %s\n", devname, intrstr); 162 163 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 164 case PCI_USBREV_PRE_1_0: 165 case PCI_USBREV_1_0: 166 case PCI_USBREV_1_1: 167 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 168 aprint_verbose("%s: pre-2.0 USB rev\n", devname); 169 return; 170 case PCI_USBREV_2_0: 171 sc->sc.sc_bus.usbrev = USBREV_2_0; 172 break; 173 default: 174 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 175 break; 176 } 177 178 /* Figure out vendor for root hub descriptor. */ 179 vendor = pci_findvendor(pa->pa_id); 180 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 181 if (vendor) 182 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 183 else 184 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 185 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 186 187 /* Enable workaround for dropped interrupts as required */ 188 switch (sc->sc.sc_id_vendor) { 189 case PCI_VENDOR_ATI: 190 case PCI_VENDOR_VIATECH: 191 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 192 aprint_normal("%s: dropped intr workaround enabled\n", devname); 193 break; 194 default: 195 break; 196 } 197 198 /* 199 * Find companion controllers. According to the spec they always 200 * have lower function numbers so they should be enumerated already. 201 */ 202 ncomp = 0; 203 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 204 if (up->bus == pa->pa_bus && up->device == pa->pa_device) { 205 DPRINTF(("ehci_pci_attach: companion %s\n", 206 device_xname(up->usb))); 207 sc->sc.sc_comps[ncomp++] = up->usb; 208 if (ncomp >= EHCI_COMPANION_MAX) 209 break; 210 } 211 } 212 sc->sc.sc_ncomp = ncomp; 213 214 ehci_get_ownership(&sc->sc, pc, tag); 215 216 r = ehci_init(&sc->sc); 217 if (r != USBD_NORMAL_COMPLETION) { 218 aprint_error("%s: init failed, error=%d\n", devname, r); 219 return; 220 } 221 222 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 223 ehci_shutdown)) 224 aprint_error_dev(self, "couldn't establish power handler\n"); 225 226 /* Attach usb device. */ 227 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 228 } 229 230 static int 231 ehci_pci_detach(device_ptr_t self, int flags) 232 { 233 struct ehci_pci_softc *sc = device_private(self); 234 int rv; 235 236 pmf_device_deregister(self); 237 rv = ehci_detach(&sc->sc, flags); 238 if (rv) 239 return (rv); 240 if (sc->sc_ih != NULL) { 241 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 242 sc->sc_ih = NULL; 243 } 244 if (sc->sc.sc_size) { 245 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 246 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 247 sc->sc.sc_size = 0; 248 } 249 250 return (0); 251 } 252 253 CFATTACH_DECL2_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 254 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 255 ehci_childdet); 256 257 #ifdef EHCI_DEBUG 258 static void 259 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 260 { 261 u_int32_t cparams, legctlsts, addr, cap, id; 262 int maxdump = 10; 263 264 cparams = EREAD4(sc, EHCI_HCCPARAMS); 265 addr = EHCI_HCC_EECP(cparams); 266 while (addr != 0) { 267 cap = pci_conf_read(pc, tag, addr); 268 id = EHCI_CAP_GET_ID(cap); 269 switch (id) { 270 case EHCI_CAP_ID_LEGACY: 271 legctlsts = pci_conf_read(pc, tag, 272 addr + PCI_EHCI_USBLEGCTLSTS); 273 printf("ehci_dump_caps: legsup=0x%08x " 274 "legctlsts=0x%08x\n", cap, legctlsts); 275 break; 276 default: 277 printf("ehci_dump_caps: cap=0x%08x\n", cap); 278 break; 279 } 280 if (--maxdump < 0) 281 break; 282 addr = EHCI_CAP_GET_NEXT(cap); 283 } 284 } 285 #endif 286 287 static void 288 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 289 { 290 const char *devname = device_xname(sc->sc_dev); 291 u_int32_t cparams, addr, cap; 292 pcireg_t legsup; 293 int maxcap = 10; 294 295 cparams = EREAD4(sc, EHCI_HCCPARAMS); 296 addr = EHCI_HCC_EECP(cparams); 297 while (addr != 0) { 298 cap = pci_conf_read(pc, tag, addr); 299 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 300 goto next; 301 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 302 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 303 legsup & ~EHCI_LEG_HC_OS_OWNED); 304 305 next: 306 if (--maxcap < 0) { 307 aprint_normal("%s: broken extended capabilities " 308 "ignored\n", devname); 309 return; 310 } 311 addr = EHCI_CAP_GET_NEXT(cap); 312 } 313 } 314 315 static void 316 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 317 { 318 const char *devname = device_xname(sc->sc_dev); 319 u_int32_t cparams, addr, cap; 320 pcireg_t legsup; 321 int maxcap = 10; 322 int ms; 323 324 #ifdef EHCI_DEBUG 325 if (ehcidebug) 326 ehci_dump_caps(sc, pc, tag); 327 #endif 328 cparams = EREAD4(sc, EHCI_HCCPARAMS); 329 addr = EHCI_HCC_EECP(cparams); 330 while (addr != 0) { 331 cap = pci_conf_read(pc, tag, addr); 332 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 333 goto next; 334 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 335 /* Ask BIOS to give up ownership */ 336 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 337 legsup | EHCI_LEG_HC_OS_OWNED); 338 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 339 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 340 legsup = pci_conf_read(pc, tag, 341 addr + PCI_EHCI_USBLEGSUP); 342 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 343 break; 344 delay(1000); 345 } 346 if (ms == EHCI_MAX_BIOS_WAIT) { 347 aprint_normal("%s: BIOS refuses to give up " 348 "ownership, using force\n", devname); 349 pci_conf_write(pc, tag, 350 addr + PCI_EHCI_USBLEGSUP, 0); 351 } else 352 aprint_verbose("%s: BIOS has given up " 353 "ownership\n", devname); 354 } 355 356 /* Disable SMIs */ 357 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 358 EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD | 359 EHCI_LEG_EXT_SMI_OS_CHANGE); 360 361 next: 362 if (--maxcap < 0) { 363 aprint_normal("%s: broken extended capabilities " 364 "ignored\n", devname); 365 return; 366 } 367 addr = EHCI_CAP_GET_NEXT(cap); 368 } 369 370 } 371 372 static bool 373 ehci_pci_suspend(device_t dv PMF_FN_ARGS) 374 { 375 struct ehci_pci_softc *sc = device_private(dv); 376 377 ehci_suspend(dv PMF_FN_CALL); 378 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 379 380 return true; 381 } 382 383 static bool 384 ehci_pci_resume(device_t dv PMF_FN_ARGS) 385 { 386 struct ehci_pci_softc *sc = device_private(dv); 387 388 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 389 return ehci_resume(dv PMF_FN_CALL); 390 } 391
Indexes created Sat Sep 27 21:09:56 GMT 2025