ehci_pci.c revision 1.37.4.1
1 /* $NetBSD: ehci_pci.c,v 1.37.4.1 2008/05/16 02:24:43 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.37.4.1 2008/05/16 02:24:43 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 64 pcitag_t tag); 65 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 66 pcitag_t tag); 67 static bool ehci_pci_suspend(device_t PMF_FN_PROTO); 68 static bool ehci_pci_resume(device_t PMF_FN_PROTO); 69 70 struct ehci_pci_softc { 71 ehci_softc_t sc; 72 pci_chipset_tag_t sc_pc; 73 pcitag_t sc_tag; 74 void *sc_ih; /* interrupt vectoring */ 75 }; 76 77 #define EHCI_MAX_BIOS_WAIT 1000 /* ms */ 78 79 static int 80 ehci_pci_match(struct device *parent, struct cfdata *match, 81 void *aux) 82 { 83 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 84 85 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 86 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 87 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 88 return (1); 89 90 return (0); 91 } 92 93 static void 94 ehci_pci_attach(struct device *parent, struct device *self, void *aux) 95 { 96 struct ehci_pci_softc *sc = device_private(self); 97 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 98 pci_chipset_tag_t pc = pa->pa_pc; 99 pcitag_t tag = pa->pa_tag; 100 char const *intrstr; 101 pci_intr_handle_t ih; 102 pcireg_t csr; 103 const char *vendor; 104 const char *devname = device_xname(self); 105 char devinfo[256]; 106 usbd_status r; 107 int ncomp; 108 struct usb_pci *up; 109 110 sc->sc.sc_dev = self; 111 sc->sc.sc_bus.hci_private = sc; 112 113 aprint_naive(": USB controller\n"); 114 115 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 116 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 117 PCI_REVISION(pa->pa_class)); 118 119 /* Map I/O registers */ 120 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 121 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 122 aprint_error("%s: can't map memory space\n", devname); 123 return; 124 } 125 126 sc->sc_pc = pc; 127 sc->sc_tag = tag; 128 sc->sc.sc_bus.dmatag = pa->pa_dmat; 129 130 /* Enable the device. */ 131 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 132 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 133 csr | PCI_COMMAND_MASTER_ENABLE); 134 135 /* Disable interrupts, so we don't get any spurious ones. */ 136 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 137 DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs)); 138 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 139 140 /* Map and establish the interrupt. */ 141 if (pci_intr_map(pa, &ih)) { 142 aprint_error("%s: couldn't map interrupt\n", devname); 143 return; 144 } 145 intrstr = pci_intr_string(pc, ih); 146 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 147 if (sc->sc_ih == NULL) { 148 aprint_error("%s: couldn't establish interrupt", devname); 149 if (intrstr != NULL) 150 aprint_normal(" at %s", intrstr); 151 aprint_normal("\n"); 152 return; 153 } 154 aprint_normal("%s: interrupting at %s\n", devname, intrstr); 155 156 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 157 case PCI_USBREV_PRE_1_0: 158 case PCI_USBREV_1_0: 159 case PCI_USBREV_1_1: 160 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 161 aprint_verbose("%s: pre-2.0 USB rev\n", devname); 162 return; 163 case PCI_USBREV_2_0: 164 sc->sc.sc_bus.usbrev = USBREV_2_0; 165 break; 166 default: 167 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 168 break; 169 } 170 171 /* Figure out vendor for root hub descriptor. */ 172 vendor = pci_findvendor(pa->pa_id); 173 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 174 if (vendor) 175 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 176 else 177 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 178 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 179 180 /* Enable workaround for dropped interrupts as required */ 181 switch (sc->sc.sc_id_vendor) { 182 case PCI_VENDOR_ATI: 183 case PCI_VENDOR_VIATECH: 184 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 185 aprint_normal("%s: dropped intr workaround enabled\n", devname); 186 break; 187 default: 188 break; 189 } 190 191 /* 192 * Find companion controllers. According to the spec they always 193 * have lower function numbers so they should be enumerated already. 194 */ 195 ncomp = 0; 196 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 197 if (up->bus == pa->pa_bus && up->device == pa->pa_device) { 198 DPRINTF(("ehci_pci_attach: companion %s\n", 199 device_xname(up->usb))); 200 sc->sc.sc_comps[ncomp++] = up->usb; 201 if (ncomp >= EHCI_COMPANION_MAX) 202 break; 203 } 204 } 205 sc->sc.sc_ncomp = ncomp; 206 207 ehci_get_ownership(&sc->sc, pc, tag); 208 209 r = ehci_init(&sc->sc); 210 if (r != USBD_NORMAL_COMPLETION) { 211 aprint_error("%s: init failed, error=%d\n", devname, r); 212 return; 213 } 214 215 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 216 ehci_shutdown)) 217 aprint_error_dev(self, "couldn't establish power handler\n"); 218 219 /* Attach usb device. */ 220 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 221 } 222 223 static int 224 ehci_pci_detach(device_ptr_t self, int flags) 225 { 226 struct ehci_pci_softc *sc = device_private(self); 227 int rv; 228 229 pmf_device_deregister(self); 230 rv = ehci_detach(&sc->sc, flags); 231 if (rv) 232 return (rv); 233 if (sc->sc_ih != NULL) { 234 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 235 sc->sc_ih = NULL; 236 } 237 if (sc->sc.sc_size) { 238 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 239 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 240 sc->sc.sc_size = 0; 241 } 242 243 return (0); 244 } 245 246 CFATTACH_DECL2_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 247 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 248 ehci_childdet); 249 250 #ifdef EHCI_DEBUG 251 static void 252 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 253 { 254 u_int32_t cparams, legctlsts, addr, cap, id; 255 int maxdump = 10; 256 257 cparams = EREAD4(sc, EHCI_HCCPARAMS); 258 addr = EHCI_HCC_EECP(cparams); 259 while (addr != 0) { 260 cap = pci_conf_read(pc, tag, addr); 261 id = EHCI_CAP_GET_ID(cap); 262 switch (id) { 263 case EHCI_CAP_ID_LEGACY: 264 legctlsts = pci_conf_read(pc, tag, 265 addr + PCI_EHCI_USBLEGCTLSTS); 266 printf("ehci_dump_caps: legsup=0x%08x " 267 "legctlsts=0x%08x\n", cap, legctlsts); 268 break; 269 default: 270 printf("ehci_dump_caps: cap=0x%08x\n", cap); 271 break; 272 } 273 if (--maxdump < 0) 274 break; 275 addr = EHCI_CAP_GET_NEXT(cap); 276 } 277 } 278 #endif 279 280 static void 281 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 282 { 283 const char *devname = device_xname(sc->sc_dev); 284 u_int32_t cparams, addr, cap; 285 pcireg_t legsup; 286 int maxcap = 10; 287 288 cparams = EREAD4(sc, EHCI_HCCPARAMS); 289 addr = EHCI_HCC_EECP(cparams); 290 while (addr != 0) { 291 cap = pci_conf_read(pc, tag, addr); 292 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 293 goto next; 294 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 295 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 296 legsup & ~EHCI_LEG_HC_OS_OWNED); 297 298 next: 299 if (--maxcap < 0) { 300 aprint_normal("%s: broken extended capabilities " 301 "ignored\n", devname); 302 return; 303 } 304 addr = EHCI_CAP_GET_NEXT(cap); 305 } 306 } 307 308 static void 309 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 310 { 311 const char *devname = device_xname(sc->sc_dev); 312 u_int32_t cparams, addr, cap; 313 pcireg_t legsup; 314 int maxcap = 10; 315 int ms; 316 317 #ifdef EHCI_DEBUG 318 if (ehcidebug) 319 ehci_dump_caps(sc, pc, tag); 320 #endif 321 cparams = EREAD4(sc, EHCI_HCCPARAMS); 322 addr = EHCI_HCC_EECP(cparams); 323 while (addr != 0) { 324 cap = pci_conf_read(pc, tag, addr); 325 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 326 goto next; 327 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 328 /* Ask BIOS to give up ownership */ 329 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 330 legsup | EHCI_LEG_HC_OS_OWNED); 331 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 332 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 333 legsup = pci_conf_read(pc, tag, 334 addr + PCI_EHCI_USBLEGSUP); 335 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 336 break; 337 delay(1000); 338 } 339 if (ms == EHCI_MAX_BIOS_WAIT) { 340 aprint_normal("%s: BIOS refuses to give up " 341 "ownership, using force\n", devname); 342 pci_conf_write(pc, tag, 343 addr + PCI_EHCI_USBLEGSUP, 0); 344 } else 345 aprint_verbose("%s: BIOS has given up " 346 "ownership\n", devname); 347 } 348 349 /* Disable SMIs */ 350 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 351 EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD | 352 EHCI_LEG_EXT_SMI_OS_CHANGE); 353 354 next: 355 if (--maxcap < 0) { 356 aprint_normal("%s: broken extended capabilities " 357 "ignored\n", devname); 358 return; 359 } 360 addr = EHCI_CAP_GET_NEXT(cap); 361 } 362 363 } 364 365 static bool 366 ehci_pci_suspend(device_t dv PMF_FN_ARGS) 367 { 368 struct ehci_pci_softc *sc = device_private(dv); 369 370 ehci_suspend(dv PMF_FN_CALL); 371 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 372 373 return true; 374 } 375 376 static bool 377 ehci_pci_resume(device_t dv PMF_FN_ARGS) 378 { 379 struct ehci_pci_softc *sc = device_private(dv); 380 381 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 382 return ehci_resume(dv PMF_FN_CALL); 383 } 384
Indexes created Sat Oct 11 14:09:46 GMT 2025