ehci_pci.c revision 1.38.16.1.2.1
1 /* $NetBSD: ehci_pci.c,v 1.38.16.1.2.1 2010/04/21 00:27:39 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.38.16.1.2.1 2010/04/21 00:27:39 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 enum ehci_pci_quirk_flags { 64 EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ 65 EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ 66 }; 67 68 static const struct pci_quirkdata ehci_pci_quirks[] = { 69 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, 70 EHCI_PCI_QUIRK_AMD_SB600 }, 71 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, 72 EHCI_PCI_QUIRK_AMD_SB700 }, 73 }; 74 75 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 76 pcitag_t tag); 77 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 78 pcitag_t tag); 79 static bool ehci_pci_suspend(device_t PMF_FN_PROTO); 80 static bool ehci_pci_resume(device_t PMF_FN_PROTO); 81 82 struct ehci_pci_softc { 83 ehci_softc_t sc; 84 pci_chipset_tag_t sc_pc; 85 pcitag_t sc_tag; 86 void *sc_ih; /* interrupt vectoring */ 87 }; 88 89 static int ehci_sb700_match(struct pci_attach_args *pa); 90 static int ehci_apply_amd_quirks(struct ehci_pci_softc *sc); 91 enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, 92 pci_product_id_t); 93 94 #define EHCI_MAX_BIOS_WAIT 1000 /* ms */ 95 #define EHCI_SBx00_WORKAROUND_REG 0x50 96 #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) 97 98 99 static int 100 ehci_pci_match(struct device *parent, struct cfdata *match, 101 void *aux) 102 { 103 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 104 105 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 106 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 107 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 108 return (1); 109 110 return (0); 111 } 112 113 static void 114 ehci_pci_attach(struct device *parent, struct device *self, void *aux) 115 { 116 struct ehci_pci_softc *sc = device_private(self); 117 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 118 pci_chipset_tag_t pc = pa->pa_pc; 119 pcitag_t tag = pa->pa_tag; 120 char const *intrstr; 121 pci_intr_handle_t ih; 122 pcireg_t csr; 123 const char *vendor; 124 const char *devname = device_xname(self); 125 char devinfo[256]; 126 usbd_status r; 127 int ncomp; 128 struct usb_pci *up; 129 int quirk; 130 131 sc->sc.sc_dev = self; 132 sc->sc.sc_bus.hci_private = sc; 133 134 aprint_naive(": USB controller\n"); 135 136 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 137 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 138 PCI_REVISION(pa->pa_class)); 139 140 /* Check for quirks */ 141 quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 142 PCI_PRODUCT(pa->pa_id)); 143 144 /* Map I/O registers */ 145 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 146 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 147 aprint_error("%s: can't map memory space\n", devname); 148 return; 149 } 150 151 sc->sc_pc = pc; 152 sc->sc_tag = tag; 153 sc->sc.sc_bus.dmatag = pa->pa_dmat; 154 155 /* Handle quirks */ 156 switch (quirk) { 157 case EHCI_PCI_QUIRK_AMD_SB600: 158 ehci_apply_amd_quirks(sc); 159 break; 160 case EHCI_PCI_QUIRK_AMD_SB700: 161 if (pci_find_device(NULL, ehci_sb700_match)) 162 ehci_apply_amd_quirks(sc); 163 break; 164 } 165 166 /* Enable the device. */ 167 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 168 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 169 csr | PCI_COMMAND_MASTER_ENABLE); 170 171 /* Disable interrupts, so we don't get any spurious ones. */ 172 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 173 DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs)); 174 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 175 176 /* Map and establish the interrupt. */ 177 if (pci_intr_map(pa, &ih)) { 178 aprint_error("%s: couldn't map interrupt\n", devname); 179 return; 180 } 181 intrstr = pci_intr_string(pc, ih); 182 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 183 if (sc->sc_ih == NULL) { 184 aprint_error("%s: couldn't establish interrupt", devname); 185 if (intrstr != NULL) 186 aprint_normal(" at %s", intrstr); 187 aprint_normal("\n"); 188 return; 189 } 190 aprint_normal("%s: interrupting at %s\n", devname, intrstr); 191 192 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 193 case PCI_USBREV_PRE_1_0: 194 case PCI_USBREV_1_0: 195 case PCI_USBREV_1_1: 196 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 197 aprint_verbose("%s: pre-2.0 USB rev\n", devname); 198 return; 199 case PCI_USBREV_2_0: 200 sc->sc.sc_bus.usbrev = USBREV_2_0; 201 break; 202 default: 203 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 204 break; 205 } 206 207 /* Figure out vendor for root hub descriptor. */ 208 vendor = pci_findvendor(pa->pa_id); 209 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 210 if (vendor) 211 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 212 else 213 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 214 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 215 216 /* Enable workaround for dropped interrupts as required */ 217 switch (sc->sc.sc_id_vendor) { 218 case PCI_VENDOR_ATI: 219 case PCI_VENDOR_VIATECH: 220 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 221 aprint_normal("%s: dropped intr workaround enabled\n", devname); 222 break; 223 default: 224 break; 225 } 226 227 /* 228 * Find companion controllers. According to the spec they always 229 * have lower function numbers so they should be enumerated already. 230 */ 231 ncomp = 0; 232 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 233 if (up->bus == pa->pa_bus && up->device == pa->pa_device) { 234 DPRINTF(("ehci_pci_attach: companion %s\n", 235 device_xname(up->usb))); 236 sc->sc.sc_comps[ncomp++] = up->usb; 237 if (ncomp >= EHCI_COMPANION_MAX) 238 break; 239 } 240 } 241 sc->sc.sc_ncomp = ncomp; 242 243 ehci_get_ownership(&sc->sc, pc, tag); 244 245 r = ehci_init(&sc->sc); 246 if (r != USBD_NORMAL_COMPLETION) { 247 aprint_error("%s: init failed, error=%d\n", devname, r); 248 return; 249 } 250 251 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 252 ehci_shutdown)) 253 aprint_error_dev(self, "couldn't establish power handler\n"); 254 255 /* Attach usb device. */ 256 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 257 } 258 259 static int 260 ehci_pci_detach(device_ptr_t self, int flags) 261 { 262 struct ehci_pci_softc *sc = device_private(self); 263 int rv; 264 265 pmf_device_deregister(self); 266 rv = ehci_detach(&sc->sc, flags); 267 if (rv) 268 return (rv); 269 if (sc->sc_ih != NULL) { 270 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 271 sc->sc_ih = NULL; 272 } 273 if (sc->sc.sc_size) { 274 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 275 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 276 sc->sc.sc_size = 0; 277 } 278 279 return (0); 280 } 281 282 CFATTACH_DECL2_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 283 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 284 ehci_childdet); 285 286 #ifdef EHCI_DEBUG 287 static void 288 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 289 { 290 u_int32_t cparams, legctlsts, addr, cap, id; 291 int maxdump = 10; 292 293 cparams = EREAD4(sc, EHCI_HCCPARAMS); 294 addr = EHCI_HCC_EECP(cparams); 295 while (addr != 0) { 296 cap = pci_conf_read(pc, tag, addr); 297 id = EHCI_CAP_GET_ID(cap); 298 switch (id) { 299 case EHCI_CAP_ID_LEGACY: 300 legctlsts = pci_conf_read(pc, tag, 301 addr + PCI_EHCI_USBLEGCTLSTS); 302 printf("ehci_dump_caps: legsup=0x%08x " 303 "legctlsts=0x%08x\n", cap, legctlsts); 304 break; 305 default: 306 printf("ehci_dump_caps: cap=0x%08x\n", cap); 307 break; 308 } 309 if (--maxdump < 0) 310 break; 311 addr = EHCI_CAP_GET_NEXT(cap); 312 } 313 } 314 #endif 315 316 static void 317 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 318 { 319 const char *devname = device_xname(sc->sc_dev); 320 u_int32_t cparams, addr, cap; 321 pcireg_t legsup; 322 int maxcap = 10; 323 324 cparams = EREAD4(sc, EHCI_HCCPARAMS); 325 addr = EHCI_HCC_EECP(cparams); 326 while (addr != 0) { 327 cap = pci_conf_read(pc, tag, addr); 328 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 329 goto next; 330 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 331 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 332 legsup & ~EHCI_LEG_HC_OS_OWNED); 333 334 next: 335 if (--maxcap < 0) { 336 aprint_normal("%s: broken extended capabilities " 337 "ignored\n", devname); 338 return; 339 } 340 addr = EHCI_CAP_GET_NEXT(cap); 341 } 342 } 343 344 static void 345 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 346 { 347 const char *devname = device_xname(sc->sc_dev); 348 u_int32_t cparams, addr, cap; 349 pcireg_t legsup; 350 int maxcap = 10; 351 int ms; 352 353 #ifdef EHCI_DEBUG 354 if (ehcidebug) 355 ehci_dump_caps(sc, pc, tag); 356 #endif 357 cparams = EREAD4(sc, EHCI_HCCPARAMS); 358 addr = EHCI_HCC_EECP(cparams); 359 while (addr != 0) { 360 cap = pci_conf_read(pc, tag, addr); 361 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 362 goto next; 363 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 364 /* Ask BIOS to give up ownership */ 365 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 366 legsup | EHCI_LEG_HC_OS_OWNED); 367 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 368 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 369 legsup = pci_conf_read(pc, tag, 370 addr + PCI_EHCI_USBLEGSUP); 371 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 372 break; 373 delay(1000); 374 } 375 if (ms == EHCI_MAX_BIOS_WAIT) { 376 aprint_normal("%s: BIOS refuses to give up " 377 "ownership, using force\n", devname); 378 pci_conf_write(pc, tag, 379 addr + PCI_EHCI_USBLEGSUP, 0); 380 } else 381 aprint_verbose("%s: BIOS has given up " 382 "ownership\n", devname); 383 } 384 385 /* Disable SMIs */ 386 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 387 EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD | 388 EHCI_LEG_EXT_SMI_OS_CHANGE); 389 390 next: 391 if (--maxcap < 0) { 392 aprint_normal("%s: broken extended capabilities " 393 "ignored\n", devname); 394 return; 395 } 396 addr = EHCI_CAP_GET_NEXT(cap); 397 } 398 399 } 400 401 static bool 402 ehci_pci_suspend(device_t dv PMF_FN_ARGS) 403 { 404 struct ehci_pci_softc *sc = device_private(dv); 405 406 ehci_suspend(dv PMF_FN_CALL); 407 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 408 409 return true; 410 } 411 412 static bool 413 ehci_pci_resume(device_t dv PMF_FN_ARGS) 414 { 415 struct ehci_pci_softc *sc = device_private(dv); 416 417 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 418 return ehci_resume(dv PMF_FN_CALL); 419 } 420 421 static int 422 ehci_sb700_match(struct pci_attach_args *pa) 423 { 424 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 425 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) 426 return 0; 427 428 switch (PCI_REVISION(pa->pa_class)) { 429 case 0x3a: 430 case 0x3b: 431 return 1; 432 } 433 434 return 0; 435 } 436 437 static int 438 ehci_apply_amd_quirks(struct ehci_pci_softc *sc) 439 { 440 pcireg_t value; 441 442 aprint_normal_dev(sc->sc.sc_dev, 443 "applying AMD SB600/SB700 USB freeze workaround\n"); 444 value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); 445 pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, 446 value | EHCI_SBx00_WORKAROUND_ENABLE); 447 448 return 0; 449 } 450 451 enum ehci_pci_quirk_flags 452 ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 453 { 454 int i; 455 456 for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { 457 if (vendor == ehci_pci_quirks[i].vendor && 458 product == ehci_pci_quirks[i].product) 459 return ehci_pci_quirks[i].quirks; 460 } 461 return 0; 462 } 463 464
Indexes created Sat Oct 11 16:09:52 GMT 2025