ehci_pci.c revision 1.38.16.1.2.2
1 /* $NetBSD: ehci_pci.c,v 1.38.16.1.2.2 2012/01/03 18:27:21 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.38.16.1.2.2 2012/01/03 18:27:21 matt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 enum ehci_pci_quirk_flags { 64 EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ 65 EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ 66 }; 67 68 static const struct pci_quirkdata ehci_pci_quirks[] = { 69 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, 70 EHCI_PCI_QUIRK_AMD_SB600 }, 71 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, 72 EHCI_PCI_QUIRK_AMD_SB700 }, 73 }; 74 75 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 76 pcitag_t tag); 77 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 78 pcitag_t tag); 79 static bool ehci_pci_suspend(device_t PMF_FN_PROTO); 80 static bool ehci_pci_resume(device_t PMF_FN_PROTO); 81 82 struct ehci_pci_softc { 83 ehci_softc_t sc; 84 pci_chipset_tag_t sc_pc; 85 pcitag_t sc_tag; 86 void *sc_ih; /* interrupt vectoring */ 87 }; 88 89 static int ehci_sb700_match(struct pci_attach_args *pa); 90 static int ehci_apply_amd_quirks(struct ehci_pci_softc *sc); 91 enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, 92 pci_product_id_t); 93 94 #define EHCI_MAX_BIOS_WAIT 1000 /* ms */ 95 #define EHCI_SBx00_WORKAROUND_REG 0x50 96 #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) 97 98 99 static int 100 ehci_pci_match(struct device *parent, struct cfdata *match, 101 void *aux) 102 { 103 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 104 105 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 106 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 107 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 108 return (1); 109 110 return (0); 111 } 112 113 static void 114 ehci_pci_attach(struct device *parent, struct device *self, void *aux) 115 { 116 struct ehci_pci_softc *sc = device_private(self); 117 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 118 pci_chipset_tag_t pc = pa->pa_pc; 119 pcitag_t tag = pa->pa_tag; 120 char const *intrstr; 121 pci_intr_handle_t ih; 122 pcireg_t csr; 123 const char *vendor; 124 const char *devname = device_xname(self); 125 char devinfo[256]; 126 usbd_status r; 127 int ncomp; 128 struct usb_pci *up; 129 int quirk; 130 131 sc->sc.sc_dev = self; 132 sc->sc.sc_bus.hci_private = sc; 133 134 aprint_naive(": USB controller\n"); 135 136 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 137 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 138 PCI_REVISION(pa->pa_class)); 139 140 /* Check for quirks */ 141 quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 142 PCI_PRODUCT(pa->pa_id)); 143 144 /* Map I/O registers */ 145 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 146 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 147 aprint_error("%s: can't map memory space\n", devname); 148 return; 149 } 150 151 sc->sc_pc = pc; 152 sc->sc_tag = tag; 153 sc->sc.sc_bus.dmatag = pa->pa_dmat; 154 155 /* Handle quirks */ 156 switch (quirk) { 157 case EHCI_PCI_QUIRK_AMD_SB600: 158 ehci_apply_amd_quirks(sc); 159 break; 160 case EHCI_PCI_QUIRK_AMD_SB700: 161 if (pci_find_device(NULL, ehci_sb700_match)) 162 ehci_apply_amd_quirks(sc); 163 break; 164 } 165 166 /* Enable the device. */ 167 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 168 if ((csr & PCI_COMMAND_MASTER_ENABLE) == 0) { 169 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 170 csr | PCI_COMMAND_MASTER_ENABLE); 171 } 172 173 /* Disable interrupts, so we don't get any spurious ones. */ 174 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 175 DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs)); 176 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 177 178 /* Map and establish the interrupt. */ 179 if (pci_intr_map(pa, &ih)) { 180 aprint_error("%s: couldn't map interrupt\n", devname); 181 return; 182 } 183 intrstr = pci_intr_string(pc, ih); 184 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 185 if (sc->sc_ih == NULL) { 186 aprint_error("%s: couldn't establish interrupt", devname); 187 if (intrstr != NULL) 188 aprint_normal(" at %s", intrstr); 189 aprint_normal("\n"); 190 return; 191 } 192 aprint_normal("%s: interrupting at %s\n", devname, intrstr); 193 194 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 195 case PCI_USBREV_PRE_1_0: 196 case PCI_USBREV_1_0: 197 case PCI_USBREV_1_1: 198 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 199 aprint_verbose("%s: pre-2.0 USB rev\n", devname); 200 return; 201 case PCI_USBREV_2_0: 202 sc->sc.sc_bus.usbrev = USBREV_2_0; 203 break; 204 default: 205 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 206 break; 207 } 208 209 /* Figure out vendor for root hub descriptor. */ 210 vendor = pci_findvendor(pa->pa_id); 211 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 212 if (vendor) 213 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 214 else 215 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 216 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 217 218 /* Enable workaround for dropped interrupts as required */ 219 switch (sc->sc.sc_id_vendor) { 220 case PCI_VENDOR_ATI: 221 case PCI_VENDOR_VIATECH: 222 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 223 aprint_normal("%s: dropped intr workaround enabled\n", devname); 224 break; 225 default: 226 break; 227 } 228 229 /* 230 * Find companion controllers. According to the spec they always 231 * have lower function numbers so they should be enumerated already. 232 */ 233 ncomp = 0; 234 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 235 if (up->bus == pa->pa_bus && up->device == pa->pa_device) { 236 DPRINTF(("ehci_pci_attach: companion %s\n", 237 device_xname(up->usb))); 238 sc->sc.sc_comps[ncomp++] = up->usb; 239 if (ncomp >= EHCI_COMPANION_MAX) 240 break; 241 } 242 } 243 sc->sc.sc_ncomp = ncomp; 244 245 ehci_get_ownership(&sc->sc, pc, tag); 246 247 r = ehci_init(&sc->sc); 248 if (r != USBD_NORMAL_COMPLETION) { 249 aprint_error("%s: init failed, error=%d\n", devname, r); 250 return; 251 } 252 253 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 254 ehci_shutdown)) 255 aprint_error_dev(self, "couldn't establish power handler\n"); 256 257 /* Attach usb device. */ 258 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 259 } 260 261 static int 262 ehci_pci_detach(device_ptr_t self, int flags) 263 { 264 struct ehci_pci_softc *sc = device_private(self); 265 int rv; 266 267 pmf_device_deregister(self); 268 rv = ehci_detach(&sc->sc, flags); 269 if (rv) 270 return (rv); 271 if (sc->sc_ih != NULL) { 272 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 273 sc->sc_ih = NULL; 274 } 275 if (sc->sc.sc_size) { 276 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 277 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 278 sc->sc.sc_size = 0; 279 } 280 281 return (0); 282 } 283 284 CFATTACH_DECL2_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 285 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 286 ehci_childdet); 287 288 #ifdef EHCI_DEBUG 289 static void 290 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 291 { 292 u_int32_t cparams, legctlsts, addr, cap, id; 293 int maxdump = 10; 294 295 cparams = EREAD4(sc, EHCI_HCCPARAMS); 296 addr = EHCI_HCC_EECP(cparams); 297 while (addr != 0) { 298 cap = pci_conf_read(pc, tag, addr); 299 id = EHCI_CAP_GET_ID(cap); 300 switch (id) { 301 case EHCI_CAP_ID_LEGACY: 302 legctlsts = pci_conf_read(pc, tag, 303 addr + PCI_EHCI_USBLEGCTLSTS); 304 printf("ehci_dump_caps: legsup=0x%08x " 305 "legctlsts=0x%08x\n", cap, legctlsts); 306 break; 307 default: 308 printf("ehci_dump_caps: cap=0x%08x\n", cap); 309 break; 310 } 311 if (--maxdump < 0) 312 break; 313 addr = EHCI_CAP_GET_NEXT(cap); 314 } 315 } 316 #endif 317 318 static void 319 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 320 { 321 const char *devname = device_xname(sc->sc_dev); 322 u_int32_t cparams, addr, cap; 323 pcireg_t legsup; 324 int maxcap = 10; 325 326 cparams = EREAD4(sc, EHCI_HCCPARAMS); 327 addr = EHCI_HCC_EECP(cparams); 328 while (addr != 0) { 329 cap = pci_conf_read(pc, tag, addr); 330 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 331 goto next; 332 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 333 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 334 legsup & ~EHCI_LEG_HC_OS_OWNED); 335 336 next: 337 if (--maxcap < 0) { 338 aprint_normal("%s: broken extended capabilities " 339 "ignored\n", devname); 340 return; 341 } 342 addr = EHCI_CAP_GET_NEXT(cap); 343 } 344 } 345 346 static void 347 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 348 { 349 const char *devname = device_xname(sc->sc_dev); 350 u_int32_t cparams, addr, cap; 351 pcireg_t legsup; 352 int maxcap = 10; 353 int ms; 354 355 #ifdef EHCI_DEBUG 356 if (ehcidebug) 357 ehci_dump_caps(sc, pc, tag); 358 #endif 359 cparams = EREAD4(sc, EHCI_HCCPARAMS); 360 addr = EHCI_HCC_EECP(cparams); 361 while (addr != 0) { 362 cap = pci_conf_read(pc, tag, addr); 363 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 364 goto next; 365 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 366 /* Ask BIOS to give up ownership */ 367 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 368 legsup | EHCI_LEG_HC_OS_OWNED); 369 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 370 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 371 legsup = pci_conf_read(pc, tag, 372 addr + PCI_EHCI_USBLEGSUP); 373 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 374 break; 375 delay(1000); 376 } 377 if (ms == EHCI_MAX_BIOS_WAIT) { 378 aprint_normal("%s: BIOS refuses to give up " 379 "ownership, using force\n", devname); 380 pci_conf_write(pc, tag, 381 addr + PCI_EHCI_USBLEGSUP, 0); 382 } else 383 aprint_verbose("%s: BIOS has given up " 384 "ownership\n", devname); 385 } 386 387 /* Disable SMIs */ 388 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 389 EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD | 390 EHCI_LEG_EXT_SMI_OS_CHANGE); 391 392 next: 393 if (--maxcap < 0) { 394 aprint_normal("%s: broken extended capabilities " 395 "ignored\n", devname); 396 return; 397 } 398 addr = EHCI_CAP_GET_NEXT(cap); 399 } 400 401 } 402 403 static bool 404 ehci_pci_suspend(device_t dv PMF_FN_ARGS) 405 { 406 struct ehci_pci_softc *sc = device_private(dv); 407 408 ehci_suspend(dv PMF_FN_CALL); 409 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 410 411 return true; 412 } 413 414 static bool 415 ehci_pci_resume(device_t dv PMF_FN_ARGS) 416 { 417 struct ehci_pci_softc *sc = device_private(dv); 418 419 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 420 return ehci_resume(dv PMF_FN_CALL); 421 } 422 423 static int 424 ehci_sb700_match(struct pci_attach_args *pa) 425 { 426 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 427 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) 428 return 0; 429 430 switch (PCI_REVISION(pa->pa_class)) { 431 case 0x3a: 432 case 0x3b: 433 return 1; 434 } 435 436 return 0; 437 } 438 439 static int 440 ehci_apply_amd_quirks(struct ehci_pci_softc *sc) 441 { 442 pcireg_t value; 443 444 aprint_normal_dev(sc->sc.sc_dev, 445 "applying AMD SB600/SB700 USB freeze workaround\n"); 446 value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); 447 pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, 448 value | EHCI_SBx00_WORKAROUND_ENABLE); 449 450 return 0; 451 } 452 453 enum ehci_pci_quirk_flags 454 ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 455 { 456 int i; 457 458 for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { 459 if (vendor == ehci_pci_quirks[i].vendor && 460 product == ehci_pci_quirks[i].product) 461 return ehci_pci_quirks[i].quirks; 462 } 463 return 0; 464 } 465 466
Indexes created Sat Oct 11 16:09:52 GMT 2025