ehci_pci.c revision 1.40
1 /* $NetBSD: ehci_pci.c,v 1.40 2009/04/17 17:21:31 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.40 2009/04/17 17:21:31 dyoung Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 64 pcitag_t tag); 65 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 66 pcitag_t tag); 67 static bool ehci_pci_suspend(device_t PMF_FN_PROTO); 68 static bool ehci_pci_resume(device_t PMF_FN_PROTO); 69 70 struct ehci_pci_softc { 71 ehci_softc_t sc; 72 pci_chipset_tag_t sc_pc; 73 pcitag_t sc_tag; 74 void *sc_ih; /* interrupt vectoring */ 75 }; 76 77 #define EHCI_MAX_BIOS_WAIT 1000 /* ms */ 78 79 static int 80 ehci_pci_match(struct device *parent, struct cfdata *match, 81 void *aux) 82 { 83 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 84 85 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 86 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 87 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 88 return (1); 89 90 return (0); 91 } 92 93 static void 94 ehci_pci_attach(struct device *parent, struct device *self, void *aux) 95 { 96 struct ehci_pci_softc *sc = device_private(self); 97 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 98 pci_chipset_tag_t pc = pa->pa_pc; 99 pcitag_t tag = pa->pa_tag; 100 char const *intrstr; 101 pci_intr_handle_t ih; 102 pcireg_t csr; 103 const char *vendor; 104 const char *devname = device_xname(self); 105 char devinfo[256]; 106 usbd_status r; 107 int ncomp; 108 struct usb_pci *up; 109 110 sc->sc.sc_dev = self; 111 sc->sc.sc_bus.hci_private = sc; 112 113 aprint_naive(": USB controller\n"); 114 115 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 116 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 117 PCI_REVISION(pa->pa_class)); 118 119 /* Map I/O registers */ 120 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 121 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 122 aprint_error("%s: can't map memory space\n", devname); 123 return; 124 } 125 126 sc->sc_pc = pc; 127 sc->sc_tag = tag; 128 sc->sc.sc_bus.dmatag = pa->pa_dmat; 129 130 /* Enable the device. */ 131 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 132 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 133 csr | PCI_COMMAND_MASTER_ENABLE); 134 135 /* Disable interrupts, so we don't get any spurious ones. */ 136 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 137 DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs)); 138 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 139 140 /* Map and establish the interrupt. */ 141 if (pci_intr_map(pa, &ih)) { 142 aprint_error("%s: couldn't map interrupt\n", devname); 143 return; 144 } 145 intrstr = pci_intr_string(pc, ih); 146 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 147 if (sc->sc_ih == NULL) { 148 aprint_error("%s: couldn't establish interrupt", devname); 149 if (intrstr != NULL) 150 aprint_normal(" at %s", intrstr); 151 aprint_normal("\n"); 152 return; 153 } 154 aprint_normal("%s: interrupting at %s\n", devname, intrstr); 155 156 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 157 case PCI_USBREV_PRE_1_0: 158 case PCI_USBREV_1_0: 159 case PCI_USBREV_1_1: 160 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 161 aprint_verbose("%s: pre-2.0 USB rev\n", devname); 162 return; 163 case PCI_USBREV_2_0: 164 sc->sc.sc_bus.usbrev = USBREV_2_0; 165 break; 166 default: 167 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 168 break; 169 } 170 171 /* Figure out vendor for root hub descriptor. */ 172 vendor = pci_findvendor(pa->pa_id); 173 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 174 if (vendor) 175 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 176 else 177 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 178 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 179 180 /* Enable workaround for dropped interrupts as required */ 181 switch (sc->sc.sc_id_vendor) { 182 case PCI_VENDOR_ATI: 183 case PCI_VENDOR_VIATECH: 184 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 185 aprint_normal("%s: dropped intr workaround enabled\n", devname); 186 break; 187 default: 188 break; 189 } 190 191 /* 192 * Find companion controllers. According to the spec they always 193 * have lower function numbers so they should be enumerated already. 194 */ 195 ncomp = 0; 196 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 197 if (up->bus == pa->pa_bus && up->device == pa->pa_device) { 198 DPRINTF(("ehci_pci_attach: companion %s\n", 199 device_xname(up->usb))); 200 sc->sc.sc_comps[ncomp++] = up->usb; 201 if (ncomp >= EHCI_COMPANION_MAX) 202 break; 203 } 204 } 205 sc->sc.sc_ncomp = ncomp; 206 207 ehci_get_ownership(&sc->sc, pc, tag); 208 209 r = ehci_init(&sc->sc); 210 if (r != USBD_NORMAL_COMPLETION) { 211 aprint_error("%s: init failed, error=%d\n", devname, r); 212 return; 213 } 214 215 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 216 ehci_shutdown)) 217 aprint_error_dev(self, "couldn't establish power handler\n"); 218 219 /* Attach usb device. */ 220 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 221 } 222 223 static int 224 ehci_pci_detach(device_ptr_t self, int flags) 225 { 226 struct ehci_pci_softc *sc = device_private(self); 227 int rv; 228 229 pmf_device_deregister(self); 230 rv = ehci_detach(&sc->sc, flags); 231 if (rv) 232 return (rv); 233 234 /* disable interrupts */ 235 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 236 /* XXX grotty hack to flush the write */ 237 EOREAD2(&sc->sc, EHCI_USBINTR); 238 239 if (sc->sc_ih != NULL) { 240 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 241 sc->sc_ih = NULL; 242 } 243 if (sc->sc.sc_size) { 244 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 245 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 246 sc->sc.sc_size = 0; 247 } 248 249 return (0); 250 } 251 252 CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 253 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 254 ehci_childdet, DVF_DETACH_SHUTDOWN); 255 256 #ifdef EHCI_DEBUG 257 static void 258 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 259 { 260 u_int32_t cparams, legctlsts, addr, cap, id; 261 int maxdump = 10; 262 263 cparams = EREAD4(sc, EHCI_HCCPARAMS); 264 addr = EHCI_HCC_EECP(cparams); 265 while (addr != 0) { 266 cap = pci_conf_read(pc, tag, addr); 267 id = EHCI_CAP_GET_ID(cap); 268 switch (id) { 269 case EHCI_CAP_ID_LEGACY: 270 legctlsts = pci_conf_read(pc, tag, 271 addr + PCI_EHCI_USBLEGCTLSTS); 272 printf("ehci_dump_caps: legsup=0x%08x " 273 "legctlsts=0x%08x\n", cap, legctlsts); 274 break; 275 default: 276 printf("ehci_dump_caps: cap=0x%08x\n", cap); 277 break; 278 } 279 if (--maxdump < 0) 280 break; 281 addr = EHCI_CAP_GET_NEXT(cap); 282 } 283 } 284 #endif 285 286 static void 287 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 288 { 289 const char *devname = device_xname(sc->sc_dev); 290 u_int32_t cparams, addr, cap; 291 pcireg_t legsup; 292 int maxcap = 10; 293 294 cparams = EREAD4(sc, EHCI_HCCPARAMS); 295 addr = EHCI_HCC_EECP(cparams); 296 while (addr != 0) { 297 cap = pci_conf_read(pc, tag, addr); 298 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 299 goto next; 300 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 301 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 302 legsup & ~EHCI_LEG_HC_OS_OWNED); 303 304 next: 305 if (--maxcap < 0) { 306 aprint_normal("%s: broken extended capabilities " 307 "ignored\n", devname); 308 return; 309 } 310 addr = EHCI_CAP_GET_NEXT(cap); 311 } 312 } 313 314 static void 315 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 316 { 317 const char *devname = device_xname(sc->sc_dev); 318 u_int32_t cparams, addr, cap; 319 pcireg_t legsup; 320 int maxcap = 10; 321 int ms; 322 323 #ifdef EHCI_DEBUG 324 if (ehcidebug) 325 ehci_dump_caps(sc, pc, tag); 326 #endif 327 cparams = EREAD4(sc, EHCI_HCCPARAMS); 328 addr = EHCI_HCC_EECP(cparams); 329 while (addr != 0) { 330 cap = pci_conf_read(pc, tag, addr); 331 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 332 goto next; 333 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 334 /* Ask BIOS to give up ownership */ 335 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 336 legsup | EHCI_LEG_HC_OS_OWNED); 337 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 338 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 339 legsup = pci_conf_read(pc, tag, 340 addr + PCI_EHCI_USBLEGSUP); 341 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 342 break; 343 delay(1000); 344 } 345 if (ms == EHCI_MAX_BIOS_WAIT) { 346 aprint_normal("%s: BIOS refuses to give up " 347 "ownership, using force\n", devname); 348 pci_conf_write(pc, tag, 349 addr + PCI_EHCI_USBLEGSUP, 0); 350 } else 351 aprint_verbose("%s: BIOS has given up " 352 "ownership\n", devname); 353 } 354 355 /* Disable SMIs */ 356 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 357 EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD | 358 EHCI_LEG_EXT_SMI_OS_CHANGE); 359 360 next: 361 if (--maxcap < 0) { 362 aprint_normal("%s: broken extended capabilities " 363 "ignored\n", devname); 364 return; 365 } 366 addr = EHCI_CAP_GET_NEXT(cap); 367 } 368 369 } 370 371 static bool 372 ehci_pci_suspend(device_t dv PMF_FN_ARGS) 373 { 374 struct ehci_pci_softc *sc = device_private(dv); 375 376 ehci_suspend(dv PMF_FN_CALL); 377 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 378 379 return true; 380 } 381 382 static bool 383 ehci_pci_resume(device_t dv PMF_FN_ARGS) 384 { 385 struct ehci_pci_softc *sc = device_private(dv); 386 387 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 388 return ehci_resume(dv PMF_FN_CALL); 389 } 390
Indexes created Tue Sep 30 11:09:46 GMT 2025