ehci_pci.c revision 1.42
1 /* $NetBSD: ehci_pci.c,v 1.42 2009/04/17 20:32:27 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.42 2009/04/17 20:32:27 christos Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 64 pcitag_t tag); 65 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 66 pcitag_t tag); 67 static bool ehci_pci_suspend(device_t PMF_FN_PROTO); 68 static bool ehci_pci_resume(device_t PMF_FN_PROTO); 69 70 struct ehci_pci_softc { 71 ehci_softc_t sc; 72 pci_chipset_tag_t sc_pc; 73 pcitag_t sc_tag; 74 void *sc_ih; /* interrupt vectoring */ 75 }; 76 77 #define EHCI_MAX_BIOS_WAIT 1000 /* ms */ 78 79 static int 80 ehci_pci_match(device_t parent, cfdata_t match, void *aux) 81 { 82 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 83 84 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 85 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 86 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 87 return 1; 88 89 return 0; 90 } 91 92 static void 93 ehci_pci_attach(device_t parent, device_t self, void *aux) 94 { 95 struct ehci_pci_softc *sc = device_private(self); 96 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 97 pci_chipset_tag_t pc = pa->pa_pc; 98 pcitag_t tag = pa->pa_tag; 99 char const *intrstr; 100 pci_intr_handle_t ih; 101 pcireg_t csr; 102 const char *vendor; 103 const char *devname = device_xname(self); 104 char devinfo[256]; 105 usbd_status r; 106 int ncomp; 107 struct usb_pci *up; 108 109 sc->sc.sc_dev = self; 110 sc->sc.sc_bus.hci_private = sc; 111 112 aprint_naive(": USB controller\n"); 113 114 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 115 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 116 PCI_REVISION(pa->pa_class)); 117 118 /* Map I/O registers */ 119 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 120 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 121 aprint_error("%s: can't map memory space\n", devname); 122 return; 123 } 124 125 sc->sc_pc = pc; 126 sc->sc_tag = tag; 127 sc->sc.sc_bus.dmatag = pa->pa_dmat; 128 129 /* Enable the device. */ 130 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 131 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 132 csr | PCI_COMMAND_MASTER_ENABLE); 133 134 /* Disable interrupts, so we don't get any spurious ones. */ 135 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 136 DPRINTF(("%s: offs=%d\n", devname, sc->sc.sc_offs)); 137 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 138 139 /* Map and establish the interrupt. */ 140 if (pci_intr_map(pa, &ih)) { 141 aprint_error("%s: couldn't map interrupt\n", devname); 142 return; 143 } 144 intrstr = pci_intr_string(pc, ih); 145 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 146 if (sc->sc_ih == NULL) { 147 aprint_error("%s: couldn't establish interrupt", devname); 148 if (intrstr != NULL) 149 aprint_normal(" at %s", intrstr); 150 aprint_normal("\n"); 151 return; 152 } 153 aprint_normal("%s: interrupting at %s\n", devname, intrstr); 154 155 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 156 case PCI_USBREV_PRE_1_0: 157 case PCI_USBREV_1_0: 158 case PCI_USBREV_1_1: 159 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 160 aprint_verbose("%s: pre-2.0 USB rev\n", devname); 161 return; 162 case PCI_USBREV_2_0: 163 sc->sc.sc_bus.usbrev = USBREV_2_0; 164 break; 165 default: 166 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 167 break; 168 } 169 170 /* Figure out vendor for root hub descriptor. */ 171 vendor = pci_findvendor(pa->pa_id); 172 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 173 if (vendor) 174 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 175 else 176 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 177 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 178 179 /* Enable workaround for dropped interrupts as required */ 180 switch (sc->sc.sc_id_vendor) { 181 case PCI_VENDOR_ATI: 182 case PCI_VENDOR_VIATECH: 183 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 184 aprint_normal("%s: dropped intr workaround enabled\n", devname); 185 break; 186 default: 187 break; 188 } 189 190 /* 191 * Find companion controllers. According to the spec they always 192 * have lower function numbers so they should be enumerated already. 193 */ 194 ncomp = 0; 195 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 196 if (up->bus == pa->pa_bus && up->device == pa->pa_device) { 197 DPRINTF(("ehci_pci_attach: companion %s\n", 198 device_xname(up->usb))); 199 sc->sc.sc_comps[ncomp++] = up->usb; 200 if (ncomp >= EHCI_COMPANION_MAX) 201 break; 202 } 203 } 204 sc->sc.sc_ncomp = ncomp; 205 206 ehci_get_ownership(&sc->sc, pc, tag); 207 208 r = ehci_init(&sc->sc); 209 if (r != USBD_NORMAL_COMPLETION) { 210 aprint_error("%s: init failed, error=%d\n", devname, r); 211 return; 212 } 213 214 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 215 ehci_shutdown)) 216 aprint_error_dev(self, "couldn't establish power handler\n"); 217 218 /* Attach usb device. */ 219 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 220 } 221 222 static int 223 ehci_pci_detach(device_t self, int flags) 224 { 225 struct ehci_pci_softc *sc = device_private(self); 226 int rv; 227 228 pmf_device_deregister(self); 229 rv = ehci_detach(&sc->sc, flags); 230 if (rv) 231 return rv; 232 233 /* disable interrupts */ 234 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 235 /* XXX grotty hack to flush the write */ 236 (void)EOREAD2(&sc->sc, EHCI_USBINTR); 237 238 if (sc->sc_ih != NULL) { 239 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 240 sc->sc_ih = NULL; 241 } 242 if (sc->sc.sc_size) { 243 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 244 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 245 sc->sc.sc_size = 0; 246 } 247 248 return 0; 249 } 250 251 CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 252 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 253 ehci_childdet, DVF_DETACH_SHUTDOWN); 254 255 #ifdef EHCI_DEBUG 256 static void 257 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 258 { 259 u_int32_t cparams, legctlsts, addr, cap, id; 260 int maxdump = 10; 261 262 cparams = EREAD4(sc, EHCI_HCCPARAMS); 263 addr = EHCI_HCC_EECP(cparams); 264 while (addr != 0) { 265 cap = pci_conf_read(pc, tag, addr); 266 id = EHCI_CAP_GET_ID(cap); 267 switch (id) { 268 case EHCI_CAP_ID_LEGACY: 269 legctlsts = pci_conf_read(pc, tag, 270 addr + PCI_EHCI_USBLEGCTLSTS); 271 printf("ehci_dump_caps: legsup=0x%08x " 272 "legctlsts=0x%08x\n", cap, legctlsts); 273 break; 274 default: 275 printf("ehci_dump_caps: cap=0x%08x\n", cap); 276 break; 277 } 278 if (--maxdump < 0) 279 break; 280 addr = EHCI_CAP_GET_NEXT(cap); 281 } 282 } 283 #endif 284 285 static void 286 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 287 { 288 const char *devname = device_xname(sc->sc_dev); 289 u_int32_t cparams, addr, cap; 290 pcireg_t legsup; 291 int maxcap = 10; 292 293 cparams = EREAD4(sc, EHCI_HCCPARAMS); 294 addr = EHCI_HCC_EECP(cparams); 295 while (addr != 0) { 296 cap = pci_conf_read(pc, tag, addr); 297 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 298 goto next; 299 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 300 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 301 legsup & ~EHCI_LEG_HC_OS_OWNED); 302 303 next: 304 if (--maxcap < 0) { 305 aprint_normal("%s: broken extended capabilities " 306 "ignored\n", devname); 307 return; 308 } 309 addr = EHCI_CAP_GET_NEXT(cap); 310 } 311 } 312 313 static void 314 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 315 { 316 const char *devname = device_xname(sc->sc_dev); 317 u_int32_t cparams, addr, cap; 318 pcireg_t legsup; 319 int maxcap = 10; 320 int ms; 321 322 #ifdef EHCI_DEBUG 323 if (ehcidebug) 324 ehci_dump_caps(sc, pc, tag); 325 #endif 326 cparams = EREAD4(sc, EHCI_HCCPARAMS); 327 addr = EHCI_HCC_EECP(cparams); 328 while (addr != 0) { 329 cap = pci_conf_read(pc, tag, addr); 330 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 331 goto next; 332 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 333 /* Ask BIOS to give up ownership */ 334 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 335 legsup | EHCI_LEG_HC_OS_OWNED); 336 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 337 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 338 legsup = pci_conf_read(pc, tag, 339 addr + PCI_EHCI_USBLEGSUP); 340 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 341 break; 342 delay(1000); 343 } 344 if (ms == EHCI_MAX_BIOS_WAIT) { 345 aprint_normal("%s: BIOS refuses to give up " 346 "ownership, using force\n", devname); 347 pci_conf_write(pc, tag, 348 addr + PCI_EHCI_USBLEGSUP, 0); 349 } else 350 aprint_verbose("%s: BIOS has given up " 351 "ownership\n", devname); 352 } 353 354 /* Disable SMIs */ 355 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 356 EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD | 357 EHCI_LEG_EXT_SMI_OS_CHANGE); 358 359 next: 360 if (--maxcap < 0) { 361 aprint_normal("%s: broken extended capabilities " 362 "ignored\n", devname); 363 return; 364 } 365 addr = EHCI_CAP_GET_NEXT(cap); 366 } 367 368 } 369 370 static bool 371 ehci_pci_suspend(device_t dv PMF_FN_ARGS) 372 { 373 struct ehci_pci_softc *sc = device_private(dv); 374 375 ehci_suspend(dv PMF_FN_CALL); 376 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 377 378 return true; 379 } 380 381 static bool 382 ehci_pci_resume(device_t dv PMF_FN_ARGS) 383 { 384 struct ehci_pci_softc *sc = device_private(dv); 385 386 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 387 return ehci_resume(dv PMF_FN_CALL); 388 } 389
Indexes created Sun Sep 28 07:09:56 GMT 2025