ehci_pci.c revision 1.43
1 /* $NetBSD: ehci_pci.c,v 1.43 2009/04/26 09:12:33 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.43 2009/04/26 09:12:33 cegger Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 64 pcitag_t tag); 65 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 66 pcitag_t tag); 67 static bool ehci_pci_suspend(device_t PMF_FN_PROTO); 68 static bool ehci_pci_resume(device_t PMF_FN_PROTO); 69 70 struct ehci_pci_softc { 71 ehci_softc_t sc; 72 pci_chipset_tag_t sc_pc; 73 pcitag_t sc_tag; 74 void *sc_ih; /* interrupt vectoring */ 75 }; 76 77 #define EHCI_MAX_BIOS_WAIT 1000 /* ms */ 78 79 static int 80 ehci_pci_match(device_t parent, cfdata_t match, void *aux) 81 { 82 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 83 84 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 85 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 86 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 87 return 1; 88 89 return 0; 90 } 91 92 static void 93 ehci_pci_attach(device_t parent, device_t self, void *aux) 94 { 95 struct ehci_pci_softc *sc = device_private(self); 96 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 97 pci_chipset_tag_t pc = pa->pa_pc; 98 pcitag_t tag = pa->pa_tag; 99 char const *intrstr; 100 pci_intr_handle_t ih; 101 pcireg_t csr; 102 const char *vendor; 103 char devinfo[256]; 104 usbd_status r; 105 int ncomp; 106 struct usb_pci *up; 107 108 sc->sc.sc_dev = self; 109 sc->sc.sc_bus.hci_private = sc; 110 111 aprint_naive(": USB controller\n"); 112 113 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 114 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 115 PCI_REVISION(pa->pa_class)); 116 117 /* Map I/O registers */ 118 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 119 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 120 sc->sc.sc_size = 0; 121 aprint_error_dev(self, "can't map memory space\n"); 122 return; 123 } 124 125 /* Disable interrupts, so we don't get any spurious ones. */ 126 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 127 DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs)); 128 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 129 130 sc->sc_pc = pc; 131 sc->sc_tag = tag; 132 sc->sc.sc_bus.dmatag = pa->pa_dmat; 133 134 /* Enable the device. */ 135 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 136 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 137 csr | PCI_COMMAND_MASTER_ENABLE); 138 139 /* Map and establish the interrupt. */ 140 if (pci_intr_map(pa, &ih)) { 141 aprint_error_dev(self, "couldn't map interrupt\n"); 142 goto fail; 143 } 144 145 /* 146 * Allocate IRQ 147 */ 148 intrstr = pci_intr_string(pc, ih); 149 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 150 if (sc->sc_ih == NULL) { 151 aprint_error_dev(self, "couldn't establish interrupt"); 152 if (intrstr != NULL) 153 aprint_error(" at %s", intrstr); 154 aprint_error("\n"); 155 return; 156 } 157 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 158 159 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 160 case PCI_USBREV_PRE_1_0: 161 case PCI_USBREV_1_0: 162 case PCI_USBREV_1_1: 163 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 164 aprint_verbose_dev(self, "pre-2.0 USB rev\n"); 165 return; 166 case PCI_USBREV_2_0: 167 sc->sc.sc_bus.usbrev = USBREV_2_0; 168 break; 169 default: 170 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 171 break; 172 } 173 174 /* Figure out vendor for root hub descriptor. */ 175 vendor = pci_findvendor(pa->pa_id); 176 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 177 if (vendor) 178 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 179 else 180 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 181 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 182 183 /* Enable workaround for dropped interrupts as required */ 184 switch (sc->sc.sc_id_vendor) { 185 case PCI_VENDOR_ATI: 186 case PCI_VENDOR_VIATECH: 187 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 188 aprint_normal_dev(self, "dropped intr workaround enabled\n"); 189 break; 190 default: 191 break; 192 } 193 194 /* 195 * Find companion controllers. According to the spec they always 196 * have lower function numbers so they should be enumerated already. 197 */ 198 ncomp = 0; 199 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 200 if (up->bus == pa->pa_bus && up->device == pa->pa_device) { 201 DPRINTF(("ehci_pci_attach: companion %s\n", 202 device_xname(up->usb))); 203 sc->sc.sc_comps[ncomp++] = up->usb; 204 if (ncomp >= EHCI_COMPANION_MAX) 205 break; 206 } 207 } 208 sc->sc.sc_ncomp = ncomp; 209 210 ehci_get_ownership(&sc->sc, pc, tag); 211 212 r = ehci_init(&sc->sc); 213 if (r != USBD_NORMAL_COMPLETION) { 214 aprint_error_dev(self, "init failed, error=%d\n", r); 215 goto fail; 216 } 217 218 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 219 ehci_shutdown)) 220 aprint_error_dev(self, "couldn't establish power handler\n"); 221 222 /* Attach usb device. */ 223 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 224 return; 225 226 fail: 227 if (sc->sc_ih) { 228 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 229 sc->sc_ih = NULL; 230 } 231 if (sc->sc.sc_size) { 232 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 233 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 234 sc->sc.sc_size = 0; 235 } 236 return; 237 } 238 239 static int 240 ehci_pci_detach(device_t self, int flags) 241 { 242 struct ehci_pci_softc *sc = device_private(self); 243 int rv; 244 245 pmf_device_deregister(self); 246 rv = ehci_detach(&sc->sc, flags); 247 if (rv) 248 return rv; 249 250 /* disable interrupts */ 251 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 252 /* XXX grotty hack to flush the write */ 253 (void)EOREAD2(&sc->sc, EHCI_USBINTR); 254 255 if (sc->sc_ih != NULL) { 256 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 257 sc->sc_ih = NULL; 258 } 259 if (sc->sc.sc_size) { 260 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 261 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 262 sc->sc.sc_size = 0; 263 } 264 265 return 0; 266 } 267 268 CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 269 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 270 ehci_childdet, DVF_DETACH_SHUTDOWN); 271 272 #ifdef EHCI_DEBUG 273 static void 274 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 275 { 276 u_int32_t cparams, legctlsts, addr, cap, id; 277 int maxdump = 10; 278 279 cparams = EREAD4(sc, EHCI_HCCPARAMS); 280 addr = EHCI_HCC_EECP(cparams); 281 while (addr != 0) { 282 cap = pci_conf_read(pc, tag, addr); 283 id = EHCI_CAP_GET_ID(cap); 284 switch (id) { 285 case EHCI_CAP_ID_LEGACY: 286 legctlsts = pci_conf_read(pc, tag, 287 addr + PCI_EHCI_USBLEGCTLSTS); 288 printf("ehci_dump_caps: legsup=0x%08x " 289 "legctlsts=0x%08x\n", cap, legctlsts); 290 break; 291 default: 292 printf("ehci_dump_caps: cap=0x%08x\n", cap); 293 break; 294 } 295 if (--maxdump < 0) 296 break; 297 addr = EHCI_CAP_GET_NEXT(cap); 298 } 299 } 300 #endif 301 302 static void 303 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 304 { 305 const char *devname = device_xname(sc->sc_dev); 306 u_int32_t cparams, addr, cap; 307 pcireg_t legsup; 308 int maxcap = 10; 309 310 cparams = EREAD4(sc, EHCI_HCCPARAMS); 311 addr = EHCI_HCC_EECP(cparams); 312 while (addr != 0) { 313 cap = pci_conf_read(pc, tag, addr); 314 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 315 goto next; 316 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 317 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 318 legsup & ~EHCI_LEG_HC_OS_OWNED); 319 320 next: 321 if (--maxcap < 0) { 322 aprint_normal("%s: broken extended capabilities " 323 "ignored\n", devname); 324 return; 325 } 326 addr = EHCI_CAP_GET_NEXT(cap); 327 } 328 } 329 330 static void 331 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 332 { 333 const char *devname = device_xname(sc->sc_dev); 334 u_int32_t cparams, addr, cap; 335 pcireg_t legsup; 336 int maxcap = 10; 337 int ms; 338 339 #ifdef EHCI_DEBUG 340 if (ehcidebug) 341 ehci_dump_caps(sc, pc, tag); 342 #endif 343 cparams = EREAD4(sc, EHCI_HCCPARAMS); 344 addr = EHCI_HCC_EECP(cparams); 345 while (addr != 0) { 346 cap = pci_conf_read(pc, tag, addr); 347 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 348 goto next; 349 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 350 /* Ask BIOS to give up ownership */ 351 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 352 legsup | EHCI_LEG_HC_OS_OWNED); 353 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 354 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 355 legsup = pci_conf_read(pc, tag, 356 addr + PCI_EHCI_USBLEGSUP); 357 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 358 break; 359 delay(1000); 360 } 361 if (ms == EHCI_MAX_BIOS_WAIT) { 362 aprint_normal("%s: BIOS refuses to give up " 363 "ownership, using force\n", devname); 364 pci_conf_write(pc, tag, 365 addr + PCI_EHCI_USBLEGSUP, 0); 366 } else 367 aprint_verbose("%s: BIOS has given up " 368 "ownership\n", devname); 369 } 370 371 /* Disable SMIs */ 372 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 373 EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD | 374 EHCI_LEG_EXT_SMI_OS_CHANGE); 375 376 next: 377 if (--maxcap < 0) { 378 aprint_normal("%s: broken extended capabilities " 379 "ignored\n", devname); 380 return; 381 } 382 addr = EHCI_CAP_GET_NEXT(cap); 383 } 384 385 } 386 387 static bool 388 ehci_pci_suspend(device_t dv PMF_FN_ARGS) 389 { 390 struct ehci_pci_softc *sc = device_private(dv); 391 392 ehci_suspend(dv PMF_FN_CALL); 393 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 394 395 return true; 396 } 397 398 static bool 399 ehci_pci_resume(device_t dv PMF_FN_ARGS) 400 { 401 struct ehci_pci_softc *sc = device_private(dv); 402 403 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 404 return ehci_resume(dv PMF_FN_CALL); 405 } 406
Indexes created Sun Sep 28 16:09:52 GMT 2025