ehci_pci.c revision 1.51
1 /* $NetBSD: ehci_pci.c,v 1.51 2011/04/04 20:37:56 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.51 2011/04/04 20:37:56 dyoung Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 enum ehci_pci_quirk_flags { 64 EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ 65 EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ 66 }; 67 68 static const struct pci_quirkdata ehci_pci_quirks[] = { 69 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, 70 EHCI_PCI_QUIRK_AMD_SB600 }, 71 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, 72 EHCI_PCI_QUIRK_AMD_SB700 }, 73 }; 74 75 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 76 pcitag_t tag); 77 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 78 pcitag_t tag); 79 static bool ehci_pci_suspend(device_t, const pmf_qual_t *); 80 static bool ehci_pci_resume(device_t, const pmf_qual_t *); 81 82 struct ehci_pci_softc { 83 ehci_softc_t sc; 84 pci_chipset_tag_t sc_pc; 85 pcitag_t sc_tag; 86 void *sc_ih; /* interrupt vectoring */ 87 }; 88 89 static int ehci_sb700_match(const struct pci_attach_args *pa); 90 static int ehci_apply_amd_quirks(struct ehci_pci_softc *sc); 91 enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, 92 pci_product_id_t); 93 94 #define EHCI_MAX_BIOS_WAIT 1000 /* ms */ 95 #define EHCI_SBx00_WORKAROUND_REG 0x50 96 #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) 97 98 99 static int 100 ehci_pci_match(device_t parent, cfdata_t match, void *aux) 101 { 102 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 103 104 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 105 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 106 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 107 return 1; 108 109 return 0; 110 } 111 112 static void 113 ehci_pci_attach(device_t parent, device_t self, void *aux) 114 { 115 struct ehci_pci_softc *sc = device_private(self); 116 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 117 pci_chipset_tag_t pc = pa->pa_pc; 118 pcitag_t tag = pa->pa_tag; 119 char const *intrstr; 120 pci_intr_handle_t ih; 121 pcireg_t csr; 122 const char *vendor; 123 char devinfo[256]; 124 usbd_status r; 125 int ncomp; 126 struct usb_pci *up; 127 int quirk; 128 129 sc->sc.sc_dev = self; 130 sc->sc.sc_bus.hci_private = sc; 131 132 aprint_naive(": USB controller\n"); 133 134 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 135 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 136 PCI_REVISION(pa->pa_class)); 137 138 /* Check for quirks */ 139 quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 140 PCI_PRODUCT(pa->pa_id)); 141 142 /* Map I/O registers */ 143 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 144 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 145 sc->sc.sc_size = 0; 146 aprint_error_dev(self, "can't map memory space\n"); 147 return; 148 } 149 150 /* Disable interrupts, so we don't get any spurious ones. */ 151 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 152 DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs)); 153 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 154 155 sc->sc_pc = pc; 156 sc->sc_tag = tag; 157 sc->sc.sc_bus.dmatag = pa->pa_dmat; 158 159 /* Handle quirks */ 160 switch (quirk) { 161 case EHCI_PCI_QUIRK_AMD_SB600: 162 ehci_apply_amd_quirks(sc); 163 break; 164 case EHCI_PCI_QUIRK_AMD_SB700: 165 if (pci_find_device(NULL, ehci_sb700_match)) 166 ehci_apply_amd_quirks(sc); 167 break; 168 } 169 170 /* Enable the device. */ 171 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 172 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 173 csr | PCI_COMMAND_MASTER_ENABLE); 174 175 /* Map and establish the interrupt. */ 176 if (pci_intr_map(pa, &ih)) { 177 aprint_error_dev(self, "couldn't map interrupt\n"); 178 goto fail; 179 } 180 181 /* 182 * Allocate IRQ 183 */ 184 intrstr = pci_intr_string(pc, ih); 185 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 186 if (sc->sc_ih == NULL) { 187 aprint_error_dev(self, "couldn't establish interrupt"); 188 if (intrstr != NULL) 189 aprint_error(" at %s", intrstr); 190 aprint_error("\n"); 191 return; 192 } 193 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 194 195 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 196 case PCI_USBREV_PRE_1_0: 197 case PCI_USBREV_1_0: 198 case PCI_USBREV_1_1: 199 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 200 aprint_verbose_dev(self, "pre-2.0 USB rev\n"); 201 return; 202 case PCI_USBREV_2_0: 203 sc->sc.sc_bus.usbrev = USBREV_2_0; 204 break; 205 default: 206 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 207 break; 208 } 209 210 /* Figure out vendor for root hub descriptor. */ 211 vendor = pci_findvendor(pa->pa_id); 212 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 213 if (vendor) 214 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 215 else 216 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 217 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 218 219 /* Enable workaround for dropped interrupts as required */ 220 switch (sc->sc.sc_id_vendor) { 221 case PCI_VENDOR_ATI: 222 case PCI_VENDOR_VIATECH: 223 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 224 aprint_normal_dev(self, "dropped intr workaround enabled\n"); 225 break; 226 default: 227 break; 228 } 229 230 /* 231 * Find companion controllers. According to the spec they always 232 * have lower function numbers so they should be enumerated already. 233 */ 234 const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS)); 235 KASSERT(maxncomp <= EHCI_COMPANION_MAX); 236 ncomp = 0; 237 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 238 if (up->bus == pa->pa_bus && up->device == pa->pa_device 239 && !up->claimed) { 240 DPRINTF(("ehci_pci_attach: companion %s\n", 241 device_xname(up->usb))); 242 sc->sc.sc_comps[ncomp++] = up->usb; 243 up->claimed = true; 244 if (ncomp == maxncomp) 245 break; 246 } 247 } 248 sc->sc.sc_ncomp = ncomp; 249 250 ehci_get_ownership(&sc->sc, pc, tag); 251 252 r = ehci_init(&sc->sc); 253 if (r != USBD_NORMAL_COMPLETION) { 254 aprint_error_dev(self, "init failed, error=%d\n", r); 255 goto fail; 256 } 257 258 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 259 ehci_shutdown)) 260 aprint_error_dev(self, "couldn't establish power handler\n"); 261 262 /* Attach usb device. */ 263 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 264 return; 265 266 fail: 267 if (sc->sc_ih) { 268 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 269 sc->sc_ih = NULL; 270 } 271 if (sc->sc.sc_size) { 272 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 273 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 274 sc->sc.sc_size = 0; 275 } 276 return; 277 } 278 279 static int 280 ehci_pci_detach(device_t self, int flags) 281 { 282 struct ehci_pci_softc *sc = device_private(self); 283 int rv; 284 285 pmf_device_deregister(self); 286 rv = ehci_detach(&sc->sc, flags); 287 if (rv) 288 return rv; 289 290 /* disable interrupts */ 291 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 292 /* XXX grotty hack to flush the write */ 293 (void)EOREAD2(&sc->sc, EHCI_USBINTR); 294 295 if (sc->sc_ih != NULL) { 296 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 297 sc->sc_ih = NULL; 298 } 299 if (sc->sc.sc_size) { 300 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 301 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 302 sc->sc.sc_size = 0; 303 } 304 305 return 0; 306 } 307 308 CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 309 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 310 ehci_childdet, DVF_DETACH_SHUTDOWN); 311 312 #ifdef EHCI_DEBUG 313 static void 314 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 315 { 316 uint32_t cparams, legctlsts, addr, cap, id; 317 int maxdump = 10; 318 319 cparams = EREAD4(sc, EHCI_HCCPARAMS); 320 addr = EHCI_HCC_EECP(cparams); 321 while (addr != 0) { 322 cap = pci_conf_read(pc, tag, addr); 323 id = EHCI_CAP_GET_ID(cap); 324 switch (id) { 325 case EHCI_CAP_ID_LEGACY: 326 legctlsts = pci_conf_read(pc, tag, 327 addr + PCI_EHCI_USBLEGCTLSTS); 328 printf("ehci_dump_caps: legsup=0x%08x " 329 "legctlsts=0x%08x\n", cap, legctlsts); 330 break; 331 default: 332 printf("ehci_dump_caps: cap=0x%08x\n", cap); 333 break; 334 } 335 if (--maxdump < 0) 336 break; 337 addr = EHCI_CAP_GET_NEXT(cap); 338 } 339 } 340 #endif 341 342 static void 343 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 344 { 345 const char *devname = device_xname(sc->sc_dev); 346 uint32_t cparams, addr, cap; 347 pcireg_t legsup; 348 int maxcap = 10; 349 350 cparams = EREAD4(sc, EHCI_HCCPARAMS); 351 addr = EHCI_HCC_EECP(cparams); 352 while (addr != 0) { 353 cap = pci_conf_read(pc, tag, addr); 354 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 355 goto next; 356 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 357 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 358 legsup & ~EHCI_LEG_HC_OS_OWNED); 359 360 next: 361 if (--maxcap < 0) { 362 aprint_normal("%s: broken extended capabilities " 363 "ignored\n", devname); 364 return; 365 } 366 addr = EHCI_CAP_GET_NEXT(cap); 367 } 368 } 369 370 static void 371 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 372 { 373 const char *devname = device_xname(sc->sc_dev); 374 uint32_t cparams, addr, cap; 375 pcireg_t legsup; 376 int maxcap = 10; 377 int ms; 378 379 #ifdef EHCI_DEBUG 380 if (ehcidebug) 381 ehci_dump_caps(sc, pc, tag); 382 #endif 383 cparams = EREAD4(sc, EHCI_HCCPARAMS); 384 addr = EHCI_HCC_EECP(cparams); 385 while (addr != 0) { 386 cap = pci_conf_read(pc, tag, addr); 387 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 388 goto next; 389 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 390 /* Ask BIOS to give up ownership */ 391 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 392 legsup | EHCI_LEG_HC_OS_OWNED); 393 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 394 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 395 legsup = pci_conf_read(pc, tag, 396 addr + PCI_EHCI_USBLEGSUP); 397 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 398 break; 399 delay(1000); 400 } 401 if (ms == EHCI_MAX_BIOS_WAIT) { 402 aprint_normal("%s: BIOS refuses to give up " 403 "ownership, using force\n", devname); 404 pci_conf_write(pc, tag, 405 addr + PCI_EHCI_USBLEGSUP, 0); 406 } else 407 aprint_verbose("%s: BIOS has given up " 408 "ownership\n", devname); 409 } 410 411 /* Disable SMIs */ 412 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 413 EHCI_LEG_EXT_SMI_BAR | EHCI_LEG_EXT_SMI_PCICMD | 414 EHCI_LEG_EXT_SMI_OS_CHANGE); 415 416 next: 417 if (--maxcap < 0) { 418 aprint_normal("%s: broken extended capabilities " 419 "ignored\n", devname); 420 return; 421 } 422 addr = EHCI_CAP_GET_NEXT(cap); 423 } 424 425 } 426 427 static bool 428 ehci_pci_suspend(device_t dv, const pmf_qual_t *qual) 429 { 430 struct ehci_pci_softc *sc = device_private(dv); 431 432 ehci_suspend(dv, qual); 433 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 434 435 return true; 436 } 437 438 static bool 439 ehci_pci_resume(device_t dv, const pmf_qual_t *qual) 440 { 441 struct ehci_pci_softc *sc = device_private(dv); 442 443 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 444 return ehci_resume(dv, qual); 445 } 446 447 static int 448 ehci_sb700_match(const struct pci_attach_args *pa) 449 { 450 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 451 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) 452 return 0; 453 454 switch (PCI_REVISION(pa->pa_class)) { 455 case 0x3a: 456 case 0x3b: 457 return 1; 458 } 459 460 return 0; 461 } 462 463 static int 464 ehci_apply_amd_quirks(struct ehci_pci_softc *sc) 465 { 466 pcireg_t value; 467 468 aprint_normal_dev(sc->sc.sc_dev, 469 "applying AMD SB600/SB700 USB freeze workaround\n"); 470 value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); 471 pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, 472 value | EHCI_SBx00_WORKAROUND_ENABLE); 473 474 return 0; 475 } 476 477 enum ehci_pci_quirk_flags 478 ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 479 { 480 int i; 481 482 for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { 483 if (vendor == ehci_pci_quirks[i].vendor && 484 product == ehci_pci_quirks[i].product) 485 return ehci_pci_quirks[i].quirks; 486 } 487 return 0; 488 } 489 490
Indexes created Sat Sep 27 21:09:56 GMT 2025