ehci_pci.c revision 1.54
1 /* $NetBSD: ehci_pci.c,v 1.54 2012/01/30 19:41:19 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.54 2012/01/30 19:41:19 drochner Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 enum ehci_pci_quirk_flags { 64 EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ 65 EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ 66 }; 67 68 static const struct pci_quirkdata ehci_pci_quirks[] = { 69 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, 70 EHCI_PCI_QUIRK_AMD_SB600 }, 71 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, 72 EHCI_PCI_QUIRK_AMD_SB700 }, 73 }; 74 75 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 76 pcitag_t tag); 77 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 78 pcitag_t tag); 79 static bool ehci_pci_suspend(device_t, const pmf_qual_t *); 80 static bool ehci_pci_resume(device_t, const pmf_qual_t *); 81 82 struct ehci_pci_softc { 83 ehci_softc_t sc; 84 pci_chipset_tag_t sc_pc; 85 pcitag_t sc_tag; 86 void *sc_ih; /* interrupt vectoring */ 87 }; 88 89 static int ehci_sb700_match(const struct pci_attach_args *pa); 90 static int ehci_apply_amd_quirks(struct ehci_pci_softc *sc); 91 enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, 92 pci_product_id_t); 93 94 #define EHCI_MAX_BIOS_WAIT 100 /* ms*10 */ 95 #define EHCI_SBx00_WORKAROUND_REG 0x50 96 #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) 97 98 99 static int 100 ehci_pci_match(device_t parent, cfdata_t match, void *aux) 101 { 102 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 103 104 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 105 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 106 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 107 return 1; 108 109 return 0; 110 } 111 112 static void 113 ehci_pci_attach(device_t parent, device_t self, void *aux) 114 { 115 struct ehci_pci_softc *sc = device_private(self); 116 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 117 pci_chipset_tag_t pc = pa->pa_pc; 118 pcitag_t tag = pa->pa_tag; 119 char const *intrstr; 120 pci_intr_handle_t ih; 121 pcireg_t csr; 122 const char *vendor; 123 usbd_status r; 124 int ncomp; 125 struct usb_pci *up; 126 int quirk; 127 128 sc->sc.sc_dev = self; 129 sc->sc.sc_bus.hci_private = sc; 130 131 pci_aprint_devinfo(pa, "USB controller"); 132 133 /* Check for quirks */ 134 quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 135 PCI_PRODUCT(pa->pa_id)); 136 137 /* Map I/O registers */ 138 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 139 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 140 sc->sc.sc_size = 0; 141 aprint_error_dev(self, "can't map memory space\n"); 142 return; 143 } 144 145 /* Disable interrupts, so we don't get any spurious ones. */ 146 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 147 DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs)); 148 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 149 150 sc->sc_pc = pc; 151 sc->sc_tag = tag; 152 sc->sc.sc_bus.dmatag = pa->pa_dmat; 153 154 /* Handle quirks */ 155 switch (quirk) { 156 case EHCI_PCI_QUIRK_AMD_SB600: 157 ehci_apply_amd_quirks(sc); 158 break; 159 case EHCI_PCI_QUIRK_AMD_SB700: 160 if (pci_find_device(NULL, ehci_sb700_match)) 161 ehci_apply_amd_quirks(sc); 162 break; 163 } 164 165 /* Enable the device. */ 166 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 167 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 168 csr | PCI_COMMAND_MASTER_ENABLE); 169 170 /* Map and establish the interrupt. */ 171 if (pci_intr_map(pa, &ih)) { 172 aprint_error_dev(self, "couldn't map interrupt\n"); 173 goto fail; 174 } 175 176 /* 177 * Allocate IRQ 178 */ 179 intrstr = pci_intr_string(pc, ih); 180 sc->sc_ih = pci_intr_establish(pc, ih, IPL_USB, ehci_intr, sc); 181 if (sc->sc_ih == NULL) { 182 aprint_error_dev(self, "couldn't establish interrupt"); 183 if (intrstr != NULL) 184 aprint_error(" at %s", intrstr); 185 aprint_error("\n"); 186 return; 187 } 188 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 189 190 switch(pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 191 case PCI_USBREV_PRE_1_0: 192 case PCI_USBREV_1_0: 193 case PCI_USBREV_1_1: 194 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 195 aprint_verbose_dev(self, "pre-2.0 USB rev\n"); 196 return; 197 case PCI_USBREV_2_0: 198 sc->sc.sc_bus.usbrev = USBREV_2_0; 199 break; 200 default: 201 sc->sc.sc_bus.usbrev = USBREV_UNKNOWN; 202 break; 203 } 204 205 /* Figure out vendor for root hub descriptor. */ 206 vendor = pci_findvendor(pa->pa_id); 207 sc->sc.sc_id_vendor = PCI_VENDOR(pa->pa_id); 208 if (vendor) 209 strlcpy(sc->sc.sc_vendor, vendor, sizeof(sc->sc.sc_vendor)); 210 else 211 snprintf(sc->sc.sc_vendor, sizeof(sc->sc.sc_vendor), 212 "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); 213 214 /* Enable workaround for dropped interrupts as required */ 215 switch (sc->sc.sc_id_vendor) { 216 case PCI_VENDOR_ATI: 217 case PCI_VENDOR_VIATECH: 218 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 219 aprint_normal_dev(self, "dropped intr workaround enabled\n"); 220 break; 221 default: 222 break; 223 } 224 225 /* 226 * Find companion controllers. According to the spec they always 227 * have lower function numbers so they should be enumerated already. 228 */ 229 const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS)); 230 KASSERT(maxncomp <= EHCI_COMPANION_MAX); 231 ncomp = 0; 232 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 233 if (up->bus == pa->pa_bus && up->device == pa->pa_device 234 && !up->claimed) { 235 DPRINTF(("ehci_pci_attach: companion %s\n", 236 device_xname(up->usb))); 237 sc->sc.sc_comps[ncomp++] = up->usb; 238 up->claimed = true; 239 if (ncomp == maxncomp) 240 break; 241 } 242 } 243 sc->sc.sc_ncomp = ncomp; 244 245 ehci_get_ownership(&sc->sc, pc, tag); 246 247 r = ehci_init(&sc->sc); 248 if (r != USBD_NORMAL_COMPLETION) { 249 aprint_error_dev(self, "init failed, error=%d\n", r); 250 goto fail; 251 } 252 253 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 254 ehci_shutdown)) 255 aprint_error_dev(self, "couldn't establish power handler\n"); 256 257 /* Attach usb device. */ 258 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 259 return; 260 261 fail: 262 if (sc->sc_ih) { 263 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 264 sc->sc_ih = NULL; 265 } 266 if (sc->sc.sc_size) { 267 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 268 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 269 sc->sc.sc_size = 0; 270 } 271 return; 272 } 273 274 static int 275 ehci_pci_detach(device_t self, int flags) 276 { 277 struct ehci_pci_softc *sc = device_private(self); 278 int rv; 279 280 rv = ehci_detach(&sc->sc, flags); 281 if (rv) 282 return rv; 283 284 pmf_device_deregister(self); 285 ehci_shutdown(self, flags); 286 287 /* disable interrupts */ 288 EOWRITE2(&sc->sc, EHCI_USBINTR, 0); 289 /* XXX grotty hack to flush the write */ 290 (void)EOREAD2(&sc->sc, EHCI_USBINTR); 291 292 if (sc->sc_ih != NULL) { 293 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 294 sc->sc_ih = NULL; 295 } 296 if (sc->sc.sc_size) { 297 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 298 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 299 sc->sc.sc_size = 0; 300 } 301 302 return 0; 303 } 304 305 CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 306 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 307 ehci_childdet, DVF_DETACH_SHUTDOWN); 308 309 #ifdef EHCI_DEBUG 310 static void 311 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 312 { 313 uint32_t cparams, legctlsts, addr, cap, id; 314 int maxdump = 10; 315 316 cparams = EREAD4(sc, EHCI_HCCPARAMS); 317 addr = EHCI_HCC_EECP(cparams); 318 while (addr != 0) { 319 cap = pci_conf_read(pc, tag, addr); 320 id = EHCI_CAP_GET_ID(cap); 321 switch (id) { 322 case EHCI_CAP_ID_LEGACY: 323 legctlsts = pci_conf_read(pc, tag, 324 addr + PCI_EHCI_USBLEGCTLSTS); 325 printf("ehci_dump_caps: legsup=0x%08x " 326 "legctlsts=0x%08x\n", cap, legctlsts); 327 break; 328 default: 329 printf("ehci_dump_caps: cap=0x%08x\n", cap); 330 break; 331 } 332 if (--maxdump < 0) 333 break; 334 addr = EHCI_CAP_GET_NEXT(cap); 335 } 336 } 337 #endif 338 339 static void 340 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 341 { 342 const char *devname = device_xname(sc->sc_dev); 343 uint32_t cparams, addr, cap; 344 pcireg_t legsup; 345 int maxcap = 10; 346 347 cparams = EREAD4(sc, EHCI_HCCPARAMS); 348 addr = EHCI_HCC_EECP(cparams); 349 while (addr != 0) { 350 cap = pci_conf_read(pc, tag, addr); 351 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 352 goto next; 353 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 354 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 355 legsup & ~EHCI_LEG_HC_OS_OWNED); 356 357 next: 358 if (--maxcap < 0) { 359 aprint_normal("%s: broken extended capabilities " 360 "ignored\n", devname); 361 return; 362 } 363 addr = EHCI_CAP_GET_NEXT(cap); 364 } 365 } 366 367 static void 368 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 369 { 370 const char *devname = device_xname(sc->sc_dev); 371 uint32_t cparams, addr, cap; 372 pcireg_t legsup; 373 int maxcap = 10; 374 int ms; 375 376 #ifdef EHCI_DEBUG 377 if (ehcidebug) 378 ehci_dump_caps(sc, pc, tag); 379 #endif 380 cparams = EREAD4(sc, EHCI_HCCPARAMS); 381 addr = EHCI_HCC_EECP(cparams); 382 while (addr != 0) { 383 cap = pci_conf_read(pc, tag, addr); 384 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 385 goto next; 386 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 387 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 388 /* Ask BIOS to give up ownership */ 389 legsup &= ~EHCI_LEG_HC_BIOS_OWNED; 390 legsup |= EHCI_LEG_HC_OS_OWNED; 391 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 392 legsup); 393 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 394 legsup = pci_conf_read(pc, tag, 395 addr + PCI_EHCI_USBLEGSUP); 396 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 397 break; 398 delay(10000); 399 } 400 if (ms == EHCI_MAX_BIOS_WAIT) { 401 aprint_normal("%s: BIOS refuses to give up " 402 "ownership, using force\n", devname); 403 pci_conf_write(pc, tag, 404 addr + PCI_EHCI_USBLEGSUP, 0); 405 } else 406 aprint_verbose("%s: BIOS has given up " 407 "ownership\n", devname); 408 } 409 410 /* Disable SMIs */ 411 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0); 412 413 next: 414 if (--maxcap < 0) { 415 aprint_normal("%s: broken extended capabilities " 416 "ignored\n", devname); 417 return; 418 } 419 addr = EHCI_CAP_GET_NEXT(cap); 420 } 421 422 } 423 424 static bool 425 ehci_pci_suspend(device_t dv, const pmf_qual_t *qual) 426 { 427 struct ehci_pci_softc *sc = device_private(dv); 428 429 ehci_suspend(dv, qual); 430 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 431 432 return true; 433 } 434 435 static bool 436 ehci_pci_resume(device_t dv, const pmf_qual_t *qual) 437 { 438 struct ehci_pci_softc *sc = device_private(dv); 439 440 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 441 return ehci_resume(dv, qual); 442 } 443 444 static int 445 ehci_sb700_match(const struct pci_attach_args *pa) 446 { 447 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 448 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) 449 return 0; 450 451 switch (PCI_REVISION(pa->pa_class)) { 452 case 0x3a: 453 case 0x3b: 454 return 1; 455 } 456 457 return 0; 458 } 459 460 static int 461 ehci_apply_amd_quirks(struct ehci_pci_softc *sc) 462 { 463 pcireg_t value; 464 465 aprint_normal_dev(sc->sc.sc_dev, 466 "applying AMD SB600/SB700 USB freeze workaround\n"); 467 value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); 468 pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, 469 value | EHCI_SBx00_WORKAROUND_ENABLE); 470 471 return 0; 472 } 473 474 enum ehci_pci_quirk_flags 475 ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 476 { 477 int i; 478 479 for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { 480 if (vendor == ehci_pci_quirks[i].vendor && 481 product == ehci_pci_quirks[i].product) 482 return ehci_pci_quirks[i].quirks; 483 } 484 return 0; 485 } 486 487
Indexes created Sun Sep 28 07:09:56 GMT 2025