ehci_pci.c revision 1.68
1 /* $NetBSD: ehci_pci.c,v 1.68 2018/10/25 21:07:58 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.68 2018/10/25 21:07:58 jdolecek Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 enum ehci_pci_quirk_flags { 64 EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ 65 EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ 66 }; 67 68 static const struct pci_quirkdata ehci_pci_quirks[] = { 69 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, 70 EHCI_PCI_QUIRK_AMD_SB600 }, 71 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, 72 EHCI_PCI_QUIRK_AMD_SB700 }, 73 }; 74 75 static void ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 76 pcitag_t tag); 77 static void ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, 78 pcitag_t tag); 79 static bool ehci_pci_suspend(device_t, const pmf_qual_t *); 80 static bool ehci_pci_resume(device_t, const pmf_qual_t *); 81 82 struct ehci_pci_softc { 83 ehci_softc_t sc; 84 pci_chipset_tag_t sc_pc; 85 pcitag_t sc_tag; 86 pci_intr_handle_t *sc_pihp; 87 void *sc_ih; /* interrupt vectoring */ 88 }; 89 90 static int ehci_sb700_match(const struct pci_attach_args *pa); 91 static int ehci_apply_amd_quirks(struct ehci_pci_softc *sc); 92 enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, 93 pci_product_id_t); 94 95 #define EHCI_MAX_BIOS_WAIT 100 /* ms*10 */ 96 #define EHCI_SBx00_WORKAROUND_REG 0x50 97 #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) 98 99 100 static int 101 ehci_pci_match(device_t parent, cfdata_t match, void *aux) 102 { 103 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 104 105 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 106 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 107 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 108 return 1; 109 110 return 0; 111 } 112 113 static void 114 ehci_pci_attach(device_t parent, device_t self, void *aux) 115 { 116 struct ehci_pci_softc *sc = device_private(self); 117 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 118 pci_chipset_tag_t pc = pa->pa_pc; 119 pcitag_t tag = pa->pa_tag; 120 char const *intrstr; 121 pcireg_t csr; 122 int ncomp; 123 struct usb_pci *up; 124 int quirk; 125 char intrbuf[PCI_INTRSTR_LEN]; 126 127 sc->sc.sc_dev = self; 128 sc->sc.sc_bus.ub_hcpriv = sc; 129 130 pci_aprint_devinfo(pa, "USB controller"); 131 132 /* Check for quirks */ 133 quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 134 PCI_PRODUCT(pa->pa_id)); 135 136 /* Map I/O registers */ 137 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 138 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 139 sc->sc.sc_size = 0; 140 aprint_error_dev(self, "can't map memory space\n"); 141 return; 142 } 143 144 sc->sc_pc = pc; 145 sc->sc_tag = tag; 146 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; 147 148 /* Disable interrupts, so we don't get any spurious ones. */ 149 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 150 DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs)); 151 EOWRITE4(&sc->sc, EHCI_USBINTR, 0); 152 153 /* Handle quirks */ 154 switch (quirk) { 155 case EHCI_PCI_QUIRK_AMD_SB600: 156 ehci_apply_amd_quirks(sc); 157 break; 158 case EHCI_PCI_QUIRK_AMD_SB700: 159 if (pci_find_device(NULL, ehci_sb700_match)) 160 ehci_apply_amd_quirks(sc); 161 break; 162 } 163 164 pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 165 int pin = PCI_INTERRUPT_PIN(intr); 166 167 /* Enable the device. */ 168 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 169 csr |= PCI_COMMAND_MASTER_ENABLE; 170 csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0); 171 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 172 173 /* Map and establish the interrupt. */ 174 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) != 0) { 175 aprint_error_dev(self, "couldn't map interrupt\n"); 176 goto fail; 177 } 178 179 /* 180 * Allocate IRQ 181 */ 182 intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf)); 183 sc->sc_ih = pci_intr_establish_xname(pc, sc->sc_pihp[0], IPL_USB, 184 ehci_intr, sc, device_xname(self)); 185 if (sc->sc_ih == NULL) { 186 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 187 sc->sc_pihp = NULL; 188 189 aprint_error_dev(self, "couldn't establish interrupt"); 190 if (intrstr != NULL) 191 aprint_error(" at %s", intrstr); 192 aprint_error("\n"); 193 goto fail; 194 } 195 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 196 197 switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 198 case PCI_USBREV_PRE_1_0: 199 case PCI_USBREV_1_0: 200 case PCI_USBREV_1_1: 201 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; 202 aprint_verbose_dev(self, "pre-2.0 USB rev\n"); 203 goto fail; 204 case PCI_USBREV_2_0: 205 sc->sc.sc_bus.ub_revision = USBREV_2_0; 206 break; 207 default: 208 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; 209 break; 210 } 211 212 /* Enable workaround for dropped interrupts as required */ 213 switch (PCI_VENDOR(pa->pa_id)) { 214 case PCI_VENDOR_ATI: 215 case PCI_VENDOR_VIATECH: 216 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 217 aprint_normal_dev(self, "dropped intr workaround enabled\n"); 218 break; 219 default: 220 break; 221 } 222 223 /* 224 * Find companion controllers. According to the spec they always 225 * have lower function numbers so they should be enumerated already. 226 */ 227 const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS)); 228 KASSERT(maxncomp <= EHCI_COMPANION_MAX); 229 ncomp = 0; 230 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 231 if (up->bus == pa->pa_bus && up->device == pa->pa_device 232 && !up->claimed) { 233 DPRINTF(("ehci_pci_attach: companion %s\n", 234 device_xname(up->usb))); 235 sc->sc.sc_comps[ncomp++] = up->usb; 236 up->claimed = true; 237 if (ncomp == maxncomp) 238 break; 239 } 240 } 241 sc->sc.sc_ncomp = ncomp; 242 243 ehci_get_ownership(&sc->sc, pc, tag); 244 245 int err = ehci_init(&sc->sc); 246 if (err) { 247 aprint_error_dev(self, "init failed, error=%d\n", err); 248 goto fail; 249 } 250 251 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 252 ehci_shutdown)) 253 aprint_error_dev(self, "couldn't establish power handler\n"); 254 255 /* Attach usb device. */ 256 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint); 257 return; 258 259 fail: 260 if (sc->sc_ih) { 261 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 262 sc->sc_ih = NULL; 263 } 264 if (sc->sc.sc_size) { 265 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 266 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 267 sc->sc.sc_size = 0; 268 } 269 return; 270 } 271 272 static int 273 ehci_pci_detach(device_t self, int flags) 274 { 275 struct ehci_pci_softc *sc = device_private(self); 276 int rv; 277 278 rv = ehci_detach(&sc->sc, flags); 279 if (rv) 280 return rv; 281 282 pmf_device_deregister(self); 283 ehci_shutdown(self, flags); 284 285 /* disable interrupts */ 286 EOWRITE4(&sc->sc, EHCI_USBINTR, 0); 287 /* XXX grotty hack to flush the write */ 288 (void)EOREAD4(&sc->sc, EHCI_USBINTR); 289 290 if (sc->sc_ih != NULL) { 291 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 292 sc->sc_ih = NULL; 293 } 294 295 if (sc->sc_pihp != NULL) { 296 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 297 sc->sc_pihp = NULL; 298 } 299 300 if (sc->sc.sc_size) { 301 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 302 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 303 sc->sc.sc_size = 0; 304 } 305 306 #if 1 307 /* XXX created in ehci.c */ 308 mutex_destroy(&sc->sc.sc_lock); 309 mutex_destroy(&sc->sc.sc_intr_lock); 310 311 softint_disestablish(sc->sc.sc_doorbell_si); 312 softint_disestablish(sc->sc.sc_pcd_si); 313 #endif 314 315 return 0; 316 } 317 318 CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 319 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 320 ehci_childdet, DVF_DETACH_SHUTDOWN); 321 322 #ifdef EHCI_DEBUG 323 static void 324 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 325 { 326 uint32_t cparams, legctlsts, addr, cap, id; 327 int maxdump = 10; 328 329 cparams = EREAD4(sc, EHCI_HCCPARAMS); 330 addr = EHCI_HCC_EECP(cparams); 331 while (addr != 0) { 332 cap = pci_conf_read(pc, tag, addr); 333 id = EHCI_CAP_GET_ID(cap); 334 switch (id) { 335 case EHCI_CAP_ID_LEGACY: 336 legctlsts = pci_conf_read(pc, tag, 337 addr + PCI_EHCI_USBLEGCTLSTS); 338 printf("ehci_dump_caps: legsup=0x%08x " 339 "legctlsts=0x%08x\n", cap, legctlsts); 340 break; 341 default: 342 printf("ehci_dump_caps: cap=0x%08x\n", cap); 343 break; 344 } 345 if (--maxdump < 0) 346 break; 347 addr = EHCI_CAP_GET_NEXT(cap); 348 } 349 } 350 #endif 351 352 static void 353 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 354 { 355 const char *devname = device_xname(sc->sc_dev); 356 uint32_t cparams, addr, cap; 357 pcireg_t legsup; 358 int maxcap = 10; 359 360 cparams = EREAD4(sc, EHCI_HCCPARAMS); 361 addr = EHCI_HCC_EECP(cparams); 362 while (addr != 0) { 363 cap = pci_conf_read(pc, tag, addr); 364 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 365 goto next; 366 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 367 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 368 legsup & ~EHCI_LEG_HC_OS_OWNED); 369 370 next: 371 if (--maxcap < 0) { 372 aprint_normal("%s: broken extended capabilities " 373 "ignored\n", devname); 374 return; 375 } 376 addr = EHCI_CAP_GET_NEXT(cap); 377 } 378 } 379 380 static void 381 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 382 { 383 const char *devname = device_xname(sc->sc_dev); 384 uint32_t cparams, addr, cap; 385 pcireg_t legsup; 386 int maxcap = 10; 387 int ms; 388 389 #ifdef EHCI_DEBUG 390 if (ehcidebug) 391 ehci_dump_caps(sc, pc, tag); 392 #endif 393 cparams = EREAD4(sc, EHCI_HCCPARAMS); 394 addr = EHCI_HCC_EECP(cparams); 395 while (addr != 0) { 396 cap = pci_conf_read(pc, tag, addr); 397 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 398 goto next; 399 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 400 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 401 /* Ask BIOS to give up ownership */ 402 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 403 legsup | EHCI_LEG_HC_OS_OWNED); 404 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 405 legsup = pci_conf_read(pc, tag, 406 addr + PCI_EHCI_USBLEGSUP); 407 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 408 break; 409 delay(10000); 410 } 411 if (ms == EHCI_MAX_BIOS_WAIT) { 412 aprint_normal("%s: BIOS refuses to give up " 413 "ownership, using force\n", devname); 414 pci_conf_write(pc, tag, 415 addr + PCI_EHCI_USBLEGSUP, 0); 416 } else 417 aprint_verbose("%s: BIOS has given up " 418 "ownership\n", devname); 419 } 420 421 /* Disable SMIs */ 422 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0); 423 424 next: 425 if (--maxcap < 0) { 426 aprint_normal("%s: broken extended capabilities " 427 "ignored\n", devname); 428 return; 429 } 430 addr = EHCI_CAP_GET_NEXT(cap); 431 } 432 433 } 434 435 static bool 436 ehci_pci_suspend(device_t dv, const pmf_qual_t *qual) 437 { 438 struct ehci_pci_softc *sc = device_private(dv); 439 440 ehci_suspend(dv, qual); 441 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 442 443 return true; 444 } 445 446 static bool 447 ehci_pci_resume(device_t dv, const pmf_qual_t *qual) 448 { 449 struct ehci_pci_softc *sc = device_private(dv); 450 451 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 452 return ehci_resume(dv, qual); 453 } 454 455 static int 456 ehci_sb700_match(const struct pci_attach_args *pa) 457 { 458 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 459 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) 460 return 0; 461 462 switch (PCI_REVISION(pa->pa_class)) { 463 case 0x3a: 464 case 0x3b: 465 return 1; 466 } 467 468 return 0; 469 } 470 471 static int 472 ehci_apply_amd_quirks(struct ehci_pci_softc *sc) 473 { 474 pcireg_t value; 475 476 aprint_normal_dev(sc->sc.sc_dev, 477 "applying AMD SB600/SB700 USB freeze workaround\n"); 478 value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); 479 pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, 480 value | EHCI_SBx00_WORKAROUND_ENABLE); 481 482 return 0; 483 } 484 485 enum ehci_pci_quirk_flags 486 ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 487 { 488 int i; 489 490 for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { 491 if (vendor == ehci_pci_quirks[i].vendor && 492 product == ehci_pci_quirks[i].product) 493 return ehci_pci_quirks[i].quirks; 494 } 495 return 0; 496 } 497 498
Indexes created Mon Sep 29 21:09:56 GMT 2025