ehci_pci.c revision 1.71
1 /* $NetBSD: ehci_pci.c,v 1.71 2021/04/24 23:36:57 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.71 2021/04/24 23:36:57 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 enum ehci_pci_quirk_flags { 64 EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ 65 EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ 66 }; 67 68 static const struct pci_quirkdata ehci_pci_quirks[] = { 69 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, 70 EHCI_PCI_QUIRK_AMD_SB600 }, 71 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, 72 EHCI_PCI_QUIRK_AMD_SB700 }, 73 }; 74 75 static void ehci_release_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t); 76 static void ehci_get_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t); 77 static bool ehci_pci_suspend(device_t, const pmf_qual_t *); 78 static bool ehci_pci_resume(device_t, const pmf_qual_t *); 79 80 struct ehci_pci_softc { 81 ehci_softc_t sc; 82 pci_chipset_tag_t sc_pc; 83 pcitag_t sc_tag; 84 pci_intr_handle_t *sc_pihp; 85 void *sc_ih; /* interrupt vectoring */ 86 enum { 87 EHCI_INIT_NONE, 88 EHCI_INIT_INITED 89 } sc_init_state; 90 }; 91 92 static int ehci_sb700_match(const struct pci_attach_args *); 93 static int ehci_apply_amd_quirks(struct ehci_pci_softc *); 94 static enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, 95 pci_product_id_t); 96 97 #define EHCI_MAX_BIOS_WAIT 100 /* ms*10 */ 98 #define EHCI_SBx00_WORKAROUND_REG 0x50 99 #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) 100 101 static int 102 ehci_pci_match(device_t parent, cfdata_t match, void *aux) 103 { 104 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 105 106 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 107 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 108 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 109 return 1; 110 111 return 0; 112 } 113 114 static void 115 ehci_pci_attach(device_t parent, device_t self, void *aux) 116 { 117 struct ehci_pci_softc *sc = device_private(self); 118 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 119 pci_chipset_tag_t pc = pa->pa_pc; 120 pcitag_t tag = pa->pa_tag; 121 char intrbuf[PCI_INTRSTR_LEN]; 122 char const *intrstr; 123 struct usb_pci *up; 124 int ncomp, quirk; 125 pcireg_t csr; 126 127 sc->sc_init_state = EHCI_INIT_NONE; 128 sc->sc.sc_dev = self; 129 sc->sc.sc_bus.ub_hcpriv = sc; 130 131 pci_aprint_devinfo(pa, "USB controller"); 132 133 /* Check for quirks */ 134 quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 135 PCI_PRODUCT(pa->pa_id)); 136 137 /* Map I/O registers */ 138 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 139 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 140 sc->sc.sc_size = 0; 141 aprint_error_dev(self, "can't map memory space\n"); 142 return; 143 } 144 145 sc->sc_pc = pc; 146 sc->sc_tag = tag; 147 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; 148 149 /* Disable interrupts, so we don't get any spurious ones. */ 150 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 151 DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs)); 152 EOWRITE4(&sc->sc, EHCI_USBINTR, 0); 153 154 /* Handle quirks */ 155 switch (quirk) { 156 case EHCI_PCI_QUIRK_AMD_SB600: 157 ehci_apply_amd_quirks(sc); 158 break; 159 case EHCI_PCI_QUIRK_AMD_SB700: 160 if (pci_find_device(NULL, ehci_sb700_match)) 161 ehci_apply_amd_quirks(sc); 162 break; 163 } 164 165 pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 166 int pin = PCI_INTERRUPT_PIN(intr); 167 168 /* Enable the device. */ 169 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 170 csr |= PCI_COMMAND_MASTER_ENABLE; 171 csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0); 172 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 173 174 /* Map and establish the interrupt. */ 175 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) != 0) { 176 aprint_error_dev(self, "couldn't map interrupt\n"); 177 goto fail; 178 } 179 180 /* 181 * Allocate IRQ 182 */ 183 intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf)); 184 sc->sc_ih = pci_intr_establish_xname(pc, sc->sc_pihp[0], IPL_USB, 185 ehci_intr, sc, device_xname(self)); 186 if (sc->sc_ih == NULL) { 187 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 188 sc->sc_pihp = NULL; 189 190 aprint_error_dev(self, "couldn't establish interrupt"); 191 if (intrstr != NULL) 192 aprint_error(" at %s", intrstr); 193 aprint_error("\n"); 194 goto fail; 195 } 196 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 197 198 switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 199 case PCI_USBREV_PRE_1_0: 200 case PCI_USBREV_1_0: 201 case PCI_USBREV_1_1: 202 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; 203 aprint_verbose_dev(self, "pre-2.0 USB rev, device ignored\n"); 204 goto fail; 205 case PCI_USBREV_2_0: 206 sc->sc.sc_bus.ub_revision = USBREV_2_0; 207 break; 208 default: 209 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; 210 break; 211 } 212 213 /* Enable workaround for dropped interrupts as required */ 214 switch (PCI_VENDOR(pa->pa_id)) { 215 case PCI_VENDOR_ATI: 216 case PCI_VENDOR_VIATECH: 217 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 218 aprint_normal_dev(self, "dropped intr workaround enabled\n"); 219 break; 220 default: 221 break; 222 } 223 224 /* 225 * Find companion controllers. According to the spec they always 226 * have lower function numbers so they should be enumerated already. 227 */ 228 const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS)); 229 KASSERT(maxncomp <= EHCI_COMPANION_MAX); 230 ncomp = 0; 231 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 232 if (up->bus == pa->pa_bus && up->device == pa->pa_device && 233 !up->claimed) { 234 DPRINTF(("ehci_pci_attach: companion %s\n", 235 device_xname(up->usb))); 236 sc->sc.sc_comps[ncomp++] = up->usb; 237 up->claimed = true; 238 if (ncomp == maxncomp) 239 break; 240 } 241 } 242 sc->sc.sc_ncomp = ncomp; 243 244 ehci_get_ownership(&sc->sc, pc, tag); 245 246 int err = ehci_init(&sc->sc); 247 if (err) { 248 aprint_error_dev(self, "init failed, error=%d\n", err); 249 goto fail; 250 } 251 sc->sc_init_state = EHCI_INIT_INITED; 252 253 if (!pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 254 ehci_shutdown)) 255 aprint_error_dev(self, "couldn't establish power handler\n"); 256 257 /* Attach usb device. */ 258 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint, 259 CFARG_EOL); 260 return; 261 262 fail: 263 if (sc->sc_ih) { 264 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 265 sc->sc_ih = NULL; 266 } 267 if (sc->sc.sc_size) { 268 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 269 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 270 sc->sc.sc_size = 0; 271 } 272 } 273 274 static int 275 ehci_pci_detach(device_t self, int flags) 276 { 277 struct ehci_pci_softc *sc = device_private(self); 278 int rv; 279 280 if (sc->sc_init_state >= EHCI_INIT_INITED) { 281 rv = ehci_detach(&sc->sc, flags); 282 if (rv) 283 return rv; 284 } 285 286 pmf_device_deregister(self); 287 ehci_shutdown(self, flags); 288 289 /* disable interrupts */ 290 EOWRITE4(&sc->sc, EHCI_USBINTR, 0); 291 /* XXX grotty hack to flush the write */ 292 (void)EOREAD4(&sc->sc, EHCI_USBINTR); 293 294 if (sc->sc_ih != NULL) { 295 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 296 sc->sc_ih = NULL; 297 } 298 299 if (sc->sc_pihp != NULL) { 300 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 301 sc->sc_pihp = NULL; 302 } 303 304 if (sc->sc.sc_size) { 305 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 306 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 307 sc->sc.sc_size = 0; 308 } 309 310 #if 1 311 /* XXX created in ehci.c */ 312 if (sc->sc_init_state >= EHCI_INIT_INITED) { 313 mutex_destroy(&sc->sc.sc_lock); 314 mutex_destroy(&sc->sc.sc_intr_lock); 315 softint_disestablish(sc->sc.sc_doorbell_si); 316 softint_disestablish(sc->sc.sc_pcd_si); 317 } 318 #endif 319 320 return 0; 321 } 322 323 CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 324 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 325 ehci_childdet, DVF_DETACH_SHUTDOWN); 326 327 #ifdef EHCI_DEBUG 328 static void 329 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 330 { 331 uint32_t cparams, legctlsts, addr, cap, id; 332 int maxdump = 10; 333 334 cparams = EREAD4(sc, EHCI_HCCPARAMS); 335 addr = EHCI_HCC_EECP(cparams); 336 while (addr != 0) { 337 cap = pci_conf_read(pc, tag, addr); 338 id = EHCI_CAP_GET_ID(cap); 339 switch (id) { 340 case EHCI_CAP_ID_LEGACY: 341 legctlsts = pci_conf_read(pc, tag, 342 addr + PCI_EHCI_USBLEGCTLSTS); 343 printf("ehci_dump_caps: legsup=0x%08x " 344 "legctlsts=0x%08x\n", cap, legctlsts); 345 break; 346 default: 347 printf("ehci_dump_caps: cap=0x%08x\n", cap); 348 break; 349 } 350 if (--maxdump < 0) 351 break; 352 addr = EHCI_CAP_GET_NEXT(cap); 353 } 354 } 355 #endif 356 357 static void 358 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 359 { 360 const char *devname = device_xname(sc->sc_dev); 361 uint32_t cparams, addr, cap; 362 pcireg_t legsup; 363 int maxcap = 10; 364 365 cparams = EREAD4(sc, EHCI_HCCPARAMS); 366 addr = EHCI_HCC_EECP(cparams); 367 while (addr != 0) { 368 cap = pci_conf_read(pc, tag, addr); 369 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 370 goto next; 371 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 372 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 373 legsup & ~EHCI_LEG_HC_OS_OWNED); 374 375 next: 376 if (--maxcap < 0) { 377 aprint_normal("%s: broken extended capabilities " 378 "ignored\n", devname); 379 return; 380 } 381 addr = EHCI_CAP_GET_NEXT(cap); 382 } 383 } 384 385 static void 386 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 387 { 388 const char *devname = device_xname(sc->sc_dev); 389 uint32_t cparams, addr, cap; 390 pcireg_t legsup; 391 int maxcap = 10; 392 int ms; 393 394 #ifdef EHCI_DEBUG 395 if (ehcidebug) 396 ehci_dump_caps(sc, pc, tag); 397 #endif 398 cparams = EREAD4(sc, EHCI_HCCPARAMS); 399 addr = EHCI_HCC_EECP(cparams); 400 while (addr != 0) { 401 cap = pci_conf_read(pc, tag, addr); 402 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 403 goto next; 404 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 405 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 406 /* Ask BIOS to give up ownership */ 407 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 408 legsup | EHCI_LEG_HC_OS_OWNED); 409 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 410 legsup = pci_conf_read(pc, tag, 411 addr + PCI_EHCI_USBLEGSUP); 412 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 413 break; 414 delay(10000); 415 } 416 if (ms == EHCI_MAX_BIOS_WAIT) { 417 aprint_normal("%s: BIOS refuses to give up " 418 "ownership, using force\n", devname); 419 pci_conf_write(pc, tag, 420 addr + PCI_EHCI_USBLEGSUP, 0); 421 } else 422 aprint_verbose("%s: BIOS has given up " 423 "ownership\n", devname); 424 } 425 426 /* Disable SMIs */ 427 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0); 428 429 next: 430 if (--maxcap < 0) { 431 aprint_normal("%s: broken extended capabilities " 432 "ignored\n", devname); 433 return; 434 } 435 addr = EHCI_CAP_GET_NEXT(cap); 436 } 437 438 } 439 440 static bool 441 ehci_pci_suspend(device_t dv, const pmf_qual_t *qual) 442 { 443 struct ehci_pci_softc *sc = device_private(dv); 444 445 ehci_suspend(dv, qual); 446 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 447 448 return true; 449 } 450 451 static bool 452 ehci_pci_resume(device_t dv, const pmf_qual_t *qual) 453 { 454 struct ehci_pci_softc *sc = device_private(dv); 455 456 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 457 return ehci_resume(dv, qual); 458 } 459 460 static int 461 ehci_sb700_match(const struct pci_attach_args *pa) 462 { 463 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 464 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) 465 return 0; 466 467 switch (PCI_REVISION(pa->pa_class)) { 468 case 0x3a: 469 case 0x3b: 470 return 1; 471 } 472 473 return 0; 474 } 475 476 static int 477 ehci_apply_amd_quirks(struct ehci_pci_softc *sc) 478 { 479 pcireg_t value; 480 481 aprint_normal_dev(sc->sc.sc_dev, 482 "applying AMD SB600/SB700 USB freeze workaround\n"); 483 value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); 484 pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, 485 value | EHCI_SBx00_WORKAROUND_ENABLE); 486 487 return 0; 488 } 489 490 static enum ehci_pci_quirk_flags 491 ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 492 { 493 int i; 494 495 for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { 496 if (vendor == ehci_pci_quirks[i].vendor && 497 product == ehci_pci_quirks[i].product) 498 return ehci_pci_quirks[i].quirks; 499 } 500 return 0; 501 } 502 503
Indexes created Mon Sep 29 03:10:08 GMT 2025