ehci_pci.c revision 1.78
1 /* $NetBSD: ehci_pci.c,v 1.78 2025/03/31 14:45:35 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net). 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: ehci_pci.c,v 1.78 2025/03/31 14:45:35 riastradh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/device.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 42 #include <sys/bus.h> 43 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/usb_pci.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 53 #include <dev/usb/ehcireg.h> 54 #include <dev/usb/ehcivar.h> 55 56 #ifdef EHCI_DEBUG 57 #define DPRINTF(x) if (ehcidebug) printf x 58 extern int ehcidebug; 59 #else 60 #define DPRINTF(x) 61 #endif 62 63 enum ehci_pci_quirk_flags { 64 EHCI_PCI_QUIRK_AMD_SB600 = 0x1, /* always need a quirk */ 65 EHCI_PCI_QUIRK_AMD_SB700 = 0x2, /* depends on the SMB revision */ 66 }; 67 68 static const struct pci_quirkdata ehci_pci_quirks[] = { 69 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_USB_EHCI, 70 EHCI_PCI_QUIRK_AMD_SB600 }, 71 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_USB_EHCI, 72 EHCI_PCI_QUIRK_AMD_SB700 }, 73 }; 74 75 static void ehci_release_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t); 76 static void ehci_get_ownership(ehci_softc_t *, pci_chipset_tag_t, pcitag_t); 77 static bool ehci_pci_suspend(device_t, const pmf_qual_t *); 78 static bool ehci_pci_resume(device_t, const pmf_qual_t *); 79 80 struct ehci_pci_softc { 81 ehci_softc_t sc; 82 pci_chipset_tag_t sc_pc; 83 pcitag_t sc_tag; 84 pci_intr_handle_t *sc_pihp; 85 void *sc_ih; /* interrupt vectoring */ 86 enum { 87 EHCI_INIT_NONE, 88 EHCI_INIT_OWNER, 89 EHCI_INIT_INITED 90 } sc_init_state; 91 }; 92 93 static void ehci_pci_release_resources(struct ehci_pci_softc *); 94 static int ehci_sb700_match(const struct pci_attach_args *); 95 static int ehci_apply_amd_quirks(struct ehci_pci_softc *); 96 static enum ehci_pci_quirk_flags ehci_pci_lookup_quirkdata(pci_vendor_id_t, 97 pci_product_id_t); 98 99 #define EHCI_MAX_BIOS_WAIT 100 /* ms*10 */ 100 #define EHCI_SBx00_WORKAROUND_REG 0x50 101 #define EHCI_SBx00_WORKAROUND_ENABLE __BIT(27) 102 103 static int 104 ehci_pci_match(device_t parent, cfdata_t match, void *aux) 105 { 106 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 107 108 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 109 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && 110 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) 111 return 1; 112 113 return 0; 114 } 115 116 static void 117 ehci_pci_attach(device_t parent, device_t self, void *aux) 118 { 119 struct ehci_pci_softc *sc = device_private(self); 120 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 121 pci_chipset_tag_t pc = pa->pa_pc; 122 pcitag_t tag = pa->pa_tag; 123 char intrbuf[PCI_INTRSTR_LEN]; 124 char const *intrstr; 125 struct usb_pci *up; 126 int ncomp, quirk; 127 pcireg_t csr; 128 129 sc->sc_init_state = EHCI_INIT_NONE; 130 sc->sc.sc_dev = self; 131 sc->sc.sc_bus.ub_hcpriv = sc; 132 133 pci_aprint_devinfo(pa, "USB controller"); 134 135 /* Check for quirks */ 136 quirk = ehci_pci_lookup_quirkdata(PCI_VENDOR(pa->pa_id), 137 PCI_PRODUCT(pa->pa_id)); 138 139 /* Map I/O registers */ 140 if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, 141 &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { 142 sc->sc.sc_size = 0; 143 aprint_error_dev(self, "can't map memory space\n"); 144 return; 145 } 146 147 sc->sc_pc = pc; 148 sc->sc_tag = tag; 149 150 const uint32_t hccparams = EREAD4(&sc->sc, EHCI_HCCPARAMS); 151 152 if (EHCI_HCC_64BIT(hccparams)) { 153 aprint_verbose_dev(self, "64-bit DMA"); 154 if (pci_dma64_available(pa)) { 155 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat64; 156 aprint_verbose("\n"); 157 } else { 158 aprint_verbose(" - limited\n"); 159 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; 160 } 161 } else { 162 aprint_verbose_dev(self, "32-bit DMA\n"); 163 sc->sc.sc_bus.ub_dmatag = pa->pa_dmat; 164 } 165 166 /* Disable interrupts, so we don't get any spurious ones. */ 167 sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH); 168 DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs)); 169 EOWRITE4(&sc->sc, EHCI_USBINTR, 0); 170 171 /* Handle quirks */ 172 switch (quirk) { 173 case EHCI_PCI_QUIRK_AMD_SB600: 174 ehci_apply_amd_quirks(sc); 175 break; 176 case EHCI_PCI_QUIRK_AMD_SB700: 177 if (pci_find_device(NULL, ehci_sb700_match)) 178 ehci_apply_amd_quirks(sc); 179 break; 180 } 181 182 pcireg_t intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 183 int pin = PCI_INTERRUPT_PIN(intr); 184 185 /* Enable the device. */ 186 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 187 csr |= PCI_COMMAND_MASTER_ENABLE; 188 csr &= ~(pin ? PCI_COMMAND_INTERRUPT_DISABLE : 0); 189 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 190 191 /* Map and establish the interrupt. */ 192 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0) != 0) { 193 aprint_error_dev(self, "couldn't map interrupt\n"); 194 goto fail; 195 } 196 197 /* 198 * Allocate IRQ 199 */ 200 intrstr = pci_intr_string(pc, sc->sc_pihp[0], intrbuf, sizeof(intrbuf)); 201 pci_intr_setattr(pc, &sc->sc_pihp[0], PCI_INTR_MPSAFE, true); 202 sc->sc_ih = pci_intr_establish_xname(pc, sc->sc_pihp[0], IPL_USB, 203 ehci_intr, sc, device_xname(self)); 204 if (sc->sc_ih == NULL) { 205 aprint_error_dev(self, "couldn't establish interrupt"); 206 if (intrstr != NULL) 207 aprint_error(" at %s", intrstr); 208 aprint_error("\n"); 209 goto fail; 210 } 211 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 212 213 switch (pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK) { 214 case PCI_USBREV_PRE_1_0: 215 case PCI_USBREV_1_0: 216 case PCI_USBREV_1_1: 217 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; 218 aprint_verbose_dev(self, "pre-2.0 USB rev, device ignored\n"); 219 goto fail; 220 case PCI_USBREV_2_0: 221 sc->sc.sc_bus.ub_revision = USBREV_2_0; 222 break; 223 default: 224 sc->sc.sc_bus.ub_revision = USBREV_UNKNOWN; 225 break; 226 } 227 228 /* Enable workaround for dropped interrupts as required */ 229 switch (PCI_VENDOR(pa->pa_id)) { 230 case PCI_VENDOR_ATI: 231 case PCI_VENDOR_VIATECH: 232 sc->sc.sc_flags |= EHCIF_DROPPED_INTR_WORKAROUND; 233 aprint_normal_dev(self, "dropped intr workaround enabled\n"); 234 break; 235 default: 236 break; 237 } 238 239 /* 240 * Find companion controllers. According to the spec they always 241 * have lower function numbers so they should be enumerated already. 242 */ 243 const u_int maxncomp = EHCI_HCS_N_CC(EREAD4(&sc->sc, EHCI_HCSPARAMS)); 244 KASSERT(maxncomp <= EHCI_COMPANION_MAX); 245 ncomp = 0; 246 KASSERT(KERNEL_LOCKED_P()); /* XXXSMP ehci_pci_alldevs */ 247 TAILQ_FOREACH(up, &ehci_pci_alldevs, next) { 248 if (up->bus == pa->pa_bus && up->device == pa->pa_device && 249 !up->claimed) { 250 DPRINTF(("ehci_pci_attach: companion %s\n", 251 device_xname(up->usb))); 252 sc->sc.sc_comps[ncomp++] = up->usb; 253 up->claimed = true; 254 if (ncomp == maxncomp) 255 break; 256 } 257 } 258 sc->sc.sc_ncomp = ncomp; 259 260 ehci_get_ownership(&sc->sc, pc, tag); 261 sc->sc_init_state = EHCI_INIT_OWNER; 262 263 int err = ehci_init(&sc->sc); 264 if (err) { 265 aprint_error_dev(self, "init failed, error=%d\n", err); 266 goto fail; 267 } 268 sc->sc_init_state = EHCI_INIT_INITED; 269 270 pmf_device_register1(self, ehci_pci_suspend, ehci_pci_resume, 271 ehci_shutdown); 272 273 /* Attach usb device. */ 274 sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint, 275 CFARGS_NONE); 276 return; 277 278 fail: 279 ehci_pci_release_resources(sc); 280 pmf_device_register(self, NULL, NULL); 281 } 282 283 static void 284 ehci_pci_release_resources(struct ehci_pci_softc *sc) 285 { 286 if (sc->sc_init_state >= EHCI_INIT_OWNER) 287 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 288 289 if (sc->sc_ih) { 290 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 291 sc->sc_ih = NULL; 292 } 293 if (sc->sc_pihp != NULL) { 294 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1); 295 sc->sc_pihp = NULL; 296 } 297 298 if (sc->sc.sc_size) { 299 bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size); 300 sc->sc.sc_size = 0; 301 } 302 303 sc->sc_init_state = EHCI_INIT_NONE; 304 } 305 306 static int 307 ehci_pci_detach(device_t self, int flags) 308 { 309 struct ehci_pci_softc *sc = device_private(self); 310 int rv; 311 312 if (sc->sc_init_state >= EHCI_INIT_INITED) { 313 rv = ehci_detach(&sc->sc, flags); 314 if (rv) 315 return rv; 316 } 317 318 pmf_device_deregister(self); 319 ehci_shutdown(self, flags); 320 321 if (sc->sc_init_state >= EHCI_INIT_INITED) { 322 /* disable interrupts */ 323 EOWRITE4(&sc->sc, EHCI_USBINTR, 0); 324 /* XXX grotty hack to flush the write */ 325 (void)EOREAD4(&sc->sc, EHCI_USBINTR); 326 } 327 328 ehci_pci_release_resources(sc); 329 330 #if 1 331 /* XXX created in ehci.c */ 332 if (sc->sc_init_state >= EHCI_INIT_INITED) { 333 mutex_destroy(&sc->sc.sc_rhlock); 334 mutex_destroy(&sc->sc.sc_lock); 335 mutex_destroy(&sc->sc.sc_intr_lock); 336 softint_disestablish(sc->sc.sc_doorbell_si); 337 softint_disestablish(sc->sc.sc_pcd_si); 338 } 339 #endif 340 341 return 0; 342 } 343 344 CFATTACH_DECL3_NEW(ehci_pci, sizeof(struct ehci_pci_softc), 345 ehci_pci_match, ehci_pci_attach, ehci_pci_detach, ehci_activate, NULL, 346 ehci_childdet, DVF_DETACH_SHUTDOWN); 347 348 #ifdef EHCI_DEBUG 349 static void 350 ehci_dump_caps(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 351 { 352 uint32_t cparams, legctlsts, addr, cap, id; 353 int maxdump = 10; 354 355 cparams = EREAD4(sc, EHCI_HCCPARAMS); 356 addr = EHCI_HCC_EECP(cparams); 357 while (addr != 0) { 358 cap = pci_conf_read(pc, tag, addr); 359 id = EHCI_CAP_GET_ID(cap); 360 switch (id) { 361 case EHCI_CAP_ID_LEGACY: 362 legctlsts = pci_conf_read(pc, tag, 363 addr + PCI_EHCI_USBLEGCTLSTS); 364 printf("ehci_dump_caps: legsup=0x%08x " 365 "legctlsts=0x%08x\n", cap, legctlsts); 366 break; 367 default: 368 printf("ehci_dump_caps: cap=0x%08x\n", cap); 369 break; 370 } 371 if (--maxdump < 0) 372 break; 373 addr = EHCI_CAP_GET_NEXT(cap); 374 } 375 } 376 #endif 377 378 static void 379 ehci_release_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 380 { 381 const char *devname = device_xname(sc->sc_dev); 382 uint32_t cparams, addr, cap; 383 pcireg_t legsup; 384 int maxcap = 10; 385 386 cparams = EREAD4(sc, EHCI_HCCPARAMS); 387 addr = EHCI_HCC_EECP(cparams); 388 while (addr != 0) { 389 cap = pci_conf_read(pc, tag, addr); 390 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 391 goto next; 392 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 393 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 394 legsup & ~EHCI_LEG_HC_OS_OWNED); 395 396 next: 397 if (--maxcap < 0) { 398 aprint_normal("%s: broken extended capabilities " 399 "ignored\n", devname); 400 return; 401 } 402 addr = EHCI_CAP_GET_NEXT(cap); 403 } 404 } 405 406 static void 407 ehci_get_ownership(ehci_softc_t *sc, pci_chipset_tag_t pc, pcitag_t tag) 408 { 409 const char *devname = device_xname(sc->sc_dev); 410 uint32_t cparams, addr, cap; 411 pcireg_t legsup; 412 int maxcap = 10; 413 int ms; 414 415 #ifdef EHCI_DEBUG 416 if (ehcidebug) 417 ehci_dump_caps(sc, pc, tag); 418 #endif 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 addr = EHCI_HCC_EECP(cparams); 421 while (addr != 0) { 422 cap = pci_conf_read(pc, tag, addr); 423 if (EHCI_CAP_GET_ID(cap) != EHCI_CAP_ID_LEGACY) 424 goto next; 425 legsup = pci_conf_read(pc, tag, addr + PCI_EHCI_USBLEGSUP); 426 if (legsup & EHCI_LEG_HC_BIOS_OWNED) { 427 /* Ask BIOS to give up ownership */ 428 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGSUP, 429 legsup | EHCI_LEG_HC_OS_OWNED); 430 for (ms = 0; ms < EHCI_MAX_BIOS_WAIT; ms++) { 431 legsup = pci_conf_read(pc, tag, 432 addr + PCI_EHCI_USBLEGSUP); 433 if (!(legsup & EHCI_LEG_HC_BIOS_OWNED)) 434 break; 435 delay(10000); 436 } 437 if (ms == EHCI_MAX_BIOS_WAIT) { 438 aprint_normal("%s: BIOS refuses to give up " 439 "ownership, using force\n", devname); 440 pci_conf_write(pc, tag, 441 addr + PCI_EHCI_USBLEGSUP, 0); 442 } else 443 aprint_verbose("%s: BIOS has given up " 444 "ownership\n", devname); 445 } 446 447 /* Disable SMIs */ 448 pci_conf_write(pc, tag, addr + PCI_EHCI_USBLEGCTLSTS, 0); 449 450 next: 451 if (--maxcap < 0) { 452 aprint_normal("%s: broken extended capabilities " 453 "ignored\n", devname); 454 return; 455 } 456 addr = EHCI_CAP_GET_NEXT(cap); 457 } 458 459 } 460 461 static bool 462 ehci_pci_suspend(device_t dv, const pmf_qual_t *qual) 463 { 464 struct ehci_pci_softc *sc = device_private(dv); 465 466 ehci_suspend(dv, qual); 467 ehci_release_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 468 469 return true; 470 } 471 472 static bool 473 ehci_pci_resume(device_t dv, const pmf_qual_t *qual) 474 { 475 struct ehci_pci_softc *sc = device_private(dv); 476 477 ehci_get_ownership(&sc->sc, sc->sc_pc, sc->sc_tag); 478 return ehci_resume(dv, qual); 479 } 480 481 static int 482 ehci_sb700_match(const struct pci_attach_args *pa) 483 { 484 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 485 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB)) 486 return 0; 487 488 switch (PCI_REVISION(pa->pa_class)) { 489 case 0x3a: 490 case 0x3b: 491 return 1; 492 } 493 494 return 0; 495 } 496 497 static int 498 ehci_apply_amd_quirks(struct ehci_pci_softc *sc) 499 { 500 pcireg_t value; 501 502 aprint_normal_dev(sc->sc.sc_dev, 503 "applying AMD SB600/SB700 USB freeze workaround\n"); 504 value = pci_conf_read(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG); 505 pci_conf_write(sc->sc_pc, sc->sc_tag, EHCI_SBx00_WORKAROUND_REG, 506 value | EHCI_SBx00_WORKAROUND_ENABLE); 507 508 return 0; 509 } 510 511 static enum ehci_pci_quirk_flags 512 ehci_pci_lookup_quirkdata(pci_vendor_id_t vendor, pci_product_id_t product) 513 { 514 int i; 515 516 for (i = 0; i < __arraycount(ehci_pci_quirks); i++) { 517 if (vendor == ehci_pci_quirks[i].vendor && 518 product == ehci_pci_quirks[i].product) 519 return ehci_pci_quirks[i].quirks; 520 } 521 return 0; 522 } 523 524
Indexes created Sat Sep 27 22:09:54 GMT 2025