1 1.67 mlelstv /* $NetBSD: esm.c,v 1.67 2025/09/01 17:44:29 mlelstv Exp $ */ 2 1.1 rh 3 1.1 rh /*- 4 1.18 fredette * Copyright (c) 2002, 2003 Matt Fredette 5 1.18 fredette * All rights reserved. 6 1.18 fredette * 7 1.23 keihan * Copyright (c) 2000, 2001 Rene Hexel <rh (at) NetBSD.org> 8 1.1 rh * All rights reserved. 9 1.1 rh * 10 1.1 rh * Copyright (c) 2000 Taku YAMAMOTO <taku (at) cent.saitama-u.ac.jp> 11 1.1 rh * All rights reserved. 12 1.1 rh * 13 1.1 rh * Redistribution and use in source and binary forms, with or without 14 1.1 rh * modification, are permitted provided that the following conditions 15 1.1 rh * are met: 16 1.1 rh * 1. Redistributions of source code must retain the above copyright 17 1.1 rh * notice, this list of conditions and the following disclaimer. 18 1.1 rh * 2. Redistributions in binary form must reproduce the above copyright 19 1.1 rh * notice, this list of conditions and the following disclaimer in the 20 1.1 rh * documentation and/or other materials provided with the distribution. 21 1.1 rh * 22 1.1 rh * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 1.1 rh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 1.1 rh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 1.1 rh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 1.1 rh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 1.1 rh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 1.1 rh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 1.1 rh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 1.1 rh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 1.1 rh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 1.1 rh * SUCH DAMAGE. 33 1.1 rh * 34 1.1 rh * Taku Id: maestro.c,v 1.12 2000/09/06 03:32:34 taku Exp 35 1.1 rh * FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.4 2000/12/18 01:36:35 cg Exp 36 1.1 rh */ 37 1.1 rh 38 1.1 rh /* 39 1.1 rh * TODO: 40 1.1 rh * - hardware volume support 41 1.18 fredette * - fix 16-bit stereo recording, add 8-bit recording 42 1.1 rh * - MIDI support 43 1.1 rh * - joystick support 44 1.1 rh * 45 1.1 rh * 46 1.1 rh * Credits: 47 1.1 rh * 48 1.1 rh * This code is based on the FreeBSD driver written by Taku YAMAMOTO 49 1.1 rh * 50 1.1 rh * 51 1.1 rh * Original credits from the FreeBSD driver: 52 1.1 rh * 53 1.1 rh * Part of this code (especially in many magic numbers) was heavily inspired 54 1.1 rh * by the Linux driver originally written by 55 1.1 rh * Alan Cox <alan.cox (at) linux.org>, modified heavily by 56 1.1 rh * Zach Brown <zab (at) zabbo.net>. 57 1.1 rh * 58 1.1 rh * busdma()-ize and buffer size reduction were suggested by 59 1.1 rh * Cameron Grant <gandalf (at) vilnya.demon.co.uk>. 60 1.1 rh * Also he showed me the way to use busdma() suite. 61 1.1 rh * 62 1.1 rh * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500 63 1.1 rh * were looked at by 64 1.1 rh * Munehiro Matsuda <haro (at) tk.kubota.co.jp>, 65 1.1 rh * who brought patches based on the Linux driver with some simplification. 66 1.1 rh */ 67 1.12 lukem 68 1.12 lukem #include <sys/cdefs.h> 69 1.67 mlelstv __KERNEL_RCSID(0, "$NetBSD: esm.c,v 1.67 2025/09/01 17:44:29 mlelstv Exp $"); 70 1.1 rh 71 1.1 rh #include <sys/param.h> 72 1.1 rh #include <sys/systm.h> 73 1.1 rh #include <sys/kernel.h> 74 1.54 jmcneill #include <sys/kmem.h> 75 1.1 rh #include <sys/device.h> 76 1.43 ad #include <sys/bus.h> 77 1.54 jmcneill #include <sys/audioio.h> 78 1.1 rh 79 1.62 isaki #include <dev/audio/audio_if.h> 80 1.54 jmcneill 81 1.1 rh #include <dev/ic/ac97var.h> 82 1.8 ichiro #include <dev/ic/ac97reg.h> 83 1.1 rh 84 1.1 rh #include <dev/pci/pcidevs.h> 85 1.1 rh #include <dev/pci/pcivar.h> 86 1.1 rh #include <dev/pci/esmreg.h> 87 1.1 rh #include <dev/pci/esmvar.h> 88 1.1 rh 89 1.1 rh #define PCI_CBIO 0x10 /* Configuration Base I/O Address */ 90 1.1 rh 91 1.1 rh /* Debug */ 92 1.1 rh #ifdef AUDIO_DEBUG 93 1.1 rh #define DPRINTF(l,x) do { if (esm_debug & (l)) printf x; } while(0) 94 1.1 rh #define DUMPREG(x) do { if (esm_debug & ESM_DEBUG_REG) \ 95 1.1 rh esm_dump_regs(x); } while(0) 96 1.1 rh int esm_debug = 0xfffc; 97 1.1 rh #define ESM_DEBUG_CODECIO 0x0001 98 1.1 rh #define ESM_DEBUG_IRQ 0x0002 99 1.1 rh #define ESM_DEBUG_DMA 0x0004 100 1.1 rh #define ESM_DEBUG_TIMER 0x0008 101 1.1 rh #define ESM_DEBUG_REG 0x0010 102 1.1 rh #define ESM_DEBUG_PARAM 0x0020 103 1.1 rh #define ESM_DEBUG_APU 0x0040 104 1.1 rh #define ESM_DEBUG_CODEC 0x0080 105 1.3 rh #define ESM_DEBUG_PCI 0x0100 106 1.8 ichiro #define ESM_DEBUG_RESUME 0x0200 107 1.1 rh #else 108 1.1 rh #define DPRINTF(x,y) /* nothing */ 109 1.1 rh #define DUMPREG(x) /* nothing */ 110 1.1 rh #endif 111 1.1 rh 112 1.1 rh #ifdef DIAGNOSTIC 113 1.1 rh #define RANGE(n, l, h) if ((n) < (l) || (n) >= (h)) \ 114 1.1 rh printf (#n "=%d out of range (%d, %d) in " \ 115 1.1 rh __FILE__ ", line %d\n", (n), (l), (h), __LINE__) 116 1.1 rh #else 117 1.1 rh #define RANGE(x,y,z) /* nothing */ 118 1.1 rh #endif 119 1.1 rh 120 1.32 perry #define inline inline 121 1.1 rh 122 1.30 kent static inline void ringbus_setdest(struct esm_softc *, int, int); 123 1.1 rh 124 1.30 kent static inline uint16_t wp_rdreg(struct esm_softc *, uint16_t); 125 1.30 kent static inline void wp_wrreg(struct esm_softc *, uint16_t, uint16_t); 126 1.30 kent static inline uint16_t wp_rdapu(struct esm_softc *, int, uint16_t); 127 1.30 kent static inline void wp_wrapu(struct esm_softc *, int, uint16_t, 128 1.30 kent uint16_t); 129 1.1 rh static inline void wp_settimer(struct esm_softc *, u_int); 130 1.1 rh static inline void wp_starttimer(struct esm_softc *); 131 1.1 rh static inline void wp_stoptimer(struct esm_softc *); 132 1.1 rh 133 1.30 kent static inline void wc_wrreg(struct esm_softc *, uint16_t, uint16_t); 134 1.30 kent static inline void wc_wrchctl(struct esm_softc *, int, uint16_t); 135 1.1 rh 136 1.1 rh static inline u_int calc_timer_freq(struct esm_chinfo*); 137 1.1 rh static void set_timer(struct esm_softc *); 138 1.1 rh 139 1.1 rh static void esmch_set_format(struct esm_chinfo *, 140 1.29 kent const audio_params_t *); 141 1.18 fredette static void esmch_combine_input(struct esm_softc *, 142 1.29 kent struct esm_chinfo *); 143 1.1 rh 144 1.53 dyoung static bool esm_suspend(device_t, const pmf_qual_t *); 145 1.53 dyoung static bool esm_resume(device_t, const pmf_qual_t *); 146 1.45 dyoung static void esm_childdet(device_t, device_t); 147 1.48 cegger static int esm_match(device_t, cfdata_t, void *); 148 1.45 dyoung static void esm_attach(device_t, device_t, void *); 149 1.45 dyoung static int esm_detach(device_t, int); 150 1.45 dyoung static int esm_intr(void *); 151 1.45 dyoung 152 1.45 dyoung static void esm_freemem(struct esm_softc *, struct esm_dma *); 153 1.45 dyoung static int esm_allocmem(struct esm_softc *, size_t, size_t, 154 1.45 dyoung struct esm_dma *); 155 1.7 ichiro 156 1.45 dyoung 157 1.49 cegger CFATTACH_DECL2_NEW(esm, sizeof(struct esm_softc), 158 1.45 dyoung esm_match, esm_attach, esm_detach, NULL, NULL, esm_childdet); 159 1.1 rh 160 1.28 yamt const struct audio_hw_if esm_hw_if = { 161 1.62 isaki .query_format = esm_query_format, 162 1.62 isaki .set_format = esm_set_format, 163 1.61 isaki .round_blocksize = esm_round_blocksize, 164 1.61 isaki .init_output = esm_init_output, 165 1.61 isaki .init_input = esm_init_input, 166 1.61 isaki .halt_output = esm_halt_output, 167 1.61 isaki .halt_input = esm_halt_input, 168 1.61 isaki .getdev = esm_getdev, 169 1.61 isaki .set_port = esm_set_port, 170 1.61 isaki .get_port = esm_get_port, 171 1.61 isaki .query_devinfo = esm_query_devinfo, 172 1.61 isaki .allocm = esm_malloc, 173 1.61 isaki .freem = esm_free, 174 1.61 isaki .round_buffersize = esm_round_buffersize, 175 1.61 isaki .get_props = esm_get_props, 176 1.61 isaki .trigger_output = esm_trigger_output, 177 1.61 isaki .trigger_input = esm_trigger_input, 178 1.61 isaki .get_locks = esm_get_locks, 179 1.1 rh }; 180 1.1 rh 181 1.1 rh struct audio_device esm_device = { 182 1.1 rh "ESS Maestro", 183 1.1 rh "", 184 1.1 rh "esm" 185 1.1 rh }; 186 1.1 rh 187 1.62 isaki #define ESM_FORMAT(enc, prec, ch, chmask) \ 188 1.62 isaki { \ 189 1.62 isaki .mode = AUMODE_PLAY | AUMODE_RECORD, \ 190 1.62 isaki .encoding = (enc), \ 191 1.62 isaki .validbits = (prec), \ 192 1.62 isaki .precision = (prec), \ 193 1.62 isaki .channels = (ch), \ 194 1.62 isaki .channel_mask = (chmask), \ 195 1.62 isaki .frequency_type = 0, \ 196 1.62 isaki .frequency = { 4000, 48000 }, \ 197 1.62 isaki } 198 1.62 isaki /* 199 1.62 isaki * XXX Recodring on 16bit/stereo seems a bit tricky so I left all 200 1.62 isaki * combination 8/16bit and mono/stereo. 201 1.62 isaki */ 202 1.62 isaki static const struct audio_format esm_formats[] = { 203 1.62 isaki ESM_FORMAT(AUDIO_ENCODING_SLINEAR_LE, 16, 2, AUFMT_STEREO), 204 1.62 isaki ESM_FORMAT(AUDIO_ENCODING_SLINEAR_LE, 16, 1, AUFMT_MONAURAL), 205 1.62 isaki ESM_FORMAT(AUDIO_ENCODING_ULINEAR_LE, 8, 2, AUFMT_STEREO), 206 1.62 isaki ESM_FORMAT(AUDIO_ENCODING_ULINEAR_LE, 8, 1, AUFMT_MONAURAL), 207 1.29 kent }; 208 1.62 isaki #define ESM_NFORMATS __arraycount(esm_formats) 209 1.3 rh 210 1.3 rh static const struct esm_quirks esm_quirks[] = { 211 1.3 rh /* COMPAL 38W2 OEM Notebook, e.g. Dell INSPIRON 5000e */ 212 1.3 rh { PCI_VENDOR_COMPAL, PCI_PRODUCT_COMPAL_38W2, ESM_QUIRKF_SWAPPEDCH }, 213 1.3 rh 214 1.5 rh /* COMPAQ Armada M700 Notebook */ 215 1.5 rh { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_M700, ESM_QUIRKF_SWAPPEDCH }, 216 1.5 rh 217 1.3 rh /* NEC Versa Pro LX VA26D */ 218 1.3 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VA26D, ESM_QUIRKF_GPIO }, 219 1.3 rh 220 1.3 rh /* NEC Versa LX */ 221 1.6 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSALX, ESM_QUIRKF_GPIO }, 222 1.6 rh 223 1.10 simonb /* Toshiba Portege */ 224 1.10 simonb { PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_PORTEGE, ESM_QUIRKF_SWAPPEDCH } 225 1.3 rh }; 226 1.3 rh 227 1.3 rh enum esm_quirk_flags 228 1.3 rh esm_get_quirks(pcireg_t subid) 229 1.3 rh { 230 1.3 rh int i; 231 1.3 rh 232 1.50 cegger for (i = 0; i < __arraycount(esm_quirks); i++) { 233 1.3 rh if (PCI_VENDOR(subid) == esm_quirks[i].eq_vendor && 234 1.3 rh PCI_PRODUCT(subid) == esm_quirks[i].eq_product) { 235 1.3 rh return esm_quirks[i].eq_quirks; 236 1.3 rh } 237 1.3 rh } 238 1.3 rh 239 1.3 rh return 0; 240 1.3 rh } 241 1.3 rh 242 1.3 rh 243 1.1 rh #ifdef AUDIO_DEBUG 244 1.1 rh struct esm_reg_info { 245 1.1 rh int offset; /* register offset */ 246 1.1 rh int width; /* 1/2/4 bytes */ 247 1.1 rh } dump_regs[] = { 248 1.1 rh { PORT_WAVCACHE_CTRL, 2 }, 249 1.1 rh { PORT_HOSTINT_CTRL, 2 }, 250 1.1 rh { PORT_HOSTINT_STAT, 2 }, 251 1.1 rh { PORT_HWVOL_VOICE_SHADOW, 1 }, 252 1.1 rh { PORT_HWVOL_VOICE, 1 }, 253 1.1 rh { PORT_HWVOL_MASTER_SHADOW, 1 }, 254 1.1 rh { PORT_HWVOL_MASTER, 1 }, 255 1.1 rh { PORT_RINGBUS_CTRL, 4 }, 256 1.1 rh { PORT_GPIO_DATA, 2 }, 257 1.1 rh { PORT_GPIO_MASK, 2 }, 258 1.1 rh { PORT_GPIO_DIR, 2 }, 259 1.1 rh { PORT_ASSP_CTRL_A, 1 }, 260 1.1 rh { PORT_ASSP_CTRL_B, 1 }, 261 1.1 rh { PORT_ASSP_CTRL_C, 1 }, 262 1.3 rh { PORT_ASSP_INT_STAT, 1 } 263 1.1 rh }; 264 1.1 rh 265 1.2 lukem static void 266 1.2 lukem esm_dump_regs(struct esm_softc *ess) 267 1.1 rh { 268 1.3 rh int i; 269 1.1 rh 270 1.49 cegger printf("%s registers:", device_xname(ess->sc_dev)); 271 1.50 cegger for (i = 0; i < __arraycount(dump_regs); i++) { 272 1.1 rh if (i % 5 == 0) 273 1.1 rh printf("\n"); 274 1.1 rh printf("0x%2.2x: ", dump_regs[i].offset); 275 1.1 rh switch(dump_regs[i].width) { 276 1.1 rh case 4: 277 1.1 rh printf("%8.8x, ", bus_space_read_4(ess->st, ess->sh, 278 1.1 rh dump_regs[i].offset)); 279 1.1 rh break; 280 1.1 rh case 2: 281 1.1 rh printf("%4.4x, ", bus_space_read_2(ess->st, ess->sh, 282 1.1 rh dump_regs[i].offset)); 283 1.1 rh break; 284 1.1 rh default: 285 1.1 rh printf("%2.2x, ", 286 1.1 rh bus_space_read_1(ess->st, ess->sh, 287 1.1 rh dump_regs[i].offset)); 288 1.1 rh } 289 1.1 rh } 290 1.1 rh printf("\n"); 291 1.1 rh } 292 1.1 rh #endif 293 1.1 rh 294 1.3 rh 295 1.1 rh /* ----------------------------- 296 1.1 rh * Subsystems. 297 1.1 rh */ 298 1.1 rh 299 1.1 rh /* Codec/Ringbus */ 300 1.1 rh 301 1.1 rh /* -------------------------------------------------------------------- */ 302 1.1 rh 303 1.1 rh int 304 1.30 kent esm_read_codec(void *sc, uint8_t regno, uint16_t *result) 305 1.1 rh { 306 1.30 kent struct esm_softc *ess; 307 1.1 rh unsigned t; 308 1.1 rh 309 1.30 kent ess = sc; 310 1.1 rh /* We have to wait for a SAFE time to write addr/data */ 311 1.1 rh for (t = 0; t < 20; t++) { 312 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT) 313 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS) 314 1.1 rh break; 315 1.1 rh delay(2); /* 20.8us / 13 */ 316 1.1 rh } 317 1.1 rh if (t == 20) 318 1.1 rh printf("%s: esm_read_codec() PROGLESS timed out.\n", 319 1.49 cegger device_xname(ess->sc_dev)); 320 1.1 rh 321 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD, 322 1.1 rh CODEC_CMD_READ | regno); 323 1.1 rh delay(21); /* AC97 cycle = 20.8usec */ 324 1.1 rh 325 1.1 rh /* Wait for data retrieve */ 326 1.1 rh for (t = 0; t < 20; t++) { 327 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT) 328 1.1 rh & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE) 329 1.1 rh break; 330 1.1 rh delay(2); /* 20.8us / 13 */ 331 1.1 rh } 332 1.1 rh if (t == 20) 333 1.1 rh /* Timed out, but perform dummy read. */ 334 1.1 rh printf("%s: esm_read_codec() RW_DONE timed out.\n", 335 1.49 cegger device_xname(ess->sc_dev)); 336 1.1 rh 337 1.1 rh *result = bus_space_read_2(ess->st, ess->sh, PORT_CODEC_REG); 338 1.1 rh 339 1.1 rh return 0; 340 1.1 rh } 341 1.1 rh 342 1.1 rh int 343 1.30 kent esm_write_codec(void *sc, uint8_t regno, uint16_t data) 344 1.1 rh { 345 1.30 kent struct esm_softc *ess; 346 1.1 rh unsigned t; 347 1.1 rh 348 1.30 kent ess = sc; 349 1.1 rh /* We have to wait for a SAFE time to write addr/data */ 350 1.1 rh for (t = 0; t < 20; t++) { 351 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT) 352 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS) 353 1.1 rh break; 354 1.1 rh delay(2); /* 20.8us / 13 */ 355 1.1 rh } 356 1.1 rh if (t == 20) { 357 1.1 rh /* Timed out. Abort writing. */ 358 1.1 rh printf("%s: esm_write_codec() PROGLESS timed out.\n", 359 1.49 cegger device_xname(ess->sc_dev)); 360 1.1 rh return -1; 361 1.1 rh } 362 1.1 rh 363 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_CODEC_REG, data); 364 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD, 365 1.1 rh CODEC_CMD_WRITE | regno); 366 1.1 rh 367 1.1 rh return 0; 368 1.1 rh } 369 1.1 rh 370 1.1 rh /* -------------------------------------------------------------------- */ 371 1.1 rh 372 1.1 rh static inline void 373 1.1 rh ringbus_setdest(struct esm_softc *ess, int src, int dest) 374 1.1 rh { 375 1.30 kent uint32_t data; 376 1.1 rh 377 1.1 rh data = bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL); 378 1.1 rh data &= ~(0xfU << src); 379 1.1 rh data |= (0xfU & dest) << src; 380 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, data); 381 1.1 rh } 382 1.1 rh 383 1.1 rh /* Wave Processor */ 384 1.1 rh 385 1.30 kent static inline uint16_t 386 1.30 kent wp_rdreg(struct esm_softc *ess, uint16_t reg) 387 1.1 rh { 388 1.30 kent 389 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg); 390 1.1 rh return bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA); 391 1.1 rh } 392 1.1 rh 393 1.1 rh static inline void 394 1.30 kent wp_wrreg(struct esm_softc *ess, uint16_t reg, uint16_t data) 395 1.1 rh { 396 1.30 kent 397 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg); 398 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data); 399 1.1 rh } 400 1.1 rh 401 1.1 rh static inline void 402 1.30 kent apu_setindex(struct esm_softc *ess, uint16_t reg) 403 1.1 rh { 404 1.1 rh int t; 405 1.1 rh 406 1.1 rh wp_wrreg(ess, WPREG_CRAM_PTR, reg); 407 1.1 rh /* Sometimes WP fails to set apu register index. */ 408 1.1 rh for (t = 0; t < 1000; t++) { 409 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == reg) 410 1.1 rh break; 411 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, reg); 412 1.1 rh } 413 1.1 rh if (t == 1000) 414 1.49 cegger printf("%s: apu_setindex() timed out.\n", device_xname(ess->sc_dev)); 415 1.1 rh } 416 1.1 rh 417 1.30 kent static inline uint16_t 418 1.30 kent wp_rdapu(struct esm_softc *ess, int ch, uint16_t reg) 419 1.1 rh { 420 1.30 kent uint16_t ret; 421 1.1 rh 422 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg); 423 1.1 rh ret = wp_rdreg(ess, WPREG_DATA_PORT); 424 1.1 rh return ret; 425 1.1 rh } 426 1.1 rh 427 1.1 rh static inline void 428 1.30 kent wp_wrapu(struct esm_softc *ess, int ch, uint16_t reg, uint16_t data) 429 1.1 rh { 430 1.1 rh int t; 431 1.1 rh 432 1.1 rh DPRINTF(ESM_DEBUG_APU, 433 1.1 rh ("wp_wrapu(%p, ch=%d, reg=0x%x, data=0x%04x)\n", 434 1.1 rh ess, ch, reg, data)); 435 1.1 rh 436 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg); 437 1.1 rh wp_wrreg(ess, WPREG_DATA_PORT, data); 438 1.1 rh for (t = 0; t < 1000; t++) { 439 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == data) 440 1.1 rh break; 441 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data); 442 1.1 rh } 443 1.1 rh if (t == 1000) 444 1.49 cegger printf("%s: wp_wrapu() timed out.\n", device_xname(ess->sc_dev)); 445 1.1 rh } 446 1.1 rh 447 1.1 rh static inline void 448 1.1 rh wp_settimer(struct esm_softc *ess, u_int freq) 449 1.1 rh { 450 1.30 kent u_int clock; 451 1.30 kent u_int prescale, divide; 452 1.1 rh 453 1.30 kent clock = 48000 << 2; 454 1.30 kent prescale = 0; 455 1.30 kent divide = (freq != 0) ? (clock / freq) : ~0; 456 1.1 rh RANGE(divide, WPTIMER_MINDIV, WPTIMER_MAXDIV); 457 1.1 rh 458 1.1 rh for (; divide > 32 << 1; divide >>= 1) 459 1.1 rh prescale++; 460 1.1 rh divide = (divide + 1) >> 1; 461 1.1 rh 462 1.1 rh for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1) 463 1.1 rh prescale++; 464 1.1 rh 465 1.1 rh DPRINTF(ESM_DEBUG_TIMER, 466 1.1 rh ("wp_settimer(%p, %u): clock = %u, prescale = %u, divide = %u\n", 467 1.1 rh ess, freq, clock, prescale, divide)); 468 1.1 rh 469 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 0); 470 1.1 rh wp_wrreg(ess, WPREG_TIMER_FREQ, 471 1.1 rh (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1)); 472 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 1); 473 1.1 rh } 474 1.1 rh 475 1.1 rh static inline void 476 1.1 rh wp_starttimer(struct esm_softc *ess) 477 1.1 rh { 478 1.30 kent 479 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 1); 480 1.1 rh } 481 1.1 rh 482 1.1 rh static inline void 483 1.1 rh wp_stoptimer(struct esm_softc *ess) 484 1.1 rh { 485 1.30 kent 486 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 0); 487 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1); 488 1.1 rh } 489 1.1 rh 490 1.1 rh /* WaveCache */ 491 1.1 rh 492 1.1 rh static inline void 493 1.30 kent wc_wrreg(struct esm_softc *ess, uint16_t reg, uint16_t data) 494 1.1 rh { 495 1.30 kent 496 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg); 497 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_DATA, data); 498 1.1 rh } 499 1.1 rh 500 1.1 rh static inline void 501 1.30 kent wc_wrchctl(struct esm_softc *ess, int ch, uint16_t data) 502 1.1 rh { 503 1.30 kent 504 1.1 rh wc_wrreg(ess, ch << 3, data); 505 1.1 rh } 506 1.1 rh 507 1.1 rh /* ----------------------------- 508 1.1 rh * Controller. 509 1.1 rh */ 510 1.1 rh 511 1.1 rh int 512 1.1 rh esm_attach_codec(void *sc, struct ac97_codec_if *codec_if) 513 1.1 rh { 514 1.30 kent struct esm_softc *ess; 515 1.1 rh 516 1.30 kent ess = sc; 517 1.1 rh ess->codec_if = codec_if; 518 1.1 rh 519 1.1 rh return 0; 520 1.1 rh } 521 1.1 rh 522 1.27 kent int 523 1.41 christos esm_reset_codec(void *sc) 524 1.1 rh { 525 1.30 kent 526 1.27 kent return 0; 527 1.1 rh } 528 1.1 rh 529 1.1 rh 530 1.3 rh enum ac97_host_flags 531 1.3 rh esm_flags_codec(void *sc) 532 1.3 rh { 533 1.30 kent struct esm_softc *ess; 534 1.3 rh 535 1.30 kent ess = sc; 536 1.3 rh return ess->codec_flags; 537 1.3 rh } 538 1.3 rh 539 1.3 rh 540 1.1 rh void 541 1.1 rh esm_initcodec(struct esm_softc *ess) 542 1.1 rh { 543 1.30 kent uint16_t data; 544 1.1 rh 545 1.1 rh DPRINTF(ESM_DEBUG_CODEC, ("esm_initcodec(%p)\n", ess)); 546 1.1 rh 547 1.1 rh if (bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL) 548 1.1 rh & RINGBUS_CTRL_ACLINK_ENABLED) { 549 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0); 550 1.1 rh delay(104); /* 20.8us * (4 + 1) */ 551 1.1 rh } 552 1.1 rh /* XXX - 2nd codec should be looked at. */ 553 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 554 1.1 rh RINGBUS_CTRL_AC97_SWRESET); 555 1.1 rh delay(2); 556 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 557 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED); 558 1.1 rh delay(21); 559 1.1 rh 560 1.1 rh esm_read_codec(ess, 0, &data); 561 1.1 rh if (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT) 562 1.1 rh & CODEC_STAT_MASK) { 563 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0); 564 1.1 rh delay(21); 565 1.1 rh 566 1.1 rh /* Try cold reset. */ 567 1.49 cegger printf("%s: will perform cold reset.\n", device_xname(ess->sc_dev)); 568 1.1 rh data = bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR); 569 1.1 rh if (pci_conf_read(ess->pc, ess->tag, 0x58) & 1) 570 1.1 rh data |= 0x10; 571 1.1 rh data |= 0x009 & 572 1.1 rh ~bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DATA); 573 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0xff6); 574 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, 575 1.1 rh data | 0x009); 576 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x000); 577 1.1 rh delay(2); 578 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x001); 579 1.1 rh delay(1); 580 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x009); 581 1.1 rh delay(500000); 582 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, data); 583 1.1 rh delay(84); /* 20.8us * 4 */ 584 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 585 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED); 586 1.1 rh delay(21); 587 1.1 rh } 588 1.1 rh } 589 1.1 rh 590 1.1 rh void 591 1.1 rh esm_init(struct esm_softc *ess) 592 1.1 rh { 593 1.30 kent 594 1.1 rh /* Reset direct sound. */ 595 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 596 1.1 rh HOSTINT_CTRL_DSOUND_RESET); 597 1.1 rh delay(10000); 598 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0); 599 1.1 rh delay(10000); 600 1.1 rh 601 1.1 rh /* Enable direct sound interruption. */ 602 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 603 1.1 rh HOSTINT_CTRL_DSOUND_INT_ENABLED); 604 1.1 rh 605 1.1 rh /* Setup Wave Processor. */ 606 1.1 rh 607 1.1 rh /* Enable WaveCache */ 608 1.1 rh wp_wrreg(ess, WPREG_WAVE_ROMRAM, 609 1.1 rh WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED); 610 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_CTRL, 611 1.1 rh WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB); 612 1.1 rh 613 1.1 rh /* Setup Codec/Ringbus. */ 614 1.1 rh esm_initcodec(ess); 615 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 616 1.1 rh RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED); 617 1.1 rh 618 1.18 fredette /* Undocumented registers from the Linux driver. */ 619 1.18 fredette wp_wrreg(ess, 0x8, 0xB004); 620 1.18 fredette wp_wrreg(ess, 0x9, 0x001B); 621 1.18 fredette wp_wrreg(ess, 0xA, 0x8000); 622 1.18 fredette wp_wrreg(ess, 0xB, 0x3F37); 623 1.18 fredette wp_wrreg(ess, 0xD, 0x7632); 624 1.18 fredette 625 1.18 fredette wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */ 626 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_ADC, 627 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN); 628 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_DSOUND, 629 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC); 630 1.1 rh 631 1.1 rh /* Setup ASSP. Needed for Dell Inspiron 7500? */ 632 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_B, 0x00); 633 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_A, 0x03); 634 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_C, 0x00); 635 1.1 rh 636 1.1 rh /* 637 1.1 rh * Setup GPIO. 638 1.1 rh * There seems to be speciality with NEC systems. 639 1.1 rh */ 640 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_GPIO) { 641 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 642 1.3 rh 0x9ff); 643 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, 644 1.3 rh bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR) | 645 1.3 rh 0x600); 646 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 647 1.3 rh 0x200); 648 1.1 rh } 649 1.1 rh 650 1.1 rh DUMPREG(ess); 651 1.1 rh } 652 1.1 rh 653 1.1 rh /* Channel controller. */ 654 1.1 rh 655 1.1 rh int 656 1.41 christos esm_init_output (void *sc, void *start, int size) 657 1.1 rh { 658 1.30 kent struct esm_softc *ess; 659 1.1 rh struct esm_dma *p; 660 1.1 rh 661 1.30 kent ess = sc; 662 1.18 fredette p = &ess->sc_dma; 663 1.42 christos if ((char *)start != (char *)p->addr + MAESTRO_PLAYBUF_OFF) { 664 1.1 rh printf("%s: esm_init_output: bad addr %p\n", 665 1.49 cegger device_xname(ess->sc_dev), start); 666 1.1 rh return EINVAL; 667 1.1 rh } 668 1.1 rh 669 1.18 fredette ess->pch.base = DMAADDR(p) + MAESTRO_PLAYBUF_OFF; 670 1.1 rh 671 1.1 rh DPRINTF(ESM_DEBUG_DMA, ("%s: pch.base = 0x%x\n", 672 1.49 cegger device_xname(ess->sc_dev), ess->pch.base)); 673 1.1 rh 674 1.18 fredette return 0; 675 1.18 fredette } 676 1.18 fredette 677 1.18 fredette int 678 1.41 christos esm_init_input (void *sc, void *start, int size) 679 1.18 fredette { 680 1.30 kent struct esm_softc *ess; 681 1.18 fredette struct esm_dma *p; 682 1.18 fredette 683 1.30 kent ess = sc; 684 1.18 fredette p = &ess->sc_dma; 685 1.42 christos if ((char *)start != (char *)p->addr + MAESTRO_RECBUF_OFF) { 686 1.18 fredette printf("%s: esm_init_input: bad addr %p\n", 687 1.49 cegger device_xname(ess->sc_dev), start); 688 1.18 fredette return EINVAL; 689 1.18 fredette } 690 1.18 fredette 691 1.18 fredette switch (ess->rch.aputype) { 692 1.18 fredette case APUTYPE_16BITSTEREO: 693 1.18 fredette ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_L_OFF; 694 1.18 fredette break; 695 1.18 fredette default: 696 1.18 fredette ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_OFF; 697 1.18 fredette break; 698 1.18 fredette } 699 1.18 fredette 700 1.18 fredette DPRINTF(ESM_DEBUG_DMA, ("%s: rch.base = 0x%x\n", 701 1.49 cegger device_xname(ess->sc_dev), ess->rch.base)); 702 1.1 rh 703 1.1 rh return 0; 704 1.1 rh } 705 1.1 rh 706 1.1 rh int 707 1.1 rh esm_trigger_output(void *sc, void *start, void *end, int blksize, 708 1.41 christos void (*intr)(void *), void *arg, const audio_params_t *param) 709 1.1 rh { 710 1.30 kent size_t size; 711 1.30 kent struct esm_softc *ess; 712 1.30 kent struct esm_chinfo *ch; 713 1.1 rh struct esm_dma *p; 714 1.30 kent int pan, choffset; 715 1.30 kent int i, nch; 716 1.30 kent unsigned speed, offset, wpwa, dv; 717 1.30 kent uint16_t apuch; 718 1.1 rh 719 1.1 rh DPRINTF(ESM_DEBUG_DMA, 720 1.1 rh ("esm_trigger_output(%p, %p, %p, 0x%x, %p, %p, %p)\n", 721 1.1 rh sc, start, end, blksize, intr, arg, param)); 722 1.30 kent ess = sc; 723 1.30 kent ch = &ess->pch; 724 1.30 kent pan = 0; 725 1.30 kent nch = 1; 726 1.30 kent speed = ch->sample_rate; 727 1.30 kent apuch = ch->num << 1; 728 1.1 rh 729 1.1 rh #ifdef DIAGNOSTIC 730 1.1 rh if (ess->pactive) { 731 1.1 rh printf("%s: esm_trigger_output: already running", 732 1.49 cegger device_xname(ess->sc_dev)); 733 1.1 rh return EINVAL; 734 1.1 rh } 735 1.1 rh #endif 736 1.1 rh 737 1.1 rh ess->sc_pintr = intr; 738 1.1 rh ess->sc_parg = arg; 739 1.18 fredette p = &ess->sc_dma; 740 1.42 christos if ((char *)start != (char *)p->addr + MAESTRO_PLAYBUF_OFF) { 741 1.1 rh printf("%s: esm_trigger_output: bad addr %p\n", 742 1.49 cegger device_xname(ess->sc_dev), start); 743 1.1 rh return EINVAL; 744 1.1 rh } 745 1.1 rh 746 1.1 rh ess->pch.blocksize = blksize; 747 1.1 rh ess->pch.apublk = blksize >> 1; 748 1.1 rh ess->pactive = 1; 749 1.1 rh 750 1.42 christos size = (size_t)(((char *)end - (char *)start) >> 1); 751 1.18 fredette choffset = MAESTRO_PLAYBUF_OFF; 752 1.1 rh offset = choffset >> 1; 753 1.18 fredette wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK); 754 1.1 rh 755 1.1 rh DPRINTF(ESM_DEBUG_DMA, 756 1.26 kleink ("choffs=0x%x, wpwa=0x%x, size=0x%lx words\n", 757 1.26 kleink choffset, wpwa, (unsigned long int)size)); 758 1.1 rh 759 1.1 rh switch (ch->aputype) { 760 1.1 rh case APUTYPE_16BITSTEREO: 761 1.1 rh ess->pch.apublk >>= 1; 762 1.1 rh wpwa >>= 1; 763 1.1 rh size >>= 1; 764 1.1 rh offset >>= 1; 765 1.1 rh /* FALLTHROUGH */ 766 1.1 rh case APUTYPE_8BITSTEREO: 767 1.3 rh if (ess->codec_flags & AC97_HOST_SWAPPED_CHANNELS) 768 1.3 rh pan = 8; 769 1.3 rh else 770 1.3 rh pan = -8; 771 1.3 rh nch++; 772 1.1 rh break; 773 1.1 rh case APUTYPE_8BITLINEAR: 774 1.1 rh ess->pch.apublk <<= 1; 775 1.1 rh speed >>= 1; 776 1.1 rh break; 777 1.1 rh } 778 1.1 rh 779 1.18 fredette ess->pch.apubase = offset; 780 1.1 rh ess->pch.apubuf = size; 781 1.1 rh ess->pch.nextirq = ess->pch.apublk; 782 1.1 rh 783 1.1 rh set_timer(ess); 784 1.1 rh wp_starttimer(ess); 785 1.1 rh 786 1.1 rh dv = (((speed % 48000) << 16) + 24000) / 48000 787 1.1 rh + ((speed / 48000) << 16); 788 1.1 rh 789 1.3 rh for (i = nch-1; i >= 0; i--) { 790 1.3 rh wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa & 0xff00); 791 1.3 rh wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset); 792 1.3 rh wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size); 793 1.3 rh wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1); 794 1.3 rh wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800); 795 1.3 rh wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00 796 1.1 rh | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 797 1.1 rh | ((PAN_FRONT + pan) << APU_PAN_SHIFT)); 798 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB 799 1.1 rh | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); 800 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8); 801 1.1 rh 802 1.1 rh if (ch->aputype == APUTYPE_16BITSTEREO) 803 1.1 rh wpwa |= APU_STEREO >> 1; 804 1.1 rh pan = -pan; 805 1.3 rh } 806 1.1 rh 807 1.1 rh wc_wrchctl(ess, apuch, ch->wcreg_tpl); 808 1.3 rh if (nch > 1) 809 1.3 rh wc_wrchctl(ess, apuch + 1, ch->wcreg_tpl); 810 1.1 rh 811 1.1 rh wp_wrapu(ess, apuch, APUREG_APUTYPE, 812 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 813 1.1 rh if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO) 814 1.1 rh wp_wrapu(ess, apuch + 1, APUREG_APUTYPE, 815 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf); 816 1.1 rh 817 1.1 rh return 0; 818 1.1 rh } 819 1.1 rh 820 1.1 rh int 821 1.1 rh esm_trigger_input(void *sc, void *start, void *end, int blksize, 822 1.41 christos void (*intr)(void *), void *arg, const audio_params_t *param) 823 1.1 rh { 824 1.18 fredette size_t size; 825 1.18 fredette size_t mixsize; 826 1.30 kent struct esm_softc *ess; 827 1.30 kent struct esm_chinfo *ch; 828 1.30 kent struct esm_dma *p; 829 1.30 kent uint32_t chctl, choffset; 830 1.30 kent uint32_t speed, offset, wpwa, dv; 831 1.30 kent uint32_t mixoffset, mixdv; 832 1.30 kent int i, nch; 833 1.30 kent uint16_t apuch; 834 1.30 kent uint16_t reg; 835 1.18 fredette 836 1.18 fredette DPRINTF(ESM_DEBUG_DMA, 837 1.18 fredette ("esm_trigger_input(%p, %p, %p, 0x%x, %p, %p, %p)\n", 838 1.18 fredette sc, start, end, blksize, intr, arg, param)); 839 1.30 kent ess = sc; 840 1.30 kent ch = &ess->rch; 841 1.30 kent nch = 1; 842 1.30 kent speed = ch->sample_rate; 843 1.30 kent apuch = ch->num << 1; 844 1.18 fredette 845 1.18 fredette #ifdef DIAGNOSTIC 846 1.18 fredette if (ess->ractive) { 847 1.18 fredette printf("%s: esm_trigger_input: already running", 848 1.49 cegger device_xname(ess->sc_dev)); 849 1.18 fredette return EINVAL; 850 1.18 fredette } 851 1.18 fredette #endif 852 1.18 fredette 853 1.18 fredette ess->sc_rintr = intr; 854 1.18 fredette ess->sc_rarg = arg; 855 1.18 fredette p = &ess->sc_dma; 856 1.42 christos if ((char *)start != (char *)p->addr + MAESTRO_RECBUF_OFF) { 857 1.18 fredette printf("%s: esm_trigger_input: bad addr %p\n", 858 1.49 cegger device_xname(ess->sc_dev), start); 859 1.18 fredette return EINVAL; 860 1.18 fredette } 861 1.18 fredette 862 1.42 christos ess->rch.buffer = (void *)start; 863 1.18 fredette ess->rch.offset = 0; 864 1.18 fredette ess->rch.blocksize = blksize; 865 1.42 christos ess->rch.bufsize = ((char *)end - (char *)start); 866 1.18 fredette ess->rch.apublk = blksize >> 1; 867 1.18 fredette ess->ractive = 1; 868 1.18 fredette 869 1.42 christos size = (size_t)(((char *)end - (char *)start) >> 1); 870 1.18 fredette choffset = MAESTRO_RECBUF_OFF; 871 1.18 fredette switch (ch->aputype) { 872 1.18 fredette case APUTYPE_16BITSTEREO: 873 1.18 fredette size >>= 1; 874 1.18 fredette choffset = MAESTRO_RECBUF_L_OFF; 875 1.18 fredette ess->rch.apublk >>= 1; 876 1.18 fredette nch++; 877 1.18 fredette break; 878 1.18 fredette case APUTYPE_16BITLINEAR: 879 1.18 fredette break; 880 1.18 fredette default: 881 1.18 fredette ess->ractive = 0; 882 1.18 fredette return EINVAL; 883 1.18 fredette } 884 1.18 fredette 885 1.18 fredette mixsize = (MAESTRO_MIXBUF_SZ >> 1) >> 1; 886 1.18 fredette mixoffset = MAESTRO_MIXBUF_OFF; 887 1.18 fredette 888 1.18 fredette ess->rch.apubase = (choffset >> 1); 889 1.18 fredette ess->rch.apubuf = size; 890 1.18 fredette ess->rch.nextirq = ess->rch.apublk; 891 1.18 fredette 892 1.18 fredette set_timer(ess); 893 1.18 fredette wp_starttimer(ess); 894 1.18 fredette 895 1.18 fredette if (speed > 47999) speed = 47999; 896 1.18 fredette if (speed < 4000) speed = 4000; 897 1.18 fredette dv = (((speed % 48000) << 16) + 24000) / 48000 898 1.18 fredette + ((speed / 48000) << 16); 899 1.33 lukem mixdv = 65536; /* 48 kHz */ 900 1.18 fredette 901 1.18 fredette for (i = 0; i < nch; i++) { 902 1.18 fredette 903 1.18 fredette /* Clear all rate conversion WP channel registers first. */ 904 1.18 fredette for (reg = 0; reg < 15; reg++) 905 1.18 fredette wp_wrapu(ess, apuch + i, reg, 0); 906 1.18 fredette 907 1.18 fredette /* Program the WaveCache for the rate conversion WP channel. */ 908 1.18 fredette chctl = (DMAADDR(p) + choffset - 0x10) & 909 1.18 fredette WAVCACHE_CHCTL_ADDRTAG_MASK; 910 1.18 fredette wc_wrchctl(ess, apuch + i, chctl); 911 1.18 fredette 912 1.18 fredette /* Program the rate conversion WP channel. */ 913 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB 914 1.18 fredette | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT) | 0x08); 915 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8); 916 1.18 fredette offset = choffset >> 1; 917 1.18 fredette wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK); 918 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa); 919 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset); 920 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size); 921 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1); 922 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_EFFECTS_ENV, 0x00f0); 923 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800); 924 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00 925 1.18 fredette | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 926 1.18 fredette | (PAN_FRONT << APU_PAN_SHIFT)); 927 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_ROUTE, apuch + 2 + i); 928 1.18 fredette 929 1.18 fredette DPRINTF(ESM_DEBUG_DMA, 930 1.26 kleink ("choffs=0x%x, wpwa=0x%x, offset=0x%x words, size=0x%lx words\n", 931 1.26 kleink choffset, wpwa, offset, (unsigned long int)size)); 932 1.18 fredette 933 1.18 fredette /* Clear all mixer WP channel registers first. */ 934 1.18 fredette for (reg = 0; reg < 15; reg++) 935 1.18 fredette wp_wrapu(ess, apuch + 2 + i, reg, 0); 936 1.18 fredette 937 1.18 fredette /* Program the WaveCache for the mixer WP channel. */ 938 1.18 fredette chctl = (ess->rch.base + mixoffset - 0x10) & 939 1.18 fredette WAVCACHE_CHCTL_ADDRTAG_MASK; 940 1.18 fredette wc_wrchctl(ess, apuch + 2 + i, chctl); 941 1.18 fredette 942 1.18 fredette /* Program the mixer WP channel. */ 943 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_FREQ_LOBYTE, APU_plus6dB 944 1.18 fredette | ((mixdv & 0xff) << APU_FREQ_LOBYTE_SHIFT) | 0x08); 945 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_FREQ_HIWORD, mixdv >> 8); 946 1.18 fredette offset = mixoffset >> 1; 947 1.18 fredette wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK); 948 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_WAVESPACE, wpwa); 949 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_CURPTR, offset); 950 1.30 kent wp_wrapu(ess, apuch + 2 + i, APUREG_ENDPTR, 951 1.18 fredette offset + mixsize); 952 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_LOOPLEN, mixsize); 953 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_EFFECTS_ENV, 0x00f0); 954 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_AMPLITUDE, 0xe800); 955 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_POSITION, 0x8f00 956 1.18 fredette | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT) 957 1.18 fredette | (PAN_FRONT << APU_PAN_SHIFT)); 958 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_ROUTE, 959 1.18 fredette ROUTE_PARALLEL + i); 960 1.18 fredette 961 1.18 fredette DPRINTF(ESM_DEBUG_DMA, 962 1.26 kleink ("mixoffs=0x%x, wpwa=0x%x, offset=0x%x words, size=0x%lx words\n", 963 1.26 kleink mixoffset, wpwa, offset, (unsigned long int)mixsize)); 964 1.18 fredette 965 1.18 fredette /* Assume we're going to loop to do the right channel. */ 966 1.18 fredette choffset += MAESTRO_RECBUF_L_SZ; 967 1.18 fredette mixoffset += MAESTRO_MIXBUF_SZ >> 1; 968 1.18 fredette } 969 1.18 fredette 970 1.18 fredette wp_wrapu(ess, apuch, APUREG_APUTYPE, 971 1.18 fredette (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | 972 1.18 fredette APU_DMA_ENABLED | 0xf); 973 1.18 fredette if (nch > 1) 974 1.18 fredette wp_wrapu(ess, apuch + 1, APUREG_APUTYPE, 975 1.18 fredette (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | 976 1.18 fredette APU_DMA_ENABLED | 0xf); 977 1.18 fredette wp_wrapu(ess, apuch + 2, APUREG_APUTYPE, 978 1.18 fredette (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 979 1.18 fredette APU_DMA_ENABLED | 0xf); 980 1.18 fredette if (nch > 1) 981 1.18 fredette wp_wrapu(ess, apuch + 3, APUREG_APUTYPE, 982 1.18 fredette (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | 983 1.18 fredette APU_DMA_ENABLED | 0xf); 984 1.18 fredette 985 1.1 rh return 0; 986 1.1 rh } 987 1.1 rh 988 1.1 rh int 989 1.1 rh esm_halt_output(void *sc) 990 1.1 rh { 991 1.30 kent struct esm_softc *ess; 992 1.30 kent struct esm_chinfo *ch; 993 1.1 rh 994 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_output(%p)\n", sc)); 995 1.30 kent ess = sc; 996 1.30 kent ch = &ess->pch; 997 1.1 rh 998 1.1 rh wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE, 999 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1000 1.1 rh wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE, 1001 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1002 1.1 rh 1003 1.1 rh ess->pactive = 0; 1004 1.1 rh if (!ess->ractive) 1005 1.1 rh wp_stoptimer(ess); 1006 1.1 rh 1007 1.1 rh return 0; 1008 1.1 rh } 1009 1.1 rh 1010 1.1 rh int 1011 1.1 rh esm_halt_input(void *sc) 1012 1.1 rh { 1013 1.30 kent struct esm_softc *ess; 1014 1.30 kent struct esm_chinfo *ch; 1015 1.18 fredette 1016 1.18 fredette DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_input(%p)\n", sc)); 1017 1.30 kent ess = sc; 1018 1.30 kent ch = &ess->rch; 1019 1.18 fredette 1020 1.18 fredette wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE, 1021 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1022 1.18 fredette wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE, 1023 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1024 1.18 fredette wp_wrapu(ess, (ch->num << 1) + 2, APUREG_APUTYPE, 1025 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1026 1.18 fredette wp_wrapu(ess, (ch->num << 1) + 3, APUREG_APUTYPE, 1027 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); 1028 1.18 fredette 1029 1.18 fredette ess->ractive = 0; 1030 1.18 fredette if (!ess->pactive) 1031 1.18 fredette wp_stoptimer(ess); 1032 1.18 fredette 1033 1.1 rh return 0; 1034 1.1 rh } 1035 1.1 rh 1036 1.1 rh static inline u_int 1037 1.1 rh calc_timer_freq(struct esm_chinfo *ch) 1038 1.1 rh { 1039 1.1 rh u_int freq; 1040 1.1 rh 1041 1.1 rh freq = (ch->sample_rate + ch->apublk - 1) / ch->apublk; 1042 1.1 rh 1043 1.1 rh DPRINTF(ESM_DEBUG_TIMER, 1044 1.1 rh ("calc_timer_freq(%p): rate = %u, blk = 0x%x (0x%x): freq = %u\n", 1045 1.1 rh ch, ch->sample_rate, ch->apublk, ch->blocksize, freq)); 1046 1.1 rh 1047 1.1 rh return freq; 1048 1.1 rh } 1049 1.1 rh 1050 1.1 rh static void 1051 1.1 rh set_timer(struct esm_softc *ess) 1052 1.1 rh { 1053 1.30 kent unsigned freq, freq2; 1054 1.1 rh 1055 1.30 kent freq = 0; 1056 1.1 rh if (ess->pactive) 1057 1.1 rh freq = calc_timer_freq(&ess->pch); 1058 1.1 rh 1059 1.1 rh if (ess->ractive) { 1060 1.1 rh freq2 = calc_timer_freq(&ess->rch); 1061 1.18 fredette if (freq2 > freq) 1062 1.1 rh freq = freq2; 1063 1.1 rh } 1064 1.1 rh 1065 1.18 fredette KASSERT(freq != 0); 1066 1.18 fredette 1067 1.1 rh for (; freq < MAESTRO_MINFREQ; freq <<= 1) 1068 1.30 kent continue; 1069 1.1 rh 1070 1.1 rh if (freq > 0) 1071 1.1 rh wp_settimer(ess, freq); 1072 1.1 rh } 1073 1.1 rh 1074 1.1 rh static void 1075 1.29 kent esmch_set_format(struct esm_chinfo *ch, const audio_params_t *p) 1076 1.1 rh { 1077 1.30 kent uint16_t wcreg_tpl; 1078 1.30 kent uint16_t aputype; 1079 1.1 rh 1080 1.30 kent wcreg_tpl = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK; 1081 1.30 kent aputype = APUTYPE_16BITLINEAR; 1082 1.1 rh if (p->channels == 2) { 1083 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_STEREO; 1084 1.1 rh aputype++; 1085 1.1 rh } 1086 1.29 kent if (p->precision == 8) { 1087 1.1 rh aputype += 2; 1088 1.25 simonb switch (p->encoding) { 1089 1.25 simonb case AUDIO_ENCODING_ULINEAR: 1090 1.25 simonb case AUDIO_ENCODING_ULINEAR_BE: 1091 1.25 simonb case AUDIO_ENCODING_ULINEAR_LE: 1092 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_U8; 1093 1.25 simonb break; 1094 1.25 simonb } 1095 1.1 rh } 1096 1.1 rh ch->wcreg_tpl = wcreg_tpl; 1097 1.1 rh ch->aputype = aputype; 1098 1.1 rh ch->sample_rate = p->sample_rate; 1099 1.1 rh 1100 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esmch_set_format: " 1101 1.29 kent "numch=%u, prec=%u, tpl=0x%x, aputype=%d, rate=%u\n", 1102 1.29 kent p->channels, p->precision, wcreg_tpl, aputype, p->sample_rate)); 1103 1.1 rh } 1104 1.1 rh 1105 1.18 fredette /* 1106 1.18 fredette * Since we can't record in true stereo, this function combines 1107 1.30 kent * the separately recorded left and right channels into the final 1108 1.18 fredette * buffer for the upper layer. 1109 1.18 fredette */ 1110 1.18 fredette static void 1111 1.18 fredette esmch_combine_input(struct esm_softc *ess, struct esm_chinfo *ch) 1112 1.18 fredette { 1113 1.18 fredette size_t offset, resid, count; 1114 1.30 kent uint32_t *dst32s; 1115 1.30 kent const uint32_t *left32s, *right32s; 1116 1.30 kent uint32_t left32, right32; 1117 1.18 fredette 1118 1.18 fredette /* The current offset into the upper layer buffer. */ 1119 1.18 fredette offset = ch->offset; 1120 1.18 fredette 1121 1.18 fredette /* The number of bytes left to combine. */ 1122 1.18 fredette resid = ch->blocksize; 1123 1.18 fredette 1124 1.18 fredette while (resid > 0) { 1125 1.18 fredette 1126 1.18 fredette /* The 32-bit words for the left channel. */ 1127 1.42 christos left32s = (const uint32_t *)((char *)ess->sc_dma.addr + 1128 1.18 fredette MAESTRO_RECBUF_L_OFF + offset / 2); 1129 1.18 fredette 1130 1.18 fredette /* The 32-bit words for the right channel. */ 1131 1.42 christos right32s = (const uint32_t *)((char *)ess->sc_dma.addr + 1132 1.18 fredette MAESTRO_RECBUF_R_OFF + offset / 2); 1133 1.18 fredette 1134 1.18 fredette /* The pointer to the 32-bit words we will write. */ 1135 1.42 christos dst32s = (uint32_t *)((char *)ch->buffer + offset); 1136 1.18 fredette 1137 1.18 fredette /* Get the number of bytes we will combine now. */ 1138 1.18 fredette count = ch->bufsize - offset; 1139 1.18 fredette if (count > resid) 1140 1.18 fredette count = resid; 1141 1.18 fredette resid -= count; 1142 1.18 fredette offset += count; 1143 1.18 fredette if (offset == ch->bufsize) 1144 1.18 fredette offset = 0; 1145 1.18 fredette 1146 1.18 fredette /* Combine, writing two 32-bit words at a time. */ 1147 1.18 fredette KASSERT((count & (sizeof(uint32_t) * 2 - 1)) == 0); 1148 1.30 kent count /= (sizeof(uint32_t) * 2); 1149 1.18 fredette while (count > 0) { 1150 1.18 fredette left32 = *(left32s++); 1151 1.18 fredette right32 = *(right32s++); 1152 1.18 fredette /* XXX this endian handling is half-baked at best */ 1153 1.18 fredette #if BYTE_ORDER == LITTLE_ENDIAN 1154 1.18 fredette *(dst32s++) = (left32 & 0xFFFF) | (right32 << 16); 1155 1.18 fredette *(dst32s++) = (left32 >> 16) | (right32 & 0xFFFF0000); 1156 1.18 fredette #else /* BYTE_ORDER == BIG_ENDIAN */ 1157 1.18 fredette *(dst32s++) = (left32 & 0xFFFF0000) | (right32 >> 16); 1158 1.18 fredette *(dst32s++) = (left32 << 16) | (right32 & 0xFFFF); 1159 1.18 fredette #endif /* BYTE_ORDER == BIG_ENDIAN */ 1160 1.18 fredette count--; 1161 1.18 fredette } 1162 1.18 fredette } 1163 1.18 fredette 1164 1.18 fredette /* Update the offset. */ 1165 1.18 fredette ch->offset = offset; 1166 1.18 fredette } 1167 1.1 rh 1168 1.1 rh /* 1169 1.1 rh * Audio interface glue functions 1170 1.1 rh */ 1171 1.1 rh 1172 1.1 rh int 1173 1.41 christos esm_getdev (void *sc, struct audio_device *adp) 1174 1.1 rh { 1175 1.30 kent 1176 1.1 rh *adp = esm_device; 1177 1.1 rh return 0; 1178 1.1 rh } 1179 1.1 rh 1180 1.1 rh int 1181 1.41 christos esm_round_blocksize(void *sc, int blk, int mode, 1182 1.41 christos const audio_params_t *param) 1183 1.1 rh { 1184 1.30 kent 1185 1.1 rh DPRINTF(ESM_DEBUG_PARAM, 1186 1.1 rh ("esm_round_blocksize(%p, 0x%x)", sc, blk)); 1187 1.1 rh 1188 1.1 rh blk &= ~0x3f; /* keep good alignment */ 1189 1.65 isaki if (blk < 0x40) 1190 1.65 isaki blk = 0x40; 1191 1.1 rh 1192 1.1 rh DPRINTF(ESM_DEBUG_PARAM, (" = 0x%x\n", blk)); 1193 1.1 rh 1194 1.1 rh return blk; 1195 1.1 rh } 1196 1.1 rh 1197 1.1 rh int 1198 1.62 isaki esm_query_format(void *sc, audio_format_query_t *afp) 1199 1.1 rh { 1200 1.30 kent 1201 1.62 isaki return audio_query_format(esm_formats, ESM_NFORMATS, afp); 1202 1.1 rh } 1203 1.1 rh 1204 1.1 rh int 1205 1.62 isaki esm_set_format(void *sc, int setmode, 1206 1.62 isaki const audio_params_t *play, const audio_params_t *rec, 1207 1.62 isaki audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 1208 1.1 rh { 1209 1.30 kent struct esm_softc *ess; 1210 1.1 rh 1211 1.1 rh DPRINTF(ESM_DEBUG_PARAM, 1212 1.62 isaki ("%s(%p, 0x%x, %p, %p)\n", __func__, 1213 1.62 isaki sc, setmode, play, rec)); 1214 1.30 kent ess = sc; 1215 1.1 rh 1216 1.62 isaki if ((setmode & AUMODE_PLAY)) 1217 1.62 isaki esmch_set_format(&ess->pch, play); 1218 1.62 isaki if ((setmode & AUMODE_RECORD)) 1219 1.62 isaki esmch_set_format(&ess->rch, rec); 1220 1.1 rh 1221 1.1 rh return 0; 1222 1.1 rh } 1223 1.1 rh 1224 1.1 rh int 1225 1.1 rh esm_set_port(void *sc, mixer_ctrl_t *cp) 1226 1.1 rh { 1227 1.30 kent struct esm_softc *ess; 1228 1.1 rh 1229 1.30 kent ess = sc; 1230 1.30 kent return ess->codec_if->vtbl->mixer_set_port(ess->codec_if, cp); 1231 1.1 rh } 1232 1.1 rh 1233 1.1 rh int 1234 1.1 rh esm_get_port(void *sc, mixer_ctrl_t *cp) 1235 1.1 rh { 1236 1.30 kent struct esm_softc *ess; 1237 1.1 rh 1238 1.30 kent ess = sc; 1239 1.30 kent return ess->codec_if->vtbl->mixer_get_port(ess->codec_if, cp); 1240 1.1 rh } 1241 1.1 rh 1242 1.1 rh int 1243 1.1 rh esm_query_devinfo(void *sc, mixer_devinfo_t *dip) 1244 1.1 rh { 1245 1.30 kent struct esm_softc *ess; 1246 1.1 rh 1247 1.30 kent ess = sc; 1248 1.30 kent return ess->codec_if->vtbl->query_devinfo(ess->codec_if, dip); 1249 1.1 rh } 1250 1.1 rh 1251 1.1 rh void * 1252 1.54 jmcneill esm_malloc(void *sc, int direction, size_t size) 1253 1.1 rh { 1254 1.30 kent struct esm_softc *ess; 1255 1.18 fredette int off; 1256 1.1 rh 1257 1.1 rh DPRINTF(ESM_DEBUG_DMA, 1258 1.54 jmcneill ("esm_malloc(%p, %d, 0x%zd)", sc, direction, size)); 1259 1.30 kent ess = sc; 1260 1.18 fredette /* 1261 1.18 fredette * Each buffer can only be allocated once. 1262 1.18 fredette */ 1263 1.18 fredette if (ess->rings_alloced & direction) { 1264 1.1 rh DPRINTF(ESM_DEBUG_DMA, (" = 0 (ENOMEM)\n")); 1265 1.1 rh return 0; 1266 1.1 rh } 1267 1.1 rh 1268 1.18 fredette /* 1269 1.18 fredette * Mark this buffer as allocated and return its 1270 1.18 fredette * kernel virtual address. 1271 1.18 fredette */ 1272 1.18 fredette ess->rings_alloced |= direction; 1273 1.18 fredette off = (direction == AUMODE_PLAY ? 1274 1.18 fredette MAESTRO_PLAYBUF_OFF : MAESTRO_RECBUF_OFF); 1275 1.18 fredette DPRINTF(ESM_DEBUG_DMA, (" = %p (DMAADDR 0x%x)\n", 1276 1.42 christos (char *)ess->sc_dma.addr + off, 1277 1.18 fredette (int)DMAADDR(&ess->sc_dma) + off)); 1278 1.42 christos return (char *)ess->sc_dma.addr + off; 1279 1.1 rh } 1280 1.1 rh 1281 1.1 rh void 1282 1.54 jmcneill esm_free(void *sc, void *ptr, size_t size) 1283 1.1 rh { 1284 1.30 kent struct esm_softc *ess; 1285 1.1 rh 1286 1.54 jmcneill DPRINTF(ESM_DEBUG_DMA, ("esm_free(%p, %p, %zd)\n", sc, ptr, size)); 1287 1.30 kent ess = sc; 1288 1.42 christos if ((char *)ptr == (char *)ess->sc_dma.addr + MAESTRO_PLAYBUF_OFF) 1289 1.18 fredette ess->rings_alloced &= ~AUMODE_PLAY; 1290 1.42 christos else if ((char *)ptr == (char *)ess->sc_dma.addr + MAESTRO_RECBUF_OFF) 1291 1.18 fredette ess->rings_alloced &= ~AUMODE_RECORD; 1292 1.1 rh } 1293 1.1 rh 1294 1.1 rh size_t 1295 1.41 christos esm_round_buffersize(void *sc, int direction, size_t size) 1296 1.1 rh { 1297 1.30 kent 1298 1.18 fredette if (size > MAESTRO_PLAYBUF_SZ) 1299 1.18 fredette size = MAESTRO_PLAYBUF_SZ; 1300 1.18 fredette if (size > MAESTRO_RECBUF_SZ) 1301 1.18 fredette size = MAESTRO_RECBUF_SZ; 1302 1.1 rh return size; 1303 1.1 rh } 1304 1.1 rh 1305 1.1 rh int 1306 1.41 christos esm_get_props(void *sc) 1307 1.1 rh { 1308 1.30 kent 1309 1.63 isaki return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 1310 1.63 isaki AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX; 1311 1.1 rh } 1312 1.1 rh 1313 1.1 rh 1314 1.1 rh /* ----------------------------- 1315 1.1 rh * Bus space. 1316 1.1 rh */ 1317 1.1 rh 1318 1.45 dyoung static int 1319 1.1 rh esm_intr(void *sc) 1320 1.1 rh { 1321 1.30 kent struct esm_softc *ess; 1322 1.30 kent uint16_t status; 1323 1.30 kent uint16_t pos; 1324 1.1 rh 1325 1.30 kent ess = sc; 1326 1.54 jmcneill 1327 1.1 rh status = bus_space_read_1(ess->st, ess->sh, PORT_HOSTINT_STAT); 1328 1.67 mlelstv if (!status) 1329 1.1 rh return 0; 1330 1.1 rh 1331 1.67 mlelstv mutex_spin_enter(&ess->sc_intr_lock); 1332 1.1 rh /* Acknowledge all. */ 1333 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1); 1334 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HOSTINT_STAT, 0); 1335 1.1 rh #if 0 /* XXX - HWVOL */ 1336 1.1 rh if (status & HOSTINT_STAT_HWVOL) { 1337 1.1 rh u_int delta; 1338 1.1 rh delta = bus_space_read_1(ess->st, ess->sh, PORT_HWVOL_MASTER) 1339 1.1 rh - 0x88; 1340 1.1 rh if (delta & 0x11) 1341 1.1 rh mixer_set(device_get_softc(ess->dev), 1342 1.1 rh SOUND_MIXER_VOLUME, 0); 1343 1.1 rh else { 1344 1.1 rh mixer_set(device_get_softc(ess->dev), 1345 1.1 rh SOUND_MIXER_VOLUME, 1346 1.1 rh mixer_get(device_get_softc(ess->dev), 1347 1.1 rh SOUND_MIXER_VOLUME) 1348 1.1 rh + ((delta >> 5) & 0x7) - 4 1349 1.1 rh + ((delta << 7) & 0x700) - 0x400); 1350 1.1 rh } 1351 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HWVOL_MASTER, 0x88); 1352 1.1 rh } 1353 1.1 rh #endif /* XXX - HWVOL */ 1354 1.1 rh 1355 1.1 rh if (ess->pactive) { 1356 1.1 rh pos = wp_rdapu(ess, ess->pch.num << 1, APUREG_CURPTR); 1357 1.1 rh 1358 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos, 1359 1.1 rh wp_rdapu(ess, (ess->pch.num<<1)+1, APUREG_CURPTR))); 1360 1.1 rh 1361 1.18 fredette pos -= ess->pch.apubase; 1362 1.1 rh if (pos >= ess->pch.nextirq && 1363 1.1 rh pos - ess->pch.nextirq < ess->pch.apubuf / 2) { 1364 1.1 rh ess->pch.nextirq += ess->pch.apublk; 1365 1.1 rh 1366 1.1 rh if (ess->pch.nextirq >= ess->pch.apubuf) 1367 1.1 rh ess->pch.nextirq = 0; 1368 1.1 rh 1369 1.1 rh if (ess->sc_pintr) { 1370 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("P\n")); 1371 1.1 rh ess->sc_pintr(ess->sc_parg); 1372 1.1 rh } 1373 1.1 rh 1374 1.1 rh } 1375 1.1 rh } 1376 1.1 rh 1377 1.1 rh if (ess->ractive) { 1378 1.1 rh pos = wp_rdapu(ess, ess->rch.num << 1, APUREG_CURPTR); 1379 1.1 rh 1380 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos, 1381 1.1 rh wp_rdapu(ess, (ess->rch.num<<1)+1, APUREG_CURPTR))); 1382 1.1 rh 1383 1.18 fredette pos -= ess->rch.apubase; 1384 1.1 rh if (pos >= ess->rch.nextirq && 1385 1.1 rh pos - ess->rch.nextirq < ess->rch.apubuf / 2) { 1386 1.1 rh ess->rch.nextirq += ess->rch.apublk; 1387 1.1 rh 1388 1.1 rh if (ess->rch.nextirq >= ess->rch.apubuf) 1389 1.1 rh ess->rch.nextirq = 0; 1390 1.1 rh 1391 1.1 rh if (ess->sc_rintr) { 1392 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("R\n")); 1393 1.18 fredette switch(ess->rch.aputype) { 1394 1.18 fredette case APUTYPE_16BITSTEREO: 1395 1.18 fredette esmch_combine_input(ess, &ess->rch); 1396 1.18 fredette break; 1397 1.18 fredette } 1398 1.18 fredette ess->sc_rintr(ess->sc_rarg); 1399 1.1 rh } 1400 1.1 rh 1401 1.1 rh } 1402 1.1 rh } 1403 1.54 jmcneill mutex_spin_exit(&ess->sc_intr_lock); 1404 1.1 rh 1405 1.67 mlelstv return 1; 1406 1.1 rh } 1407 1.1 rh 1408 1.45 dyoung static void 1409 1.45 dyoung esm_freemem(struct esm_softc *sc, struct esm_dma *p) 1410 1.45 dyoung { 1411 1.45 dyoung if (p->size == 0) 1412 1.45 dyoung return; 1413 1.45 dyoung 1414 1.66 rin bus_dmamap_unload(sc->dmat, p->map); 1415 1.66 rin 1416 1.66 rin bus_dmamap_destroy(sc->dmat, p->map); 1417 1.45 dyoung 1418 1.45 dyoung bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1419 1.45 dyoung 1420 1.66 rin bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1421 1.45 dyoung 1422 1.45 dyoung p->size = 0; 1423 1.45 dyoung } 1424 1.45 dyoung 1425 1.45 dyoung static int 1426 1.1 rh esm_allocmem(struct esm_softc *sc, size_t size, size_t align, 1427 1.1 rh struct esm_dma *p) 1428 1.1 rh { 1429 1.1 rh int error; 1430 1.1 rh 1431 1.1 rh p->size = size; 1432 1.1 rh error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, 1433 1.50 cegger p->segs, __arraycount(p->segs), 1434 1.54 jmcneill &p->nsegs, BUS_DMA_WAITOK); 1435 1.1 rh if (error) 1436 1.1 rh return error; 1437 1.1 rh 1438 1.1 rh error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size, 1439 1.54 jmcneill &p->addr, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1440 1.1 rh if (error) 1441 1.1 rh goto free; 1442 1.1 rh 1443 1.1 rh error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 1444 1.54 jmcneill 0, BUS_DMA_WAITOK, &p->map); 1445 1.1 rh if (error) 1446 1.1 rh goto unmap; 1447 1.1 rh 1448 1.1 rh error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL, 1449 1.54 jmcneill BUS_DMA_WAITOK); 1450 1.1 rh if (error) 1451 1.1 rh goto destroy; 1452 1.1 rh 1453 1.1 rh return 0; 1454 1.1 rh 1455 1.1 rh destroy: 1456 1.1 rh bus_dmamap_destroy(sc->dmat, p->map); 1457 1.1 rh unmap: 1458 1.1 rh bus_dmamem_unmap(sc->dmat, p->addr, p->size); 1459 1.1 rh free: 1460 1.1 rh bus_dmamem_free(sc->dmat, p->segs, p->nsegs); 1461 1.1 rh 1462 1.45 dyoung p->size = 0; 1463 1.1 rh return error; 1464 1.1 rh } 1465 1.1 rh 1466 1.45 dyoung static int 1467 1.48 cegger esm_match(device_t dev, cfdata_t match, void *aux) 1468 1.1 rh { 1469 1.30 kent struct pci_attach_args *pa; 1470 1.1 rh 1471 1.30 kent pa = (struct pci_attach_args *)aux; 1472 1.1 rh switch (PCI_VENDOR(pa->pa_id)) { 1473 1.1 rh case PCI_VENDOR_ESSTECH: 1474 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) { 1475 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO1: 1476 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2: 1477 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2E: 1478 1.1 rh return 1; 1479 1.1 rh } 1480 1.64 mrg break; 1481 1.1 rh 1482 1.1 rh case PCI_VENDOR_ESSTECH2: 1483 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) { 1484 1.1 rh case PCI_PRODUCT_ESSTECH2_MAESTRO1: 1485 1.1 rh return 1; 1486 1.1 rh } 1487 1.1 rh } 1488 1.1 rh return 0; 1489 1.1 rh } 1490 1.1 rh 1491 1.45 dyoung static void 1492 1.45 dyoung esm_attach(device_t parent, device_t self, void *aux) 1493 1.1 rh { 1494 1.30 kent struct esm_softc *ess; 1495 1.30 kent struct pci_attach_args *pa; 1496 1.30 kent const char *intrstr; 1497 1.30 kent pci_chipset_tag_t pc; 1498 1.30 kent pcitag_t tag; 1499 1.1 rh pci_intr_handle_t ih; 1500 1.1 rh pcireg_t csr, data; 1501 1.30 kent uint16_t codec_data; 1502 1.30 kent uint16_t pcmbar; 1503 1.35 christos int error; 1504 1.58 christos char intrbuf[PCI_INTRSTR_LEN]; 1505 1.1 rh 1506 1.45 dyoung ess = device_private(self); 1507 1.49 cegger ess->sc_dev = self; 1508 1.30 kent pa = (struct pci_attach_args *)aux; 1509 1.30 kent pc = pa->pa_pc; 1510 1.30 kent tag = pa->pa_tag; 1511 1.20 thorpej 1512 1.56 drochner pci_aprint_devinfo(pa, "Audio controller"); 1513 1.1 rh 1514 1.54 jmcneill mutex_init(&ess->sc_lock, MUTEX_DEFAULT, IPL_NONE); 1515 1.55 mrg mutex_init(&ess->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO); 1516 1.54 jmcneill 1517 1.1 rh /* Enable the device. */ 1518 1.1 rh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 1519 1.1 rh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 1520 1.1 rh csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE); 1521 1.1 rh 1522 1.1 rh /* Map I/O register */ 1523 1.1 rh if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0, 1524 1.45 dyoung &ess->st, &ess->sh, NULL, &ess->sz)) { 1525 1.49 cegger aprint_error_dev(ess->sc_dev, "can't map i/o space\n"); 1526 1.54 jmcneill mutex_destroy(&ess->sc_lock); 1527 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock); 1528 1.1 rh return; 1529 1.1 rh } 1530 1.1 rh 1531 1.1 rh /* Initialize softc */ 1532 1.1 rh ess->pch.num = 0; 1533 1.18 fredette ess->rch.num = 1; 1534 1.1 rh ess->dmat = pa->pa_dmat; 1535 1.1 rh ess->tag = tag; 1536 1.1 rh ess->pc = pc; 1537 1.1 rh ess->subid = pci_conf_read(pc, tag, PCI_SUBSYS_ID_REG); 1538 1.1 rh 1539 1.3 rh DPRINTF(ESM_DEBUG_PCI, 1540 1.3 rh ("%s: sub-system vendor 0x%4.4x, product 0x%4.4x\n", 1541 1.49 cegger device_xname(ess->sc_dev), 1542 1.3 rh PCI_VENDOR(ess->subid), PCI_PRODUCT(ess->subid))); 1543 1.3 rh 1544 1.1 rh /* Map and establish the interrupt. */ 1545 1.1 rh if (pci_intr_map(pa, &ih)) { 1546 1.49 cegger aprint_error_dev(ess->sc_dev, "can't map interrupt\n"); 1547 1.54 jmcneill mutex_destroy(&ess->sc_lock); 1548 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock); 1549 1.1 rh return; 1550 1.1 rh } 1551 1.58 christos intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1552 1.67 mlelstv ess->ih = pci_intr_establish_xname(pc, ih, IPL_AUDIO, esm_intr, ess, 1553 1.60 jdolecek device_xname(self)); 1554 1.1 rh if (ess->ih == NULL) { 1555 1.49 cegger aprint_error_dev(ess->sc_dev, "can't establish interrupt"); 1556 1.1 rh if (intrstr != NULL) 1557 1.51 njoly aprint_error(" at %s", intrstr); 1558 1.51 njoly aprint_error("\n"); 1559 1.54 jmcneill mutex_destroy(&ess->sc_lock); 1560 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock); 1561 1.1 rh return; 1562 1.1 rh } 1563 1.59 msaitoh aprint_normal_dev(ess->sc_dev, "interrupting at %s\n", intrstr); 1564 1.1 rh 1565 1.1 rh /* 1566 1.1 rh * Setup PCI config registers 1567 1.1 rh */ 1568 1.1 rh 1569 1.35 christos /* power up chip */ 1570 1.46 dyoung if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1571 1.35 christos pci_activate_null)) && error != EOPNOTSUPP) { 1572 1.59 msaitoh aprint_error_dev(ess->sc_dev, "cannot activate %d\n", error); 1573 1.54 jmcneill mutex_destroy(&ess->sc_lock); 1574 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock); 1575 1.35 christos return; 1576 1.35 christos } 1577 1.1 rh delay(100000); 1578 1.1 rh 1579 1.1 rh /* Disable all legacy emulations. */ 1580 1.1 rh data = pci_conf_read(pc, tag, CONF_LEGACY); 1581 1.1 rh pci_conf_write(pc, tag, CONF_LEGACY, data | LEGACY_DISABLED); 1582 1.1 rh 1583 1.1 rh /* Disconnect from CHI. (Makes Dell inspiron 7500 work?) 1584 1.1 rh * Enable posted write. 1585 1.1 rh * Prefer PCI timing rather than that of ISA. 1586 1.1 rh * Don't swap L/R. */ 1587 1.1 rh data = pci_conf_read(pc, tag, CONF_MAESTRO); 1588 1.1 rh data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING; 1589 1.1 rh data &= ~MAESTRO_SWAP_LR; 1590 1.1 rh pci_conf_write(pc, tag, CONF_MAESTRO, data); 1591 1.1 rh 1592 1.1 rh /* initialize sound chip */ 1593 1.1 rh esm_init(ess); 1594 1.1 rh 1595 1.1 rh esm_read_codec(ess, 0, &codec_data); 1596 1.1 rh if (codec_data == 0x80) { 1597 1.49 cegger aprint_error_dev(ess->sc_dev, "PT101 codec detected!\n"); 1598 1.54 jmcneill mutex_destroy(&ess->sc_lock); 1599 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock); 1600 1.1 rh return; 1601 1.1 rh } 1602 1.1 rh 1603 1.3 rh /* 1604 1.3 rh * Some cards and Notebooks appear to have left and right channels 1605 1.3 rh * reversed. Check if there is a corresponding quirk entry for 1606 1.3 rh * the subsystem vendor and product and if so, set the appropriate 1607 1.3 rh * codec flag. 1608 1.3 rh */ 1609 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_SWAPPEDCH) { 1610 1.3 rh ess->codec_flags |= AC97_HOST_SWAPPED_CHANNELS; 1611 1.3 rh } 1612 1.5 rh ess->codec_flags |= AC97_HOST_DONT_READ; 1613 1.3 rh 1614 1.1 rh /* initialize AC97 host interface */ 1615 1.67 mlelstv ess->host_if.arg = ess; 1616 1.1 rh ess->host_if.attach = esm_attach_codec; 1617 1.1 rh ess->host_if.read = esm_read_codec; 1618 1.1 rh ess->host_if.write = esm_write_codec; 1619 1.1 rh ess->host_if.reset = esm_reset_codec; 1620 1.3 rh ess->host_if.flags = esm_flags_codec; 1621 1.1 rh 1622 1.54 jmcneill if (ac97_attach(&ess->host_if, self, &ess->sc_lock) != 0) { 1623 1.54 jmcneill mutex_destroy(&ess->sc_lock); 1624 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock); 1625 1.1 rh return; 1626 1.54 jmcneill } 1627 1.18 fredette 1628 1.18 fredette /* allocate our DMA region */ 1629 1.18 fredette if (esm_allocmem(ess, MAESTRO_DMA_SZ, MAESTRO_DMA_ALIGN, 1630 1.18 fredette &ess->sc_dma)) { 1631 1.49 cegger aprint_error_dev(ess->sc_dev, "couldn't allocate memory!\n"); 1632 1.54 jmcneill mutex_destroy(&ess->sc_lock); 1633 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock); 1634 1.18 fredette return; 1635 1.18 fredette } 1636 1.18 fredette ess->rings_alloced = 0; 1637 1.18 fredette 1638 1.18 fredette /* set DMA base address */ 1639 1.18 fredette for (pcmbar = WAVCACHE_PCMBAR; pcmbar < WAVCACHE_PCMBAR + 4; pcmbar++) 1640 1.18 fredette wc_wrreg(ess, pcmbar, 1641 1.18 fredette DMAADDR(&ess->sc_dma) >> WAVCACHE_BASEADDR_SHIFT); 1642 1.1 rh 1643 1.67 mlelstv audio_attach_mi(&esm_hw_if, ess, ess->sc_dev); 1644 1.7 ichiro 1645 1.44 jmcneill if (!pmf_device_register(self, esm_suspend, esm_resume)) 1646 1.44 jmcneill aprint_error_dev(self, "couldn't establish power handler\n"); 1647 1.7 ichiro } 1648 1.7 ichiro 1649 1.45 dyoung static void 1650 1.45 dyoung esm_childdet(device_t self, device_t child) 1651 1.45 dyoung { 1652 1.45 dyoung /* we hold no child references, so do nothing */ 1653 1.45 dyoung } 1654 1.45 dyoung 1655 1.45 dyoung static int 1656 1.45 dyoung esm_detach(device_t self, int flags) 1657 1.45 dyoung { 1658 1.45 dyoung int rc; 1659 1.45 dyoung struct esm_softc *ess = device_private(self); 1660 1.45 dyoung 1661 1.45 dyoung if ((rc = config_detach_children(self, flags)) != 0) 1662 1.45 dyoung return rc; 1663 1.54 jmcneill pmf_device_deregister(self); 1664 1.45 dyoung 1665 1.45 dyoung /* free our DMA region */ 1666 1.45 dyoung esm_freemem(ess, &ess->sc_dma); 1667 1.45 dyoung 1668 1.54 jmcneill if (ess->codec_if != NULL) { 1669 1.54 jmcneill mutex_enter(&ess->sc_lock); 1670 1.45 dyoung ess->codec_if->vtbl->detach(ess->codec_if); 1671 1.54 jmcneill mutex_exit(&ess->sc_lock); 1672 1.54 jmcneill } 1673 1.45 dyoung 1674 1.45 dyoung /* XXX Restore CONF_MAESTRO? */ 1675 1.45 dyoung /* XXX Restore legacy emulations? */ 1676 1.45 dyoung /* XXX Restore PCI config registers? */ 1677 1.45 dyoung 1678 1.45 dyoung if (ess->ih != NULL) 1679 1.45 dyoung pci_intr_disestablish(ess->pc, ess->ih); 1680 1.45 dyoung 1681 1.45 dyoung bus_space_unmap(ess->st, ess->sh, ess->sz); 1682 1.54 jmcneill mutex_destroy(&ess->sc_lock); 1683 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock); 1684 1.45 dyoung 1685 1.45 dyoung return 0; 1686 1.45 dyoung } 1687 1.45 dyoung 1688 1.44 jmcneill static bool 1689 1.53 dyoung esm_suspend(device_t dv, const pmf_qual_t *qual) 1690 1.1 rh { 1691 1.44 jmcneill struct esm_softc *ess = device_private(dv); 1692 1.1 rh 1693 1.54 jmcneill mutex_enter(&ess->sc_lock); 1694 1.54 jmcneill mutex_spin_enter(&ess->sc_intr_lock); 1695 1.1 rh wp_stoptimer(ess); 1696 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0); 1697 1.1 rh esm_halt_output(ess); 1698 1.1 rh esm_halt_input(ess); 1699 1.54 jmcneill mutex_spin_exit(&ess->sc_intr_lock); 1700 1.1 rh 1701 1.1 rh /* Power down everything except clock. */ 1702 1.1 rh esm_write_codec(ess, AC97_REG_POWER, 0xdf00); 1703 1.1 rh delay(20); 1704 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0); 1705 1.1 rh delay(1); 1706 1.54 jmcneill mutex_exit(&ess->sc_lock); 1707 1.1 rh 1708 1.44 jmcneill return true; 1709 1.1 rh } 1710 1.1 rh 1711 1.44 jmcneill static bool 1712 1.53 dyoung esm_resume(device_t dv, const pmf_qual_t *qual) 1713 1.1 rh { 1714 1.44 jmcneill struct esm_softc *ess = device_private(dv); 1715 1.38 jmcneill uint16_t pcmbar; 1716 1.1 rh 1717 1.1 rh delay(100000); 1718 1.54 jmcneill 1719 1.54 jmcneill mutex_enter(&ess->sc_lock); 1720 1.54 jmcneill mutex_spin_enter(&ess->sc_intr_lock); 1721 1.1 rh esm_init(ess); 1722 1.8 ichiro 1723 1.38 jmcneill /* set DMA base address */ 1724 1.38 jmcneill for (pcmbar = WAVCACHE_PCMBAR; pcmbar < WAVCACHE_PCMBAR + 4; pcmbar++) 1725 1.38 jmcneill wc_wrreg(ess, pcmbar, 1726 1.38 jmcneill DMAADDR(&ess->sc_dma) >> WAVCACHE_BASEADDR_SHIFT); 1727 1.54 jmcneill mutex_spin_exit(&ess->sc_intr_lock); 1728 1.30 kent ess->codec_if->vtbl->restore_ports(ess->codec_if); 1729 1.54 jmcneill mutex_spin_enter(&ess->sc_intr_lock); 1730 1.8 ichiro #if 0 1731 1.1 rh if (mixer_reinit(dev)) { 1732 1.1 rh printf("%s: unable to reinitialize the mixer\n", 1733 1.49 cegger device_xname(ess->sc_dev)); 1734 1.1 rh return ENXIO; 1735 1.1 rh } 1736 1.8 ichiro #endif 1737 1.1 rh 1738 1.8 ichiro #if TODO 1739 1.1 rh if (ess->pactive) 1740 1.1 rh esm_start_output(ess); 1741 1.1 rh if (ess->ractive) 1742 1.1 rh esm_start_input(ess); 1743 1.30 kent #endif 1744 1.1 rh if (ess->pactive || ess->ractive) { 1745 1.1 rh set_timer(ess); 1746 1.1 rh wp_starttimer(ess); 1747 1.1 rh } 1748 1.54 jmcneill mutex_spin_exit(&ess->sc_intr_lock); 1749 1.54 jmcneill mutex_exit(&ess->sc_lock); 1750 1.1 rh 1751 1.44 jmcneill return true; 1752 1.1 rh } 1753 1.54 jmcneill 1754 1.54 jmcneill void 1755 1.54 jmcneill esm_get_locks(void *addr, kmutex_t **intr, kmutex_t **proc) 1756 1.54 jmcneill { 1757 1.54 jmcneill struct esm_softc *esm; 1758 1.54 jmcneill 1759 1.54 jmcneill esm = addr; 1760 1.54 jmcneill *intr = &esm->sc_intr_lock; 1761 1.54 jmcneill *proc = &esm->sc_lock; 1762 1.54 jmcneill } 1763