esm.c revision 1.11 1 1.11 augustss /* $NetBSD: esm.c,v 1.11 2001/10/03 00:04:52 augustss Exp $ */
2 1.1 rh
3 1.1 rh /*-
4 1.1 rh * Copyright (c) 2000, 2001 Rene Hexel <rh (at) netbsd.org>
5 1.1 rh * All rights reserved.
6 1.1 rh *
7 1.1 rh * Copyright (c) 2000 Taku YAMAMOTO <taku (at) cent.saitama-u.ac.jp>
8 1.1 rh * All rights reserved.
9 1.1 rh *
10 1.1 rh * Redistribution and use in source and binary forms, with or without
11 1.1 rh * modification, are permitted provided that the following conditions
12 1.1 rh * are met:
13 1.1 rh * 1. Redistributions of source code must retain the above copyright
14 1.1 rh * notice, this list of conditions and the following disclaimer.
15 1.1 rh * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 rh * notice, this list of conditions and the following disclaimer in the
17 1.1 rh * documentation and/or other materials provided with the distribution.
18 1.1 rh *
19 1.1 rh * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 1.1 rh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 1.1 rh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 1.1 rh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 1.1 rh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 1.1 rh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 1.1 rh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 1.1 rh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 1.1 rh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 1.1 rh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 1.1 rh * SUCH DAMAGE.
30 1.1 rh *
31 1.1 rh * Taku Id: maestro.c,v 1.12 2000/09/06 03:32:34 taku Exp
32 1.1 rh * FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.4 2000/12/18 01:36:35 cg Exp
33 1.1 rh */
34 1.1 rh
35 1.1 rh /*
36 1.1 rh * TODO:
37 1.1 rh * - hardware volume support
38 1.1 rh * - recording
39 1.1 rh * - MIDI support
40 1.1 rh * - joystick support
41 1.1 rh *
42 1.1 rh *
43 1.1 rh * Credits:
44 1.1 rh *
45 1.1 rh * This code is based on the FreeBSD driver written by Taku YAMAMOTO
46 1.1 rh *
47 1.1 rh *
48 1.1 rh * Original credits from the FreeBSD driver:
49 1.1 rh *
50 1.1 rh * Part of this code (especially in many magic numbers) was heavily inspired
51 1.1 rh * by the Linux driver originally written by
52 1.1 rh * Alan Cox <alan.cox (at) linux.org>, modified heavily by
53 1.1 rh * Zach Brown <zab (at) zabbo.net>.
54 1.1 rh *
55 1.1 rh * busdma()-ize and buffer size reduction were suggested by
56 1.1 rh * Cameron Grant <gandalf (at) vilnya.demon.co.uk>.
57 1.1 rh * Also he showed me the way to use busdma() suite.
58 1.1 rh *
59 1.1 rh * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
60 1.1 rh * were looked at by
61 1.1 rh * Munehiro Matsuda <haro (at) tk.kubota.co.jp>,
62 1.1 rh * who brought patches based on the Linux driver with some simplification.
63 1.1 rh */
64 1.1 rh
65 1.1 rh #include <sys/param.h>
66 1.1 rh #include <sys/systm.h>
67 1.1 rh #include <sys/kernel.h>
68 1.1 rh #include <sys/malloc.h>
69 1.1 rh #include <sys/device.h>
70 1.1 rh
71 1.1 rh #include <machine/bus.h>
72 1.1 rh
73 1.1 rh #include <sys/audioio.h>
74 1.1 rh #include <dev/audio_if.h>
75 1.1 rh #include <dev/mulaw.h>
76 1.1 rh #include <dev/auconv.h>
77 1.1 rh #include <dev/ic/ac97var.h>
78 1.8 ichiro #include <dev/ic/ac97reg.h>
79 1.1 rh
80 1.1 rh #include <dev/pci/pcidevs.h>
81 1.1 rh #include <dev/pci/pcivar.h>
82 1.1 rh
83 1.1 rh #include <dev/pci/esmreg.h>
84 1.1 rh #include <dev/pci/esmvar.h>
85 1.1 rh
86 1.1 rh #define PCI_CBIO 0x10 /* Configuration Base I/O Address */
87 1.1 rh
88 1.1 rh /* Debug */
89 1.1 rh #ifdef AUDIO_DEBUG
90 1.1 rh #define DPRINTF(l,x) do { if (esm_debug & (l)) printf x; } while(0)
91 1.1 rh #define DUMPREG(x) do { if (esm_debug & ESM_DEBUG_REG) \
92 1.1 rh esm_dump_regs(x); } while(0)
93 1.1 rh int esm_debug = 0xfffc;
94 1.1 rh #define ESM_DEBUG_CODECIO 0x0001
95 1.1 rh #define ESM_DEBUG_IRQ 0x0002
96 1.1 rh #define ESM_DEBUG_DMA 0x0004
97 1.1 rh #define ESM_DEBUG_TIMER 0x0008
98 1.1 rh #define ESM_DEBUG_REG 0x0010
99 1.1 rh #define ESM_DEBUG_PARAM 0x0020
100 1.1 rh #define ESM_DEBUG_APU 0x0040
101 1.1 rh #define ESM_DEBUG_CODEC 0x0080
102 1.3 rh #define ESM_DEBUG_PCI 0x0100
103 1.8 ichiro #define ESM_DEBUG_RESUME 0x0200
104 1.1 rh #else
105 1.1 rh #define DPRINTF(x,y) /* nothing */
106 1.1 rh #define DUMPREG(x) /* nothing */
107 1.1 rh #endif
108 1.1 rh
109 1.1 rh #ifdef DIAGNOSTIC
110 1.1 rh #define RANGE(n, l, h) if ((n) < (l) || (n) >= (h)) \
111 1.1 rh printf (#n "=%d out of range (%d, %d) in " \
112 1.1 rh __FILE__ ", line %d\n", (n), (l), (h), __LINE__)
113 1.1 rh #else
114 1.1 rh #define RANGE(x,y,z) /* nothing */
115 1.1 rh #endif
116 1.1 rh
117 1.1 rh #define inline __inline
118 1.1 rh
119 1.1 rh static inline void ringbus_setdest(struct esm_softc *, int, int);
120 1.1 rh
121 1.1 rh static inline u_int16_t wp_rdreg(struct esm_softc *, u_int16_t);
122 1.1 rh static inline void wp_wrreg(struct esm_softc *, u_int16_t, u_int16_t);
123 1.1 rh static inline u_int16_t wp_rdapu(struct esm_softc *, int, u_int16_t);
124 1.1 rh static inline void wp_wrapu(struct esm_softc *, int, u_int16_t,
125 1.1 rh u_int16_t);
126 1.1 rh static inline void wp_settimer(struct esm_softc *, u_int);
127 1.1 rh static inline void wp_starttimer(struct esm_softc *);
128 1.1 rh static inline void wp_stoptimer(struct esm_softc *);
129 1.1 rh
130 1.1 rh static inline u_int16_t wc_rdreg(struct esm_softc *, u_int16_t);
131 1.1 rh static inline void wc_wrreg(struct esm_softc *, u_int16_t, u_int16_t);
132 1.1 rh static inline u_int16_t wc_rdchctl(struct esm_softc *, int);
133 1.1 rh static inline void wc_wrchctl(struct esm_softc *, int, u_int16_t);
134 1.1 rh
135 1.1 rh static inline u_int calc_timer_freq(struct esm_chinfo*);
136 1.1 rh static void set_timer(struct esm_softc *);
137 1.1 rh
138 1.1 rh static void esmch_set_format(struct esm_chinfo *,
139 1.1 rh struct audio_params *p);
140 1.1 rh
141 1.7 ichiro /* Power Management */
142 1.7 ichiro void esm_powerhook(int, void *);
143 1.7 ichiro
144 1.1 rh struct cfattach esm_ca = {
145 1.1 rh sizeof(struct esm_softc), esm_match, esm_attach
146 1.1 rh };
147 1.1 rh
148 1.1 rh struct audio_hw_if esm_hw_if = {
149 1.1 rh esm_open,
150 1.1 rh esm_close,
151 1.1 rh NULL, /* drain */
152 1.1 rh esm_query_encoding,
153 1.1 rh esm_set_params,
154 1.1 rh esm_round_blocksize,
155 1.1 rh NULL, /* commit_settings */
156 1.1 rh esm_init_output,
157 1.1 rh NULL, /* init_input */
158 1.1 rh NULL, /* start_output */
159 1.1 rh NULL, /* start_input */
160 1.1 rh esm_halt_output,
161 1.1 rh esm_halt_input,
162 1.1 rh NULL, /* speaker_ctl */
163 1.1 rh esm_getdev,
164 1.1 rh NULL, /* getfd */
165 1.1 rh esm_set_port,
166 1.1 rh esm_get_port,
167 1.1 rh esm_query_devinfo,
168 1.1 rh esm_malloc,
169 1.1 rh esm_free,
170 1.1 rh esm_round_buffersize,
171 1.1 rh esm_mappage,
172 1.1 rh esm_get_props,
173 1.1 rh esm_trigger_output,
174 1.11 augustss esm_trigger_input,
175 1.11 augustss NULL,
176 1.1 rh };
177 1.1 rh
178 1.1 rh struct audio_device esm_device = {
179 1.1 rh "ESS Maestro",
180 1.1 rh "",
181 1.1 rh "esm"
182 1.1 rh };
183 1.1 rh
184 1.1 rh
185 1.1 rh static audio_encoding_t esm_encoding[] = {
186 1.1 rh { 0, AudioEulinear, AUDIO_ENCODING_ULINEAR, 8, 0 },
187 1.1 rh { 1, AudioEmulaw, AUDIO_ENCODING_ULAW, 8,
188 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
189 1.1 rh { 2, AudioEalaw, AUDIO_ENCODING_ALAW, 8, AUDIO_ENCODINGFLAG_EMULATED },
190 1.1 rh { 3, AudioEslinear, AUDIO_ENCODING_SLINEAR, 8, 0 },
191 1.1 rh { 4, AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 16, 0 },
192 1.1 rh { 5, AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 16,
193 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
194 1.1 rh { 6, AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 16,
195 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
196 1.1 rh { 7, AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 16,
197 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
198 1.1 rh };
199 1.1 rh
200 1.1 rh #define MAESTRO_NENCODINGS 8
201 1.1 rh
202 1.3 rh
203 1.3 rh static const struct esm_quirks esm_quirks[] = {
204 1.3 rh /* COMPAL 38W2 OEM Notebook, e.g. Dell INSPIRON 5000e */
205 1.3 rh { PCI_VENDOR_COMPAL, PCI_PRODUCT_COMPAL_38W2, ESM_QUIRKF_SWAPPEDCH },
206 1.3 rh
207 1.5 rh /* COMPAQ Armada M700 Notebook */
208 1.5 rh { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_M700, ESM_QUIRKF_SWAPPEDCH },
209 1.5 rh
210 1.3 rh /* NEC Versa Pro LX VA26D */
211 1.3 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VA26D, ESM_QUIRKF_GPIO },
212 1.3 rh
213 1.3 rh /* NEC Versa LX */
214 1.6 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSALX, ESM_QUIRKF_GPIO },
215 1.6 rh
216 1.10 simonb /* Toshiba Portege */
217 1.10 simonb { PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_PORTEGE, ESM_QUIRKF_SWAPPEDCH }
218 1.3 rh };
219 1.3 rh
220 1.3 rh enum esm_quirk_flags
221 1.3 rh esm_get_quirks(pcireg_t subid)
222 1.3 rh {
223 1.3 rh int i;
224 1.3 rh
225 1.3 rh for (i = 0; i < (sizeof esm_quirks / sizeof esm_quirks[0]); i++) {
226 1.3 rh if (PCI_VENDOR(subid) == esm_quirks[i].eq_vendor &&
227 1.3 rh PCI_PRODUCT(subid) == esm_quirks[i].eq_product) {
228 1.3 rh return esm_quirks[i].eq_quirks;
229 1.3 rh }
230 1.3 rh }
231 1.3 rh
232 1.3 rh return 0;
233 1.3 rh }
234 1.3 rh
235 1.3 rh
236 1.1 rh #ifdef AUDIO_DEBUG
237 1.1 rh struct esm_reg_info {
238 1.1 rh int offset; /* register offset */
239 1.1 rh int width; /* 1/2/4 bytes */
240 1.1 rh } dump_regs[] = {
241 1.1 rh { PORT_WAVCACHE_CTRL, 2 },
242 1.1 rh { PORT_HOSTINT_CTRL, 2 },
243 1.1 rh { PORT_HOSTINT_STAT, 2 },
244 1.1 rh { PORT_HWVOL_VOICE_SHADOW, 1 },
245 1.1 rh { PORT_HWVOL_VOICE, 1 },
246 1.1 rh { PORT_HWVOL_MASTER_SHADOW, 1 },
247 1.1 rh { PORT_HWVOL_MASTER, 1 },
248 1.1 rh { PORT_RINGBUS_CTRL, 4 },
249 1.1 rh { PORT_GPIO_DATA, 2 },
250 1.1 rh { PORT_GPIO_MASK, 2 },
251 1.1 rh { PORT_GPIO_DIR, 2 },
252 1.1 rh { PORT_ASSP_CTRL_A, 1 },
253 1.1 rh { PORT_ASSP_CTRL_B, 1 },
254 1.1 rh { PORT_ASSP_CTRL_C, 1 },
255 1.3 rh { PORT_ASSP_INT_STAT, 1 }
256 1.1 rh };
257 1.1 rh
258 1.2 lukem static void
259 1.2 lukem esm_dump_regs(struct esm_softc *ess)
260 1.1 rh {
261 1.3 rh int i;
262 1.1 rh
263 1.1 rh printf("%s registers:", ess->sc_dev.dv_xname);
264 1.3 rh for (i = 0; i < (sizeof dump_regs / sizeof dump_regs[0]); i++) {
265 1.1 rh if (i % 5 == 0)
266 1.1 rh printf("\n");
267 1.1 rh printf("0x%2.2x: ", dump_regs[i].offset);
268 1.1 rh switch(dump_regs[i].width) {
269 1.1 rh case 4:
270 1.1 rh printf("%8.8x, ", bus_space_read_4(ess->st, ess->sh,
271 1.1 rh dump_regs[i].offset));
272 1.1 rh break;
273 1.1 rh case 2:
274 1.1 rh printf("%4.4x, ", bus_space_read_2(ess->st, ess->sh,
275 1.1 rh dump_regs[i].offset));
276 1.1 rh break;
277 1.1 rh default:
278 1.1 rh printf("%2.2x, ",
279 1.1 rh bus_space_read_1(ess->st, ess->sh,
280 1.1 rh dump_regs[i].offset));
281 1.1 rh }
282 1.1 rh }
283 1.1 rh printf("\n");
284 1.1 rh }
285 1.1 rh #endif
286 1.1 rh
287 1.3 rh
288 1.1 rh /* -----------------------------
289 1.1 rh * Subsystems.
290 1.1 rh */
291 1.1 rh
292 1.1 rh /* Codec/Ringbus */
293 1.1 rh
294 1.1 rh /* -------------------------------------------------------------------- */
295 1.1 rh
296 1.1 rh int
297 1.1 rh esm_read_codec(void *sc, u_int8_t regno, u_int16_t *result)
298 1.1 rh {
299 1.1 rh struct esm_softc *ess = sc;
300 1.1 rh unsigned t;
301 1.1 rh
302 1.1 rh /* We have to wait for a SAFE time to write addr/data */
303 1.1 rh for (t = 0; t < 20; t++) {
304 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
305 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
306 1.1 rh break;
307 1.1 rh delay(2); /* 20.8us / 13 */
308 1.1 rh }
309 1.1 rh if (t == 20)
310 1.1 rh printf("%s: esm_read_codec() PROGLESS timed out.\n",
311 1.1 rh ess->sc_dev.dv_xname);
312 1.1 rh
313 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
314 1.1 rh CODEC_CMD_READ | regno);
315 1.1 rh delay(21); /* AC97 cycle = 20.8usec */
316 1.1 rh
317 1.1 rh /* Wait for data retrieve */
318 1.1 rh for (t = 0; t < 20; t++) {
319 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
320 1.1 rh & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE)
321 1.1 rh break;
322 1.1 rh delay(2); /* 20.8us / 13 */
323 1.1 rh }
324 1.1 rh if (t == 20)
325 1.1 rh /* Timed out, but perform dummy read. */
326 1.1 rh printf("%s: esm_read_codec() RW_DONE timed out.\n",
327 1.1 rh ess->sc_dev.dv_xname);
328 1.1 rh
329 1.1 rh *result = bus_space_read_2(ess->st, ess->sh, PORT_CODEC_REG);
330 1.1 rh
331 1.1 rh return 0;
332 1.1 rh }
333 1.1 rh
334 1.1 rh int
335 1.1 rh esm_write_codec(void *sc, u_int8_t regno, u_int16_t data)
336 1.1 rh {
337 1.1 rh struct esm_softc *ess = sc;
338 1.1 rh unsigned t;
339 1.1 rh
340 1.1 rh /* We have to wait for a SAFE time to write addr/data */
341 1.1 rh for (t = 0; t < 20; t++) {
342 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
343 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
344 1.1 rh break;
345 1.1 rh delay(2); /* 20.8us / 13 */
346 1.1 rh }
347 1.1 rh if (t == 20) {
348 1.1 rh /* Timed out. Abort writing. */
349 1.1 rh printf("%s: esm_write_codec() PROGLESS timed out.\n",
350 1.1 rh ess->sc_dev.dv_xname);
351 1.1 rh return -1;
352 1.1 rh }
353 1.1 rh
354 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_CODEC_REG, data);
355 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
356 1.1 rh CODEC_CMD_WRITE | regno);
357 1.1 rh
358 1.1 rh return 0;
359 1.1 rh }
360 1.1 rh
361 1.1 rh /* -------------------------------------------------------------------- */
362 1.1 rh
363 1.1 rh static inline void
364 1.1 rh ringbus_setdest(struct esm_softc *ess, int src, int dest)
365 1.1 rh {
366 1.1 rh u_int32_t data;
367 1.1 rh
368 1.1 rh data = bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL);
369 1.1 rh data &= ~(0xfU << src);
370 1.1 rh data |= (0xfU & dest) << src;
371 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, data);
372 1.1 rh }
373 1.1 rh
374 1.1 rh /* Wave Processor */
375 1.1 rh
376 1.1 rh static inline u_int16_t
377 1.1 rh wp_rdreg(struct esm_softc *ess, u_int16_t reg)
378 1.1 rh {
379 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
380 1.1 rh return bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA);
381 1.1 rh }
382 1.1 rh
383 1.1 rh static inline void
384 1.1 rh wp_wrreg(struct esm_softc *ess, u_int16_t reg, u_int16_t data)
385 1.1 rh {
386 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
387 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
388 1.1 rh }
389 1.1 rh
390 1.1 rh static inline void
391 1.1 rh apu_setindex(struct esm_softc *ess, u_int16_t reg)
392 1.1 rh {
393 1.1 rh int t;
394 1.1 rh
395 1.1 rh wp_wrreg(ess, WPREG_CRAM_PTR, reg);
396 1.1 rh /* Sometimes WP fails to set apu register index. */
397 1.1 rh for (t = 0; t < 1000; t++) {
398 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == reg)
399 1.1 rh break;
400 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, reg);
401 1.1 rh }
402 1.1 rh if (t == 1000)
403 1.1 rh printf("%s: apu_setindex() timed out.\n", ess->sc_dev.dv_xname);
404 1.1 rh }
405 1.1 rh
406 1.1 rh static inline u_int16_t
407 1.1 rh wp_rdapu(struct esm_softc *ess, int ch, u_int16_t reg)
408 1.1 rh {
409 1.1 rh u_int16_t ret;
410 1.1 rh
411 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg);
412 1.1 rh ret = wp_rdreg(ess, WPREG_DATA_PORT);
413 1.1 rh return ret;
414 1.1 rh }
415 1.1 rh
416 1.1 rh static inline void
417 1.1 rh wp_wrapu(struct esm_softc *ess, int ch, u_int16_t reg, u_int16_t data)
418 1.1 rh {
419 1.1 rh int t;
420 1.1 rh
421 1.1 rh DPRINTF(ESM_DEBUG_APU,
422 1.1 rh ("wp_wrapu(%p, ch=%d, reg=0x%x, data=0x%04x)\n",
423 1.1 rh ess, ch, reg, data));
424 1.1 rh
425 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg);
426 1.1 rh wp_wrreg(ess, WPREG_DATA_PORT, data);
427 1.1 rh for (t = 0; t < 1000; t++) {
428 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == data)
429 1.1 rh break;
430 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
431 1.1 rh }
432 1.1 rh if (t == 1000)
433 1.1 rh printf("%s: wp_wrapu() timed out.\n", ess->sc_dev.dv_xname);
434 1.1 rh }
435 1.1 rh
436 1.1 rh static inline void
437 1.1 rh wp_settimer(struct esm_softc *ess, u_int freq)
438 1.1 rh {
439 1.1 rh u_int clock = 48000 << 2;
440 1.1 rh u_int prescale = 0, divide = (freq != 0) ? (clock / freq) : ~0;
441 1.1 rh
442 1.1 rh RANGE(divide, WPTIMER_MINDIV, WPTIMER_MAXDIV);
443 1.1 rh
444 1.1 rh for (; divide > 32 << 1; divide >>= 1)
445 1.1 rh prescale++;
446 1.1 rh divide = (divide + 1) >> 1;
447 1.1 rh
448 1.1 rh for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
449 1.1 rh prescale++;
450 1.1 rh
451 1.1 rh DPRINTF(ESM_DEBUG_TIMER,
452 1.1 rh ("wp_settimer(%p, %u): clock = %u, prescale = %u, divide = %u\n",
453 1.1 rh ess, freq, clock, prescale, divide));
454 1.1 rh
455 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
456 1.1 rh wp_wrreg(ess, WPREG_TIMER_FREQ,
457 1.1 rh (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
458 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
459 1.1 rh }
460 1.1 rh
461 1.1 rh static inline void
462 1.1 rh wp_starttimer(struct esm_softc *ess)
463 1.1 rh {
464 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 1);
465 1.1 rh }
466 1.1 rh
467 1.1 rh static inline void
468 1.1 rh wp_stoptimer(struct esm_softc *ess)
469 1.1 rh {
470 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 0);
471 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
472 1.1 rh }
473 1.1 rh
474 1.1 rh /* WaveCache */
475 1.1 rh
476 1.1 rh static inline u_int16_t
477 1.1 rh wc_rdreg(struct esm_softc *ess, u_int16_t reg)
478 1.1 rh {
479 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
480 1.1 rh return bus_space_read_2(ess->st, ess->sh, PORT_WAVCACHE_DATA);
481 1.1 rh }
482 1.1 rh
483 1.1 rh static inline void
484 1.1 rh wc_wrreg(struct esm_softc *ess, u_int16_t reg, u_int16_t data)
485 1.1 rh {
486 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
487 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_DATA, data);
488 1.1 rh }
489 1.1 rh
490 1.1 rh static inline u_int16_t
491 1.1 rh wc_rdchctl(struct esm_softc *ess, int ch)
492 1.1 rh {
493 1.1 rh return wc_rdreg(ess, ch << 3);
494 1.1 rh }
495 1.1 rh
496 1.1 rh static inline void
497 1.1 rh wc_wrchctl(struct esm_softc *ess, int ch, u_int16_t data)
498 1.1 rh {
499 1.1 rh wc_wrreg(ess, ch << 3, data);
500 1.1 rh }
501 1.1 rh
502 1.1 rh /* Power management */
503 1.1 rh
504 1.1 rh void
505 1.1 rh esm_power(struct esm_softc *ess, int status)
506 1.1 rh {
507 1.1 rh u_int8_t data;
508 1.1 rh
509 1.1 rh data = pci_conf_read(ess->pc, ess->tag, CONF_PM_PTR);
510 1.1 rh if ((pci_conf_read(ess->pc, ess->tag, data) & 0xff) == PPMI_CID)
511 1.1 rh pci_conf_write(ess->pc, ess->tag, data + PM_CTRL, status);
512 1.1 rh }
513 1.1 rh
514 1.1 rh
515 1.1 rh /* -----------------------------
516 1.1 rh * Controller.
517 1.1 rh */
518 1.1 rh
519 1.1 rh int
520 1.1 rh esm_attach_codec(void *sc, struct ac97_codec_if *codec_if)
521 1.1 rh {
522 1.1 rh struct esm_softc *ess = sc;
523 1.1 rh
524 1.1 rh ess->codec_if = codec_if;
525 1.1 rh
526 1.1 rh return 0;
527 1.1 rh }
528 1.1 rh
529 1.1 rh void
530 1.1 rh esm_reset_codec(void *sc)
531 1.1 rh {
532 1.1 rh }
533 1.1 rh
534 1.1 rh
535 1.3 rh enum ac97_host_flags
536 1.3 rh esm_flags_codec(void *sc)
537 1.3 rh {
538 1.3 rh struct esm_softc *ess = sc;
539 1.3 rh
540 1.3 rh return ess->codec_flags;
541 1.3 rh }
542 1.3 rh
543 1.3 rh
544 1.1 rh void
545 1.1 rh esm_initcodec(struct esm_softc *ess)
546 1.1 rh {
547 1.1 rh u_int16_t data;
548 1.1 rh
549 1.1 rh DPRINTF(ESM_DEBUG_CODEC, ("esm_initcodec(%p)\n", ess));
550 1.1 rh
551 1.1 rh if (bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL)
552 1.1 rh & RINGBUS_CTRL_ACLINK_ENABLED) {
553 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
554 1.1 rh delay(104); /* 20.8us * (4 + 1) */
555 1.1 rh }
556 1.1 rh /* XXX - 2nd codec should be looked at. */
557 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
558 1.1 rh RINGBUS_CTRL_AC97_SWRESET);
559 1.1 rh delay(2);
560 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
561 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED);
562 1.1 rh delay(21);
563 1.1 rh
564 1.1 rh esm_read_codec(ess, 0, &data);
565 1.1 rh if (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
566 1.1 rh & CODEC_STAT_MASK) {
567 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
568 1.1 rh delay(21);
569 1.1 rh
570 1.1 rh /* Try cold reset. */
571 1.1 rh printf("%s: will perform cold reset.\n", ess->sc_dev.dv_xname);
572 1.1 rh data = bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR);
573 1.1 rh if (pci_conf_read(ess->pc, ess->tag, 0x58) & 1)
574 1.1 rh data |= 0x10;
575 1.1 rh data |= 0x009 &
576 1.1 rh ~bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DATA);
577 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0xff6);
578 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
579 1.1 rh data | 0x009);
580 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x000);
581 1.1 rh delay(2);
582 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x001);
583 1.1 rh delay(1);
584 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x009);
585 1.1 rh delay(500000);
586 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, data);
587 1.1 rh delay(84); /* 20.8us * 4 */
588 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
589 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED);
590 1.1 rh delay(21);
591 1.1 rh }
592 1.1 rh }
593 1.1 rh
594 1.1 rh void
595 1.1 rh esm_init(struct esm_softc *ess)
596 1.1 rh {
597 1.1 rh /* Reset direct sound. */
598 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
599 1.1 rh HOSTINT_CTRL_DSOUND_RESET);
600 1.1 rh delay(10000);
601 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
602 1.1 rh delay(10000);
603 1.1 rh
604 1.1 rh /* Enable direct sound interruption. */
605 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
606 1.1 rh HOSTINT_CTRL_DSOUND_INT_ENABLED);
607 1.1 rh
608 1.1 rh /* Setup Wave Processor. */
609 1.1 rh
610 1.1 rh /* Enable WaveCache */
611 1.1 rh wp_wrreg(ess, WPREG_WAVE_ROMRAM,
612 1.1 rh WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
613 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_CTRL,
614 1.1 rh WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB);
615 1.1 rh
616 1.1 rh /* Setup Codec/Ringbus. */
617 1.1 rh esm_initcodec(ess);
618 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
619 1.1 rh RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED);
620 1.1 rh
621 1.1 rh wp_wrreg(ess, WPREG_BASE, 0x8500); /* Parallel I/O */
622 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_ADC,
623 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
624 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
625 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
626 1.1 rh
627 1.1 rh /* Setup ASSP. Needed for Dell Inspiron 7500? */
628 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_B, 0x00);
629 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_A, 0x03);
630 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_C, 0x00);
631 1.1 rh
632 1.1 rh /*
633 1.1 rh * Setup GPIO.
634 1.1 rh * There seems to be speciality with NEC systems.
635 1.1 rh */
636 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_GPIO) {
637 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK,
638 1.3 rh 0x9ff);
639 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
640 1.3 rh bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR) |
641 1.3 rh 0x600);
642 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA,
643 1.3 rh 0x200);
644 1.1 rh }
645 1.1 rh
646 1.1 rh DUMPREG(ess);
647 1.1 rh }
648 1.1 rh
649 1.1 rh
650 1.1 rh /* Channel controller. */
651 1.1 rh
652 1.1 rh int
653 1.1 rh esm_init_output (void *sc, void *start, int size)
654 1.1 rh {
655 1.1 rh struct esm_softc *ess = sc;
656 1.1 rh struct esm_dma *p;
657 1.1 rh u_int32_t data;
658 1.1 rh
659 1.1 rh for (p = ess->sc_dmas; p && KERNADDR(p) != start; p = p->next)
660 1.1 rh ;
661 1.1 rh if (!p) {
662 1.1 rh printf("%s: esm_init_output: bad addr %p\n",
663 1.1 rh ess->sc_dev.dv_xname, start);
664 1.1 rh return EINVAL;
665 1.1 rh }
666 1.1 rh
667 1.1 rh ess->pch.base = DMAADDR(p) & ~0xFFF;
668 1.1 rh
669 1.1 rh DPRINTF(ESM_DEBUG_DMA, ("%s: pch.base = 0x%x\n",
670 1.1 rh ess->sc_dev.dv_xname, ess->pch.base));
671 1.1 rh
672 1.1 rh /* set DMA base address */
673 1.1 rh for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
674 1.1 rh wc_wrreg(ess, data, ess->pch.base >> WAVCACHE_BASEADDR_SHIFT);
675 1.1 rh
676 1.1 rh return 0;
677 1.1 rh }
678 1.1 rh
679 1.1 rh
680 1.1 rh int
681 1.1 rh esm_trigger_output(void *sc, void *start, void *end, int blksize,
682 1.1 rh void (*intr)(void *), void *arg, struct audio_params *param)
683 1.1 rh {
684 1.1 rh struct esm_softc *ess = sc;
685 1.1 rh struct esm_chinfo *ch = &ess->pch;
686 1.1 rh struct esm_dma *p;
687 1.1 rh int pan = 0, choffset;
688 1.3 rh int i, nch = 1;
689 1.1 rh unsigned speed = ch->sample_rate, offset, wpwa, dv;
690 1.1 rh size_t size;
691 1.1 rh u_int16_t apuch = ch->num << 1;
692 1.1 rh
693 1.1 rh DPRINTF(ESM_DEBUG_DMA,
694 1.1 rh ("esm_trigger_output(%p, %p, %p, 0x%x, %p, %p, %p)\n",
695 1.1 rh sc, start, end, blksize, intr, arg, param));
696 1.1 rh
697 1.1 rh #ifdef DIAGNOSTIC
698 1.1 rh if (ess->pactive) {
699 1.1 rh printf("%s: esm_trigger_output: already running",
700 1.1 rh ess->sc_dev.dv_xname);
701 1.1 rh return EINVAL;
702 1.1 rh }
703 1.1 rh #endif
704 1.1 rh
705 1.1 rh ess->sc_pintr = intr;
706 1.1 rh ess->sc_parg = arg;
707 1.1 rh for (p = ess->sc_dmas; p && KERNADDR(p) != start; p = p->next)
708 1.1 rh ;
709 1.1 rh if (!p) {
710 1.1 rh printf("%s: esm_trigger_output: bad addr %p\n",
711 1.1 rh ess->sc_dev.dv_xname, start);
712 1.1 rh return EINVAL;
713 1.1 rh }
714 1.1 rh
715 1.1 rh ess->pch.blocksize = blksize;
716 1.1 rh ess->pch.apublk = blksize >> 1;
717 1.1 rh ess->pactive = 1;
718 1.1 rh
719 1.1 rh size = (size_t)(((caddr_t)end - (caddr_t)start) >> 1);
720 1.1 rh choffset = DMAADDR(p) - ess->pch.base;
721 1.1 rh offset = choffset >> 1;
722 1.1 rh wpwa = APU_USE_SYSMEM | (offset >> 9);
723 1.1 rh
724 1.1 rh DPRINTF(ESM_DEBUG_DMA,
725 1.1 rh ("choffs=0x%x, wpwa=0x%x, size=0x%x words\n",
726 1.1 rh choffset, wpwa, size));
727 1.1 rh
728 1.1 rh switch (ch->aputype) {
729 1.1 rh case APUTYPE_16BITSTEREO:
730 1.1 rh ess->pch.apublk >>= 1;
731 1.1 rh wpwa >>= 1;
732 1.1 rh size >>= 1;
733 1.1 rh offset >>= 1;
734 1.1 rh /* FALLTHROUGH */
735 1.1 rh case APUTYPE_8BITSTEREO:
736 1.3 rh if (ess->codec_flags & AC97_HOST_SWAPPED_CHANNELS)
737 1.3 rh pan = 8;
738 1.3 rh else
739 1.3 rh pan = -8;
740 1.3 rh nch++;
741 1.1 rh break;
742 1.1 rh case APUTYPE_8BITLINEAR:
743 1.1 rh ess->pch.apublk <<= 1;
744 1.1 rh speed >>= 1;
745 1.1 rh break;
746 1.1 rh }
747 1.1 rh
748 1.1 rh ess->pch.apubuf = size;
749 1.1 rh ess->pch.nextirq = ess->pch.apublk;
750 1.1 rh
751 1.1 rh set_timer(ess);
752 1.1 rh wp_starttimer(ess);
753 1.1 rh
754 1.1 rh dv = (((speed % 48000) << 16) + 24000) / 48000
755 1.1 rh + ((speed / 48000) << 16);
756 1.1 rh
757 1.3 rh for (i = nch-1; i >= 0; i--) {
758 1.3 rh wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa & 0xff00);
759 1.3 rh wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset);
760 1.3 rh wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size);
761 1.3 rh wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1);
762 1.3 rh wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800);
763 1.3 rh wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00
764 1.1 rh | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
765 1.1 rh | ((PAN_FRONT + pan) << APU_PAN_SHIFT));
766 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB
767 1.1 rh | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
768 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8);
769 1.1 rh
770 1.1 rh if (ch->aputype == APUTYPE_16BITSTEREO)
771 1.1 rh wpwa |= APU_STEREO >> 1;
772 1.1 rh pan = -pan;
773 1.3 rh }
774 1.1 rh
775 1.1 rh wc_wrchctl(ess, apuch, ch->wcreg_tpl);
776 1.3 rh if (nch > 1)
777 1.3 rh wc_wrchctl(ess, apuch + 1, ch->wcreg_tpl);
778 1.1 rh
779 1.1 rh wp_wrapu(ess, apuch, APUREG_APUTYPE,
780 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
781 1.1 rh if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO)
782 1.1 rh wp_wrapu(ess, apuch + 1, APUREG_APUTYPE,
783 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
784 1.1 rh
785 1.1 rh return 0;
786 1.1 rh }
787 1.1 rh
788 1.1 rh
789 1.1 rh int
790 1.1 rh esm_trigger_input(void *sc, void *start, void *end, int blksize,
791 1.1 rh void (*intr)(void *), void *arg, struct audio_params *param)
792 1.1 rh {
793 1.1 rh return 0;
794 1.1 rh }
795 1.1 rh
796 1.1 rh
797 1.1 rh int
798 1.1 rh esm_halt_output(void *sc)
799 1.1 rh {
800 1.1 rh struct esm_softc *ess = sc;
801 1.1 rh struct esm_chinfo *ch = &ess->pch;
802 1.1 rh
803 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_output(%p)\n", sc));
804 1.1 rh
805 1.1 rh wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE,
806 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
807 1.1 rh wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE,
808 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
809 1.1 rh
810 1.1 rh ess->pactive = 0;
811 1.1 rh if (!ess->ractive)
812 1.1 rh wp_stoptimer(ess);
813 1.1 rh
814 1.1 rh return 0;
815 1.1 rh }
816 1.1 rh
817 1.1 rh
818 1.1 rh int
819 1.1 rh esm_halt_input(void *sc)
820 1.1 rh {
821 1.1 rh return 0;
822 1.1 rh }
823 1.1 rh
824 1.1 rh
825 1.1 rh static inline u_int
826 1.1 rh calc_timer_freq(struct esm_chinfo *ch)
827 1.1 rh {
828 1.1 rh u_int freq;
829 1.1 rh
830 1.1 rh freq = (ch->sample_rate + ch->apublk - 1) / ch->apublk;
831 1.1 rh
832 1.1 rh DPRINTF(ESM_DEBUG_TIMER,
833 1.1 rh ("calc_timer_freq(%p): rate = %u, blk = 0x%x (0x%x): freq = %u\n",
834 1.1 rh ch, ch->sample_rate, ch->apublk, ch->blocksize, freq));
835 1.1 rh
836 1.1 rh return freq;
837 1.1 rh }
838 1.1 rh
839 1.1 rh static void
840 1.1 rh set_timer(struct esm_softc *ess)
841 1.1 rh {
842 1.1 rh unsigned freq = 0, freq2;
843 1.1 rh
844 1.1 rh if (ess->pactive)
845 1.1 rh freq = calc_timer_freq(&ess->pch);
846 1.1 rh
847 1.1 rh if (ess->ractive) {
848 1.1 rh freq2 = calc_timer_freq(&ess->rch);
849 1.1 rh if (freq2 < freq)
850 1.1 rh freq = freq2;
851 1.1 rh }
852 1.1 rh
853 1.1 rh for (; freq < MAESTRO_MINFREQ; freq <<= 1)
854 1.1 rh ;
855 1.1 rh
856 1.1 rh if (freq > 0)
857 1.1 rh wp_settimer(ess, freq);
858 1.1 rh }
859 1.1 rh
860 1.1 rh
861 1.1 rh static void
862 1.1 rh esmch_set_format(struct esm_chinfo *ch, struct audio_params *p)
863 1.1 rh {
864 1.1 rh u_int16_t wcreg_tpl = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
865 1.1 rh u_int16_t aputype = APUTYPE_16BITLINEAR;
866 1.1 rh
867 1.1 rh if (p->channels == 2) {
868 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_STEREO;
869 1.1 rh aputype++;
870 1.1 rh }
871 1.1 rh if (p->precision * p->factor == 8) {
872 1.1 rh aputype += 2;
873 1.1 rh if (p->encoding == AUDIO_ENCODING_ULINEAR)
874 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_U8;
875 1.1 rh }
876 1.1 rh ch->wcreg_tpl = wcreg_tpl;
877 1.1 rh ch->aputype = aputype;
878 1.1 rh ch->sample_rate = p->sample_rate;
879 1.1 rh
880 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esmch_set_format: "
881 1.1 rh "numch=%d, prec=%d*%d, tpl=0x%x, aputype=%d, rate=%ld\n",
882 1.1 rh p->channels, p->precision, p->factor, wcreg_tpl, aputype,
883 1.1 rh p->sample_rate));
884 1.1 rh }
885 1.1 rh
886 1.1 rh
887 1.1 rh /*
888 1.1 rh * Audio interface glue functions
889 1.1 rh */
890 1.1 rh
891 1.1 rh int
892 1.1 rh esm_open(void *sc, int flags)
893 1.1 rh {
894 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_open(%p, 0x%x)\n", sc, flags));
895 1.1 rh
896 1.1 rh return 0;
897 1.1 rh }
898 1.1 rh
899 1.1 rh
900 1.1 rh void
901 1.1 rh esm_close(void *sc)
902 1.1 rh {
903 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_close(%p)\n", sc));
904 1.1 rh }
905 1.1 rh
906 1.1 rh
907 1.1 rh int
908 1.1 rh esm_getdev (void *sc, struct audio_device *adp)
909 1.1 rh {
910 1.1 rh *adp = esm_device;
911 1.1 rh return 0;
912 1.1 rh }
913 1.1 rh
914 1.1 rh
915 1.1 rh int
916 1.1 rh esm_round_blocksize (void *sc, int blk)
917 1.1 rh {
918 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
919 1.1 rh ("esm_round_blocksize(%p, 0x%x)", sc, blk));
920 1.1 rh
921 1.1 rh blk &= ~0x3f; /* keep good alignment */
922 1.1 rh
923 1.1 rh DPRINTF(ESM_DEBUG_PARAM, (" = 0x%x\n", blk));
924 1.1 rh
925 1.1 rh return blk;
926 1.1 rh }
927 1.1 rh
928 1.1 rh
929 1.1 rh int
930 1.1 rh esm_query_encoding(void *sc, struct audio_encoding *fp)
931 1.1 rh {
932 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
933 1.1 rh ("esm_query_encoding(%p, %d)\n", sc, fp->index));
934 1.1 rh
935 1.1 rh if (fp->index < 0 || fp->index >= MAESTRO_NENCODINGS)
936 1.1 rh return EINVAL;
937 1.1 rh
938 1.1 rh *fp = esm_encoding[fp->index];
939 1.1 rh return 0;
940 1.1 rh }
941 1.1 rh
942 1.1 rh
943 1.1 rh int
944 1.1 rh esm_set_params(void *sc, int setmode, int usemode,
945 1.1 rh struct audio_params *play, struct audio_params *rec)
946 1.1 rh {
947 1.1 rh struct esm_softc *ess = sc;
948 1.1 rh struct audio_params *p;
949 1.1 rh int mode;
950 1.1 rh
951 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
952 1.1 rh ("esm_set_params(%p, 0x%x, 0x%x, %p, %p)\n",
953 1.1 rh sc, setmode, usemode, play, rec));
954 1.1 rh
955 1.1 rh for (mode = AUMODE_RECORD; mode != -1;
956 1.1 rh mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
957 1.1 rh if ((setmode & mode) == 0)
958 1.1 rh continue;
959 1.1 rh
960 1.1 rh p = mode == AUMODE_PLAY ? play : rec;
961 1.1 rh
962 1.1 rh if (p->sample_rate < 4000 || p->sample_rate > 48000 ||
963 1.1 rh (p->precision != 8 && p->precision != 16) ||
964 1.1 rh (p->channels != 1 && p->channels != 2))
965 1.1 rh return EINVAL;
966 1.1 rh
967 1.1 rh p->factor = 1;
968 1.1 rh p->sw_code = 0;
969 1.1 rh switch (p->encoding) {
970 1.1 rh case AUDIO_ENCODING_SLINEAR_BE:
971 1.1 rh if (p->precision == 16)
972 1.1 rh p->sw_code = swap_bytes;
973 1.1 rh else
974 1.1 rh p->sw_code = change_sign8;
975 1.1 rh break;
976 1.1 rh case AUDIO_ENCODING_SLINEAR_LE:
977 1.1 rh if (p->precision != 16)
978 1.1 rh p->sw_code = change_sign8;
979 1.1 rh break;
980 1.1 rh case AUDIO_ENCODING_ULINEAR_BE:
981 1.1 rh if (p->precision == 16) {
982 1.1 rh if (mode == AUMODE_PLAY)
983 1.1 rh p->sw_code = swap_bytes_change_sign16_le;
984 1.1 rh else
985 1.1 rh p->sw_code = change_sign16_swap_bytes_le;
986 1.1 rh }
987 1.1 rh break;
988 1.1 rh case AUDIO_ENCODING_ULINEAR_LE:
989 1.1 rh if (p->precision == 16)
990 1.1 rh p->sw_code = change_sign16_le;
991 1.1 rh break;
992 1.1 rh case AUDIO_ENCODING_ULAW:
993 1.1 rh if (mode == AUMODE_PLAY) {
994 1.1 rh p->factor = 2;
995 1.1 rh p->sw_code = mulaw_to_slinear16_le;
996 1.1 rh } else
997 1.1 rh p->sw_code = ulinear8_to_mulaw;
998 1.1 rh break;
999 1.1 rh case AUDIO_ENCODING_ALAW:
1000 1.1 rh if (mode == AUMODE_PLAY) {
1001 1.1 rh p->factor = 2;
1002 1.1 rh p->sw_code = alaw_to_slinear16_le;
1003 1.1 rh } else
1004 1.1 rh p->sw_code = ulinear8_to_alaw;
1005 1.1 rh break;
1006 1.1 rh default:
1007 1.1 rh return EINVAL;
1008 1.1 rh }
1009 1.1 rh }
1010 1.1 rh
1011 1.1 rh if (setmode & AUMODE_PLAY)
1012 1.1 rh esmch_set_format(&ess->pch, play);
1013 1.1 rh
1014 1.1 rh if (setmode & AUMODE_RECORD)
1015 1.1 rh esmch_set_format(&ess->rch, rec);
1016 1.1 rh
1017 1.1 rh return 0;
1018 1.1 rh }
1019 1.1 rh
1020 1.1 rh
1021 1.1 rh int
1022 1.1 rh esm_set_port(void *sc, mixer_ctrl_t *cp)
1023 1.1 rh {
1024 1.1 rh struct esm_softc *ess = sc;
1025 1.1 rh
1026 1.1 rh return (ess->codec_if->vtbl->mixer_set_port(ess->codec_if, cp));
1027 1.1 rh }
1028 1.1 rh
1029 1.1 rh
1030 1.1 rh int
1031 1.1 rh esm_get_port(void *sc, mixer_ctrl_t *cp)
1032 1.1 rh {
1033 1.1 rh struct esm_softc *ess = sc;
1034 1.1 rh
1035 1.1 rh return (ess->codec_if->vtbl->mixer_get_port(ess->codec_if, cp));
1036 1.1 rh }
1037 1.1 rh
1038 1.1 rh
1039 1.1 rh int
1040 1.1 rh esm_query_devinfo(void *sc, mixer_devinfo_t *dip)
1041 1.1 rh {
1042 1.1 rh struct esm_softc *ess = sc;
1043 1.1 rh
1044 1.1 rh return (ess->codec_if->vtbl->query_devinfo(ess->codec_if, dip));
1045 1.1 rh }
1046 1.1 rh
1047 1.1 rh
1048 1.1 rh void *
1049 1.1 rh esm_malloc(void *sc, int direction, size_t size, int pool, int flags)
1050 1.1 rh {
1051 1.1 rh struct esm_softc *ess = sc;
1052 1.1 rh struct esm_dma *p;
1053 1.1 rh int error;
1054 1.1 rh
1055 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1056 1.1 rh ("esm_malloc(%p, %d, 0x%x, 0x%x, 0x%x)",
1057 1.1 rh sc, direction, size, pool, flags));
1058 1.1 rh
1059 1.1 rh p = malloc(sizeof(*p), pool, flags);
1060 1.1 rh if (!p)
1061 1.1 rh return 0;
1062 1.1 rh error = esm_allocmem(ess, size, 16, p);
1063 1.1 rh if (error) {
1064 1.1 rh free(p, pool);
1065 1.1 rh DPRINTF(ESM_DEBUG_DMA, (" = 0 (ENOMEM)\n"));
1066 1.1 rh return 0;
1067 1.1 rh }
1068 1.1 rh p->next = ess->sc_dmas;
1069 1.1 rh ess->sc_dmas = p;
1070 1.1 rh
1071 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1072 1.1 rh (": KERNADDR(%p) = %p (DMAADDR 0x%x)\n", p, KERNADDR(p), (int)DMAADDR(p)));
1073 1.1 rh
1074 1.1 rh return KERNADDR(p);
1075 1.1 rh }
1076 1.1 rh
1077 1.1 rh
1078 1.1 rh void
1079 1.1 rh esm_free(void *sc, void *ptr, int pool)
1080 1.1 rh {
1081 1.1 rh struct esm_softc *ess = sc;
1082 1.1 rh struct esm_dma *p, **pp;
1083 1.1 rh
1084 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1085 1.1 rh ("esm_free(%p, %p, 0x%x)\n",
1086 1.1 rh sc, ptr, pool));
1087 1.1 rh
1088 1.1 rh for (pp = &ess->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
1089 1.1 rh if (KERNADDR(p) == ptr) {
1090 1.1 rh esm_freemem(ess, p);
1091 1.1 rh *pp = p->next;
1092 1.1 rh free(p, pool);
1093 1.1 rh return;
1094 1.1 rh }
1095 1.1 rh }
1096 1.1 rh }
1097 1.1 rh
1098 1.1 rh
1099 1.1 rh size_t
1100 1.1 rh esm_round_buffersize(void *sc, int direction, size_t size)
1101 1.1 rh {
1102 1.1 rh return size;
1103 1.1 rh }
1104 1.1 rh
1105 1.1 rh
1106 1.1 rh paddr_t
1107 1.1 rh esm_mappage(void *sc, void *mem, off_t off, int prot)
1108 1.1 rh {
1109 1.1 rh struct esm_softc *ess = sc;
1110 1.1 rh struct esm_dma *p;
1111 1.1 rh
1112 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1113 1.1 rh ("esm_mappage(%p, %p, 0x%lx, 0x%x)\n",
1114 1.1 rh sc, mem, (unsigned long)off, prot));
1115 1.1 rh
1116 1.1 rh if (off < 0)
1117 1.1 rh return (-1);
1118 1.1 rh
1119 1.1 rh for (p = ess->sc_dmas; p && KERNADDR(p) != mem; p = p->next)
1120 1.1 rh ;
1121 1.1 rh if (!p)
1122 1.1 rh return (-1);
1123 1.1 rh return bus_dmamem_mmap(ess->dmat, p->segs, p->nsegs, off,
1124 1.1 rh prot, BUS_DMA_WAITOK);
1125 1.1 rh }
1126 1.1 rh
1127 1.1 rh
1128 1.1 rh int
1129 1.1 rh esm_get_props(void *sc)
1130 1.1 rh {
1131 1.1 rh return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1132 1.1 rh }
1133 1.1 rh
1134 1.1 rh
1135 1.1 rh /* -----------------------------
1136 1.1 rh * Bus space.
1137 1.1 rh */
1138 1.1 rh
1139 1.1 rh int
1140 1.1 rh esm_intr(void *sc)
1141 1.1 rh {
1142 1.1 rh struct esm_softc *ess = sc;
1143 1.1 rh u_int16_t status;
1144 1.1 rh u_int16_t pos;
1145 1.1 rh int ret = 0;
1146 1.1 rh
1147 1.1 rh status = bus_space_read_1(ess->st, ess->sh, PORT_HOSTINT_STAT);
1148 1.1 rh if (!status)
1149 1.1 rh return 0;
1150 1.1 rh
1151 1.1 rh /* Acknowledge all. */
1152 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
1153 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HOSTINT_STAT, 0);
1154 1.1 rh #if 0 /* XXX - HWVOL */
1155 1.1 rh if (status & HOSTINT_STAT_HWVOL) {
1156 1.1 rh u_int delta;
1157 1.1 rh delta = bus_space_read_1(ess->st, ess->sh, PORT_HWVOL_MASTER)
1158 1.1 rh - 0x88;
1159 1.1 rh if (delta & 0x11)
1160 1.1 rh mixer_set(device_get_softc(ess->dev),
1161 1.1 rh SOUND_MIXER_VOLUME, 0);
1162 1.1 rh else {
1163 1.1 rh mixer_set(device_get_softc(ess->dev),
1164 1.1 rh SOUND_MIXER_VOLUME,
1165 1.1 rh mixer_get(device_get_softc(ess->dev),
1166 1.1 rh SOUND_MIXER_VOLUME)
1167 1.1 rh + ((delta >> 5) & 0x7) - 4
1168 1.1 rh + ((delta << 7) & 0x700) - 0x400);
1169 1.1 rh }
1170 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HWVOL_MASTER, 0x88);
1171 1.1 rh ret++;
1172 1.1 rh }
1173 1.1 rh #endif /* XXX - HWVOL */
1174 1.1 rh
1175 1.1 rh if (ess->pactive) {
1176 1.1 rh pos = wp_rdapu(ess, ess->pch.num << 1, APUREG_CURPTR);
1177 1.1 rh
1178 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
1179 1.1 rh wp_rdapu(ess, (ess->pch.num<<1)+1, APUREG_CURPTR)));
1180 1.1 rh
1181 1.1 rh if (pos >= ess->pch.nextirq &&
1182 1.1 rh pos - ess->pch.nextirq < ess->pch.apubuf / 2) {
1183 1.1 rh ess->pch.nextirq += ess->pch.apublk;
1184 1.1 rh
1185 1.1 rh if (ess->pch.nextirq >= ess->pch.apubuf)
1186 1.1 rh ess->pch.nextirq = 0;
1187 1.1 rh
1188 1.1 rh if (ess->sc_pintr) {
1189 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("P\n"));
1190 1.1 rh ess->sc_pintr(ess->sc_parg);
1191 1.1 rh }
1192 1.1 rh
1193 1.1 rh }
1194 1.1 rh ret++;
1195 1.1 rh }
1196 1.1 rh
1197 1.1 rh if (ess->ractive) {
1198 1.1 rh pos = wp_rdapu(ess, ess->rch.num << 1, APUREG_CURPTR);
1199 1.1 rh
1200 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
1201 1.1 rh wp_rdapu(ess, (ess->rch.num<<1)+1, APUREG_CURPTR)));
1202 1.1 rh
1203 1.1 rh if (pos >= ess->rch.nextirq &&
1204 1.1 rh pos - ess->rch.nextirq < ess->rch.apubuf / 2) {
1205 1.1 rh ess->rch.nextirq += ess->rch.apublk;
1206 1.1 rh
1207 1.1 rh if (ess->rch.nextirq >= ess->rch.apubuf)
1208 1.1 rh ess->rch.nextirq = 0;
1209 1.1 rh
1210 1.1 rh if (ess->sc_rintr) {
1211 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("R\n"));
1212 1.1 rh ess->sc_rintr(ess->sc_parg);
1213 1.1 rh }
1214 1.1 rh
1215 1.1 rh }
1216 1.1 rh ret++;
1217 1.1 rh }
1218 1.1 rh
1219 1.1 rh return ret;
1220 1.1 rh }
1221 1.1 rh
1222 1.1 rh
1223 1.1 rh int
1224 1.1 rh esm_allocmem(struct esm_softc *sc, size_t size, size_t align,
1225 1.1 rh struct esm_dma *p)
1226 1.1 rh {
1227 1.1 rh int error;
1228 1.1 rh
1229 1.1 rh p->size = size;
1230 1.1 rh error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
1231 1.1 rh p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
1232 1.1 rh &p->nsegs, BUS_DMA_NOWAIT);
1233 1.1 rh if (error)
1234 1.1 rh return error;
1235 1.1 rh
1236 1.1 rh error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
1237 1.1 rh &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
1238 1.1 rh if (error)
1239 1.1 rh goto free;
1240 1.1 rh
1241 1.1 rh error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
1242 1.1 rh 0, BUS_DMA_NOWAIT, &p->map);
1243 1.1 rh if (error)
1244 1.1 rh goto unmap;
1245 1.1 rh
1246 1.1 rh error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
1247 1.1 rh BUS_DMA_NOWAIT);
1248 1.1 rh if (error)
1249 1.1 rh goto destroy;
1250 1.1 rh
1251 1.1 rh return 0;
1252 1.1 rh
1253 1.1 rh destroy:
1254 1.1 rh bus_dmamap_destroy(sc->dmat, p->map);
1255 1.1 rh unmap:
1256 1.1 rh bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1257 1.1 rh free:
1258 1.1 rh bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1259 1.1 rh
1260 1.1 rh return error;
1261 1.1 rh }
1262 1.1 rh
1263 1.1 rh
1264 1.1 rh int
1265 1.1 rh esm_freemem(struct esm_softc *sc, struct esm_dma *p)
1266 1.1 rh {
1267 1.1 rh bus_dmamap_unload(sc->dmat, p->map);
1268 1.1 rh bus_dmamap_destroy(sc->dmat, p->map);
1269 1.1 rh bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1270 1.1 rh bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1271 1.1 rh return 0;
1272 1.1 rh }
1273 1.1 rh
1274 1.1 rh
1275 1.1 rh int
1276 1.1 rh esm_match(struct device *dev, struct cfdata *match, void *aux)
1277 1.1 rh {
1278 1.1 rh struct pci_attach_args *pa = (struct pci_attach_args *) aux;
1279 1.1 rh
1280 1.1 rh switch (PCI_VENDOR(pa->pa_id)) {
1281 1.1 rh case PCI_VENDOR_ESSTECH:
1282 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) {
1283 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO1:
1284 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2:
1285 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2E:
1286 1.1 rh return 1;
1287 1.1 rh }
1288 1.1 rh
1289 1.1 rh case PCI_VENDOR_ESSTECH2:
1290 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) {
1291 1.1 rh case PCI_PRODUCT_ESSTECH2_MAESTRO1:
1292 1.1 rh return 1;
1293 1.1 rh }
1294 1.1 rh }
1295 1.1 rh return 0;
1296 1.1 rh }
1297 1.1 rh
1298 1.1 rh void
1299 1.1 rh esm_attach(struct device *parent, struct device *self, void *aux)
1300 1.1 rh {
1301 1.1 rh struct esm_softc *ess = (struct esm_softc *)self;
1302 1.1 rh struct pci_attach_args *pa = (struct pci_attach_args *)aux;
1303 1.1 rh pci_chipset_tag_t pc = pa->pa_pc;
1304 1.1 rh pcitag_t tag = pa->pa_tag;
1305 1.1 rh pci_intr_handle_t ih;
1306 1.1 rh pcireg_t csr, data;
1307 1.1 rh u_int16_t codec_data;
1308 1.1 rh const char *intrstr;
1309 1.1 rh int revision;
1310 1.1 rh char devinfo[256];
1311 1.1 rh
1312 1.1 rh pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
1313 1.1 rh revision = PCI_REVISION(pa->pa_class);
1314 1.1 rh printf(": %s (rev. 0x%02x)\n", devinfo, revision);
1315 1.1 rh
1316 1.1 rh /* Enable the device. */
1317 1.1 rh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
1318 1.1 rh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
1319 1.1 rh csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
1320 1.1 rh
1321 1.1 rh /* Map I/O register */
1322 1.1 rh if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
1323 1.1 rh &ess->st, &ess->sh, NULL, NULL)) {
1324 1.1 rh printf("%s: can't map i/o space\n", ess->sc_dev.dv_xname);
1325 1.1 rh return;
1326 1.1 rh }
1327 1.1 rh
1328 1.1 rh /* Initialize softc */
1329 1.1 rh ess->pch.num = 0;
1330 1.1 rh ess->rch.num = 2;
1331 1.1 rh ess->dmat = pa->pa_dmat;
1332 1.1 rh ess->tag = tag;
1333 1.1 rh ess->pc = pc;
1334 1.1 rh ess->subid = pci_conf_read(pc, tag, PCI_SUBSYS_ID_REG);
1335 1.1 rh
1336 1.3 rh DPRINTF(ESM_DEBUG_PCI,
1337 1.3 rh ("%s: sub-system vendor 0x%4.4x, product 0x%4.4x\n",
1338 1.3 rh ess->sc_dev.dv_xname,
1339 1.3 rh PCI_VENDOR(ess->subid), PCI_PRODUCT(ess->subid)));
1340 1.3 rh
1341 1.1 rh /* Map and establish the interrupt. */
1342 1.1 rh if (pci_intr_map(pa, &ih)) {
1343 1.1 rh printf("%s: can't map interrupt\n", ess->sc_dev.dv_xname);
1344 1.1 rh return;
1345 1.1 rh }
1346 1.1 rh intrstr = pci_intr_string(pc, ih);
1347 1.1 rh ess->ih = pci_intr_establish(pc, ih, IPL_AUDIO, esm_intr, self);
1348 1.1 rh if (ess->ih == NULL) {
1349 1.1 rh printf("%s: can't establish interrupt", ess->sc_dev.dv_xname);
1350 1.1 rh if (intrstr != NULL)
1351 1.1 rh printf(" at %s", intrstr);
1352 1.1 rh printf("\n");
1353 1.1 rh return;
1354 1.1 rh }
1355 1.1 rh printf("%s: interrupting at %s\n", ess->sc_dev.dv_xname, intrstr);
1356 1.1 rh
1357 1.1 rh /*
1358 1.1 rh * Setup PCI config registers
1359 1.1 rh */
1360 1.1 rh
1361 1.1 rh /* set to power state D0 */
1362 1.1 rh esm_power(ess, PPMI_D0);
1363 1.1 rh delay(100000);
1364 1.1 rh
1365 1.1 rh /* Disable all legacy emulations. */
1366 1.1 rh data = pci_conf_read(pc, tag, CONF_LEGACY);
1367 1.1 rh pci_conf_write(pc, tag, CONF_LEGACY, data | LEGACY_DISABLED);
1368 1.1 rh
1369 1.1 rh /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
1370 1.1 rh * Enable posted write.
1371 1.1 rh * Prefer PCI timing rather than that of ISA.
1372 1.1 rh * Don't swap L/R. */
1373 1.1 rh data = pci_conf_read(pc, tag, CONF_MAESTRO);
1374 1.1 rh data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
1375 1.1 rh data &= ~MAESTRO_SWAP_LR;
1376 1.1 rh pci_conf_write(pc, tag, CONF_MAESTRO, data);
1377 1.1 rh
1378 1.1 rh /* initialize sound chip */
1379 1.1 rh esm_init(ess);
1380 1.1 rh
1381 1.1 rh esm_read_codec(ess, 0, &codec_data);
1382 1.1 rh if (codec_data == 0x80) {
1383 1.1 rh printf("%s: PT101 codec detected!\n", ess->sc_dev.dv_xname);
1384 1.1 rh return;
1385 1.1 rh }
1386 1.1 rh
1387 1.3 rh /*
1388 1.3 rh * Some cards and Notebooks appear to have left and right channels
1389 1.3 rh * reversed. Check if there is a corresponding quirk entry for
1390 1.3 rh * the subsystem vendor and product and if so, set the appropriate
1391 1.3 rh * codec flag.
1392 1.3 rh */
1393 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_SWAPPEDCH) {
1394 1.3 rh ess->codec_flags |= AC97_HOST_SWAPPED_CHANNELS;
1395 1.3 rh }
1396 1.5 rh ess->codec_flags |= AC97_HOST_DONT_READ;
1397 1.3 rh
1398 1.1 rh /* initialize AC97 host interface */
1399 1.1 rh ess->host_if.arg = self;
1400 1.1 rh ess->host_if.attach = esm_attach_codec;
1401 1.1 rh ess->host_if.read = esm_read_codec;
1402 1.1 rh ess->host_if.write = esm_write_codec;
1403 1.1 rh ess->host_if.reset = esm_reset_codec;
1404 1.3 rh ess->host_if.flags = esm_flags_codec;
1405 1.1 rh
1406 1.1 rh if (ac97_attach(&ess->host_if) != 0)
1407 1.1 rh return;
1408 1.1 rh
1409 1.1 rh audio_attach_mi(&esm_hw_if, self, &ess->sc_dev);
1410 1.7 ichiro
1411 1.7 ichiro ess->esm_suspend = PWR_RESUME;
1412 1.7 ichiro ess->esm_powerhook = powerhook_establish(esm_powerhook, ess);
1413 1.7 ichiro }
1414 1.7 ichiro
1415 1.7 ichiro /* Power Hook */
1416 1.7 ichiro void
1417 1.7 ichiro esm_powerhook(why, v)
1418 1.7 ichiro int why;
1419 1.7 ichiro void *v;
1420 1.7 ichiro {
1421 1.7 ichiro struct esm_softc *ess = (struct esm_softc *)v;
1422 1.7 ichiro
1423 1.7 ichiro DPRINTF(ESM_DEBUG_PARAM,
1424 1.7 ichiro ("%s: ESS maestro 2E why=%d\n", ess->sc_dev.dv_xname, why));
1425 1.7 ichiro switch (why) {
1426 1.8 ichiro case PWR_SUSPEND:
1427 1.8 ichiro case PWR_STANDBY:
1428 1.8 ichiro ess->esm_suspend = why;
1429 1.8 ichiro esm_suspend(ess);
1430 1.9 rh DPRINTF(ESM_DEBUG_RESUME, ("esm_suspend\n"));
1431 1.8 ichiro break;
1432 1.8 ichiro
1433 1.7 ichiro case PWR_RESUME:
1434 1.7 ichiro ess->esm_suspend = why;
1435 1.8 ichiro esm_resume(ess);
1436 1.9 rh DPRINTF(ESM_DEBUG_RESUME, ("esm_resumed\n"));
1437 1.7 ichiro break;
1438 1.7 ichiro }
1439 1.1 rh }
1440 1.1 rh
1441 1.1 rh int
1442 1.1 rh esm_suspend(struct esm_softc *ess)
1443 1.1 rh {
1444 1.8 ichiro int x;
1445 1.1 rh
1446 1.1 rh x = splaudio();
1447 1.1 rh wp_stoptimer(ess);
1448 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1449 1.1 rh
1450 1.1 rh esm_halt_output(ess);
1451 1.1 rh esm_halt_input(ess);
1452 1.1 rh splx(x);
1453 1.1 rh
1454 1.1 rh /* Power down everything except clock. */
1455 1.1 rh esm_write_codec(ess, AC97_REG_POWER, 0xdf00);
1456 1.1 rh delay(20);
1457 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
1458 1.1 rh delay(1);
1459 1.1 rh esm_power(ess, PPMI_D3);
1460 1.1 rh
1461 1.1 rh return 0;
1462 1.1 rh }
1463 1.1 rh
1464 1.1 rh int
1465 1.1 rh esm_resume(struct esm_softc *ess)
1466 1.1 rh {
1467 1.8 ichiro int x;
1468 1.1 rh
1469 1.1 rh esm_power(ess, PPMI_D0);
1470 1.1 rh delay(100000);
1471 1.1 rh esm_init(ess);
1472 1.8 ichiro
1473 1.8 ichiro (*ess->codec_if->vtbl->restore_ports)(ess->codec_if);
1474 1.8 ichiro #if 0
1475 1.1 rh if (mixer_reinit(dev)) {
1476 1.1 rh printf("%s: unable to reinitialize the mixer\n",
1477 1.1 rh ess->sc_dev.dv_xname);
1478 1.1 rh return ENXIO;
1479 1.1 rh }
1480 1.8 ichiro #endif
1481 1.1 rh
1482 1.1 rh x = splaudio();
1483 1.8 ichiro #if TODO
1484 1.1 rh if (ess->pactive)
1485 1.1 rh esm_start_output(ess);
1486 1.1 rh if (ess->ractive)
1487 1.1 rh esm_start_input(ess);
1488 1.8 ichiro #endif
1489 1.1 rh if (ess->pactive || ess->ractive) {
1490 1.1 rh set_timer(ess);
1491 1.1 rh wp_starttimer(ess);
1492 1.1 rh }
1493 1.1 rh splx(x);
1494 1.1 rh return 0;
1495 1.1 rh }
1496 1.1 rh
1497 1.8 ichiro #if 0
1498 1.1 rh int
1499 1.1 rh esm_shutdown(struct esm_softc *ess)
1500 1.1 rh {
1501 1.1 rh int i;
1502 1.1 rh
1503 1.1 rh wp_stoptimer(ess);
1504 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1505 1.1 rh
1506 1.1 rh esm_halt_output(ess);
1507 1.1 rh esm_halt_input(ess);
1508 1.1 rh
1509 1.1 rh return 0;
1510 1.1 rh }
1511 1.1 rh #endif
1512