esm.c revision 1.18 1 1.18 fredette /* $NetBSD: esm.c,v 1.18 2002/12/30 05:23:27 fredette Exp $ */
2 1.1 rh
3 1.1 rh /*-
4 1.18 fredette * Copyright (c) 2002, 2003 Matt Fredette
5 1.18 fredette * All rights reserved.
6 1.18 fredette *
7 1.1 rh * Copyright (c) 2000, 2001 Rene Hexel <rh (at) netbsd.org>
8 1.1 rh * All rights reserved.
9 1.1 rh *
10 1.1 rh * Copyright (c) 2000 Taku YAMAMOTO <taku (at) cent.saitama-u.ac.jp>
11 1.1 rh * All rights reserved.
12 1.1 rh *
13 1.1 rh * Redistribution and use in source and binary forms, with or without
14 1.1 rh * modification, are permitted provided that the following conditions
15 1.1 rh * are met:
16 1.1 rh * 1. Redistributions of source code must retain the above copyright
17 1.1 rh * notice, this list of conditions and the following disclaimer.
18 1.1 rh * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 rh * notice, this list of conditions and the following disclaimer in the
20 1.1 rh * documentation and/or other materials provided with the distribution.
21 1.1 rh *
22 1.1 rh * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 1.1 rh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 rh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 rh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 1.1 rh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 rh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 rh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 rh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 rh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 rh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 rh * SUCH DAMAGE.
33 1.1 rh *
34 1.1 rh * Taku Id: maestro.c,v 1.12 2000/09/06 03:32:34 taku Exp
35 1.1 rh * FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.4 2000/12/18 01:36:35 cg Exp
36 1.1 rh */
37 1.1 rh
38 1.1 rh /*
39 1.1 rh * TODO:
40 1.1 rh * - hardware volume support
41 1.18 fredette * - fix 16-bit stereo recording, add 8-bit recording
42 1.1 rh * - MIDI support
43 1.1 rh * - joystick support
44 1.1 rh *
45 1.1 rh *
46 1.1 rh * Credits:
47 1.1 rh *
48 1.1 rh * This code is based on the FreeBSD driver written by Taku YAMAMOTO
49 1.1 rh *
50 1.1 rh *
51 1.1 rh * Original credits from the FreeBSD driver:
52 1.1 rh *
53 1.1 rh * Part of this code (especially in many magic numbers) was heavily inspired
54 1.1 rh * by the Linux driver originally written by
55 1.1 rh * Alan Cox <alan.cox (at) linux.org>, modified heavily by
56 1.1 rh * Zach Brown <zab (at) zabbo.net>.
57 1.1 rh *
58 1.1 rh * busdma()-ize and buffer size reduction were suggested by
59 1.1 rh * Cameron Grant <gandalf (at) vilnya.demon.co.uk>.
60 1.1 rh * Also he showed me the way to use busdma() suite.
61 1.1 rh *
62 1.1 rh * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
63 1.1 rh * were looked at by
64 1.1 rh * Munehiro Matsuda <haro (at) tk.kubota.co.jp>,
65 1.1 rh * who brought patches based on the Linux driver with some simplification.
66 1.1 rh */
67 1.12 lukem
68 1.12 lukem #include <sys/cdefs.h>
69 1.18 fredette __KERNEL_RCSID(0, "$NetBSD: esm.c,v 1.18 2002/12/30 05:23:27 fredette Exp $");
70 1.1 rh
71 1.1 rh #include <sys/param.h>
72 1.1 rh #include <sys/systm.h>
73 1.1 rh #include <sys/kernel.h>
74 1.1 rh #include <sys/malloc.h>
75 1.1 rh #include <sys/device.h>
76 1.1 rh
77 1.1 rh #include <machine/bus.h>
78 1.1 rh
79 1.1 rh #include <sys/audioio.h>
80 1.1 rh #include <dev/audio_if.h>
81 1.1 rh #include <dev/mulaw.h>
82 1.1 rh #include <dev/auconv.h>
83 1.1 rh #include <dev/ic/ac97var.h>
84 1.8 ichiro #include <dev/ic/ac97reg.h>
85 1.1 rh
86 1.1 rh #include <dev/pci/pcidevs.h>
87 1.1 rh #include <dev/pci/pcivar.h>
88 1.1 rh
89 1.1 rh #include <dev/pci/esmreg.h>
90 1.1 rh #include <dev/pci/esmvar.h>
91 1.1 rh
92 1.1 rh #define PCI_CBIO 0x10 /* Configuration Base I/O Address */
93 1.1 rh
94 1.1 rh /* Debug */
95 1.1 rh #ifdef AUDIO_DEBUG
96 1.1 rh #define DPRINTF(l,x) do { if (esm_debug & (l)) printf x; } while(0)
97 1.1 rh #define DUMPREG(x) do { if (esm_debug & ESM_DEBUG_REG) \
98 1.1 rh esm_dump_regs(x); } while(0)
99 1.1 rh int esm_debug = 0xfffc;
100 1.1 rh #define ESM_DEBUG_CODECIO 0x0001
101 1.1 rh #define ESM_DEBUG_IRQ 0x0002
102 1.1 rh #define ESM_DEBUG_DMA 0x0004
103 1.1 rh #define ESM_DEBUG_TIMER 0x0008
104 1.1 rh #define ESM_DEBUG_REG 0x0010
105 1.1 rh #define ESM_DEBUG_PARAM 0x0020
106 1.1 rh #define ESM_DEBUG_APU 0x0040
107 1.1 rh #define ESM_DEBUG_CODEC 0x0080
108 1.3 rh #define ESM_DEBUG_PCI 0x0100
109 1.8 ichiro #define ESM_DEBUG_RESUME 0x0200
110 1.1 rh #else
111 1.1 rh #define DPRINTF(x,y) /* nothing */
112 1.1 rh #define DUMPREG(x) /* nothing */
113 1.1 rh #endif
114 1.1 rh
115 1.1 rh #ifdef DIAGNOSTIC
116 1.1 rh #define RANGE(n, l, h) if ((n) < (l) || (n) >= (h)) \
117 1.1 rh printf (#n "=%d out of range (%d, %d) in " \
118 1.1 rh __FILE__ ", line %d\n", (n), (l), (h), __LINE__)
119 1.1 rh #else
120 1.1 rh #define RANGE(x,y,z) /* nothing */
121 1.1 rh #endif
122 1.1 rh
123 1.1 rh #define inline __inline
124 1.1 rh
125 1.1 rh static inline void ringbus_setdest(struct esm_softc *, int, int);
126 1.1 rh
127 1.1 rh static inline u_int16_t wp_rdreg(struct esm_softc *, u_int16_t);
128 1.1 rh static inline void wp_wrreg(struct esm_softc *, u_int16_t, u_int16_t);
129 1.1 rh static inline u_int16_t wp_rdapu(struct esm_softc *, int, u_int16_t);
130 1.1 rh static inline void wp_wrapu(struct esm_softc *, int, u_int16_t,
131 1.1 rh u_int16_t);
132 1.1 rh static inline void wp_settimer(struct esm_softc *, u_int);
133 1.1 rh static inline void wp_starttimer(struct esm_softc *);
134 1.1 rh static inline void wp_stoptimer(struct esm_softc *);
135 1.1 rh
136 1.1 rh static inline u_int16_t wc_rdreg(struct esm_softc *, u_int16_t);
137 1.1 rh static inline void wc_wrreg(struct esm_softc *, u_int16_t, u_int16_t);
138 1.1 rh static inline u_int16_t wc_rdchctl(struct esm_softc *, int);
139 1.1 rh static inline void wc_wrchctl(struct esm_softc *, int, u_int16_t);
140 1.1 rh
141 1.1 rh static inline u_int calc_timer_freq(struct esm_chinfo*);
142 1.1 rh static void set_timer(struct esm_softc *);
143 1.1 rh
144 1.1 rh static void esmch_set_format(struct esm_chinfo *,
145 1.1 rh struct audio_params *p);
146 1.18 fredette static void esmch_combine_input(struct esm_softc *,
147 1.18 fredette struct esm_chinfo *ch);
148 1.1 rh
149 1.7 ichiro /* Power Management */
150 1.7 ichiro void esm_powerhook(int, void *);
151 1.7 ichiro
152 1.15 thorpej CFATTACH_DECL(esm, sizeof(struct esm_softc),
153 1.16 thorpej esm_match, esm_attach, NULL, NULL);
154 1.1 rh
155 1.1 rh struct audio_hw_if esm_hw_if = {
156 1.1 rh esm_open,
157 1.1 rh esm_close,
158 1.1 rh NULL, /* drain */
159 1.1 rh esm_query_encoding,
160 1.1 rh esm_set_params,
161 1.1 rh esm_round_blocksize,
162 1.1 rh NULL, /* commit_settings */
163 1.1 rh esm_init_output,
164 1.18 fredette esm_init_input,
165 1.1 rh NULL, /* start_output */
166 1.1 rh NULL, /* start_input */
167 1.1 rh esm_halt_output,
168 1.1 rh esm_halt_input,
169 1.1 rh NULL, /* speaker_ctl */
170 1.1 rh esm_getdev,
171 1.1 rh NULL, /* getfd */
172 1.1 rh esm_set_port,
173 1.1 rh esm_get_port,
174 1.1 rh esm_query_devinfo,
175 1.1 rh esm_malloc,
176 1.1 rh esm_free,
177 1.1 rh esm_round_buffersize,
178 1.1 rh esm_mappage,
179 1.1 rh esm_get_props,
180 1.1 rh esm_trigger_output,
181 1.11 augustss esm_trigger_input,
182 1.11 augustss NULL,
183 1.1 rh };
184 1.1 rh
185 1.1 rh struct audio_device esm_device = {
186 1.1 rh "ESS Maestro",
187 1.1 rh "",
188 1.1 rh "esm"
189 1.1 rh };
190 1.1 rh
191 1.1 rh
192 1.1 rh static audio_encoding_t esm_encoding[] = {
193 1.1 rh { 0, AudioEulinear, AUDIO_ENCODING_ULINEAR, 8, 0 },
194 1.1 rh { 1, AudioEmulaw, AUDIO_ENCODING_ULAW, 8,
195 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
196 1.1 rh { 2, AudioEalaw, AUDIO_ENCODING_ALAW, 8, AUDIO_ENCODINGFLAG_EMULATED },
197 1.1 rh { 3, AudioEslinear, AUDIO_ENCODING_SLINEAR, 8, 0 },
198 1.1 rh { 4, AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 16, 0 },
199 1.1 rh { 5, AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 16,
200 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
201 1.1 rh { 6, AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 16,
202 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
203 1.1 rh { 7, AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 16,
204 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
205 1.1 rh };
206 1.1 rh
207 1.1 rh #define MAESTRO_NENCODINGS 8
208 1.1 rh
209 1.3 rh
210 1.3 rh static const struct esm_quirks esm_quirks[] = {
211 1.3 rh /* COMPAL 38W2 OEM Notebook, e.g. Dell INSPIRON 5000e */
212 1.3 rh { PCI_VENDOR_COMPAL, PCI_PRODUCT_COMPAL_38W2, ESM_QUIRKF_SWAPPEDCH },
213 1.3 rh
214 1.5 rh /* COMPAQ Armada M700 Notebook */
215 1.5 rh { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_M700, ESM_QUIRKF_SWAPPEDCH },
216 1.5 rh
217 1.3 rh /* NEC Versa Pro LX VA26D */
218 1.3 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VA26D, ESM_QUIRKF_GPIO },
219 1.3 rh
220 1.3 rh /* NEC Versa LX */
221 1.6 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSALX, ESM_QUIRKF_GPIO },
222 1.6 rh
223 1.10 simonb /* Toshiba Portege */
224 1.10 simonb { PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_PORTEGE, ESM_QUIRKF_SWAPPEDCH }
225 1.3 rh };
226 1.3 rh
227 1.3 rh enum esm_quirk_flags
228 1.3 rh esm_get_quirks(pcireg_t subid)
229 1.3 rh {
230 1.3 rh int i;
231 1.3 rh
232 1.3 rh for (i = 0; i < (sizeof esm_quirks / sizeof esm_quirks[0]); i++) {
233 1.3 rh if (PCI_VENDOR(subid) == esm_quirks[i].eq_vendor &&
234 1.3 rh PCI_PRODUCT(subid) == esm_quirks[i].eq_product) {
235 1.3 rh return esm_quirks[i].eq_quirks;
236 1.3 rh }
237 1.3 rh }
238 1.3 rh
239 1.3 rh return 0;
240 1.3 rh }
241 1.3 rh
242 1.3 rh
243 1.1 rh #ifdef AUDIO_DEBUG
244 1.1 rh struct esm_reg_info {
245 1.1 rh int offset; /* register offset */
246 1.1 rh int width; /* 1/2/4 bytes */
247 1.1 rh } dump_regs[] = {
248 1.1 rh { PORT_WAVCACHE_CTRL, 2 },
249 1.1 rh { PORT_HOSTINT_CTRL, 2 },
250 1.1 rh { PORT_HOSTINT_STAT, 2 },
251 1.1 rh { PORT_HWVOL_VOICE_SHADOW, 1 },
252 1.1 rh { PORT_HWVOL_VOICE, 1 },
253 1.1 rh { PORT_HWVOL_MASTER_SHADOW, 1 },
254 1.1 rh { PORT_HWVOL_MASTER, 1 },
255 1.1 rh { PORT_RINGBUS_CTRL, 4 },
256 1.1 rh { PORT_GPIO_DATA, 2 },
257 1.1 rh { PORT_GPIO_MASK, 2 },
258 1.1 rh { PORT_GPIO_DIR, 2 },
259 1.1 rh { PORT_ASSP_CTRL_A, 1 },
260 1.1 rh { PORT_ASSP_CTRL_B, 1 },
261 1.1 rh { PORT_ASSP_CTRL_C, 1 },
262 1.3 rh { PORT_ASSP_INT_STAT, 1 }
263 1.1 rh };
264 1.1 rh
265 1.2 lukem static void
266 1.2 lukem esm_dump_regs(struct esm_softc *ess)
267 1.1 rh {
268 1.3 rh int i;
269 1.1 rh
270 1.1 rh printf("%s registers:", ess->sc_dev.dv_xname);
271 1.3 rh for (i = 0; i < (sizeof dump_regs / sizeof dump_regs[0]); i++) {
272 1.1 rh if (i % 5 == 0)
273 1.1 rh printf("\n");
274 1.1 rh printf("0x%2.2x: ", dump_regs[i].offset);
275 1.1 rh switch(dump_regs[i].width) {
276 1.1 rh case 4:
277 1.1 rh printf("%8.8x, ", bus_space_read_4(ess->st, ess->sh,
278 1.1 rh dump_regs[i].offset));
279 1.1 rh break;
280 1.1 rh case 2:
281 1.1 rh printf("%4.4x, ", bus_space_read_2(ess->st, ess->sh,
282 1.1 rh dump_regs[i].offset));
283 1.1 rh break;
284 1.1 rh default:
285 1.1 rh printf("%2.2x, ",
286 1.1 rh bus_space_read_1(ess->st, ess->sh,
287 1.1 rh dump_regs[i].offset));
288 1.1 rh }
289 1.1 rh }
290 1.1 rh printf("\n");
291 1.1 rh }
292 1.1 rh #endif
293 1.1 rh
294 1.3 rh
295 1.1 rh /* -----------------------------
296 1.1 rh * Subsystems.
297 1.1 rh */
298 1.1 rh
299 1.1 rh /* Codec/Ringbus */
300 1.1 rh
301 1.1 rh /* -------------------------------------------------------------------- */
302 1.1 rh
303 1.1 rh int
304 1.1 rh esm_read_codec(void *sc, u_int8_t regno, u_int16_t *result)
305 1.1 rh {
306 1.1 rh struct esm_softc *ess = sc;
307 1.1 rh unsigned t;
308 1.1 rh
309 1.1 rh /* We have to wait for a SAFE time to write addr/data */
310 1.1 rh for (t = 0; t < 20; t++) {
311 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
312 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
313 1.1 rh break;
314 1.1 rh delay(2); /* 20.8us / 13 */
315 1.1 rh }
316 1.1 rh if (t == 20)
317 1.1 rh printf("%s: esm_read_codec() PROGLESS timed out.\n",
318 1.1 rh ess->sc_dev.dv_xname);
319 1.1 rh
320 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
321 1.1 rh CODEC_CMD_READ | regno);
322 1.1 rh delay(21); /* AC97 cycle = 20.8usec */
323 1.1 rh
324 1.1 rh /* Wait for data retrieve */
325 1.1 rh for (t = 0; t < 20; t++) {
326 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
327 1.1 rh & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE)
328 1.1 rh break;
329 1.1 rh delay(2); /* 20.8us / 13 */
330 1.1 rh }
331 1.1 rh if (t == 20)
332 1.1 rh /* Timed out, but perform dummy read. */
333 1.1 rh printf("%s: esm_read_codec() RW_DONE timed out.\n",
334 1.1 rh ess->sc_dev.dv_xname);
335 1.1 rh
336 1.1 rh *result = bus_space_read_2(ess->st, ess->sh, PORT_CODEC_REG);
337 1.1 rh
338 1.1 rh return 0;
339 1.1 rh }
340 1.1 rh
341 1.1 rh int
342 1.1 rh esm_write_codec(void *sc, u_int8_t regno, u_int16_t data)
343 1.1 rh {
344 1.1 rh struct esm_softc *ess = sc;
345 1.1 rh unsigned t;
346 1.1 rh
347 1.1 rh /* We have to wait for a SAFE time to write addr/data */
348 1.1 rh for (t = 0; t < 20; t++) {
349 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
350 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
351 1.1 rh break;
352 1.1 rh delay(2); /* 20.8us / 13 */
353 1.1 rh }
354 1.1 rh if (t == 20) {
355 1.1 rh /* Timed out. Abort writing. */
356 1.1 rh printf("%s: esm_write_codec() PROGLESS timed out.\n",
357 1.1 rh ess->sc_dev.dv_xname);
358 1.1 rh return -1;
359 1.1 rh }
360 1.1 rh
361 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_CODEC_REG, data);
362 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
363 1.1 rh CODEC_CMD_WRITE | regno);
364 1.1 rh
365 1.1 rh return 0;
366 1.1 rh }
367 1.1 rh
368 1.1 rh /* -------------------------------------------------------------------- */
369 1.1 rh
370 1.1 rh static inline void
371 1.1 rh ringbus_setdest(struct esm_softc *ess, int src, int dest)
372 1.1 rh {
373 1.1 rh u_int32_t data;
374 1.1 rh
375 1.1 rh data = bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL);
376 1.1 rh data &= ~(0xfU << src);
377 1.1 rh data |= (0xfU & dest) << src;
378 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, data);
379 1.1 rh }
380 1.1 rh
381 1.1 rh /* Wave Processor */
382 1.1 rh
383 1.1 rh static inline u_int16_t
384 1.1 rh wp_rdreg(struct esm_softc *ess, u_int16_t reg)
385 1.1 rh {
386 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
387 1.1 rh return bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA);
388 1.1 rh }
389 1.1 rh
390 1.1 rh static inline void
391 1.1 rh wp_wrreg(struct esm_softc *ess, u_int16_t reg, u_int16_t data)
392 1.1 rh {
393 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
394 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
395 1.1 rh }
396 1.1 rh
397 1.1 rh static inline void
398 1.1 rh apu_setindex(struct esm_softc *ess, u_int16_t reg)
399 1.1 rh {
400 1.1 rh int t;
401 1.1 rh
402 1.1 rh wp_wrreg(ess, WPREG_CRAM_PTR, reg);
403 1.1 rh /* Sometimes WP fails to set apu register index. */
404 1.1 rh for (t = 0; t < 1000; t++) {
405 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == reg)
406 1.1 rh break;
407 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, reg);
408 1.1 rh }
409 1.1 rh if (t == 1000)
410 1.1 rh printf("%s: apu_setindex() timed out.\n", ess->sc_dev.dv_xname);
411 1.1 rh }
412 1.1 rh
413 1.1 rh static inline u_int16_t
414 1.1 rh wp_rdapu(struct esm_softc *ess, int ch, u_int16_t reg)
415 1.1 rh {
416 1.1 rh u_int16_t ret;
417 1.1 rh
418 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg);
419 1.1 rh ret = wp_rdreg(ess, WPREG_DATA_PORT);
420 1.1 rh return ret;
421 1.1 rh }
422 1.1 rh
423 1.1 rh static inline void
424 1.1 rh wp_wrapu(struct esm_softc *ess, int ch, u_int16_t reg, u_int16_t data)
425 1.1 rh {
426 1.1 rh int t;
427 1.1 rh
428 1.1 rh DPRINTF(ESM_DEBUG_APU,
429 1.1 rh ("wp_wrapu(%p, ch=%d, reg=0x%x, data=0x%04x)\n",
430 1.1 rh ess, ch, reg, data));
431 1.1 rh
432 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg);
433 1.1 rh wp_wrreg(ess, WPREG_DATA_PORT, data);
434 1.1 rh for (t = 0; t < 1000; t++) {
435 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == data)
436 1.1 rh break;
437 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
438 1.1 rh }
439 1.1 rh if (t == 1000)
440 1.1 rh printf("%s: wp_wrapu() timed out.\n", ess->sc_dev.dv_xname);
441 1.1 rh }
442 1.1 rh
443 1.1 rh static inline void
444 1.1 rh wp_settimer(struct esm_softc *ess, u_int freq)
445 1.1 rh {
446 1.1 rh u_int clock = 48000 << 2;
447 1.1 rh u_int prescale = 0, divide = (freq != 0) ? (clock / freq) : ~0;
448 1.1 rh
449 1.1 rh RANGE(divide, WPTIMER_MINDIV, WPTIMER_MAXDIV);
450 1.1 rh
451 1.1 rh for (; divide > 32 << 1; divide >>= 1)
452 1.1 rh prescale++;
453 1.1 rh divide = (divide + 1) >> 1;
454 1.1 rh
455 1.1 rh for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
456 1.1 rh prescale++;
457 1.1 rh
458 1.1 rh DPRINTF(ESM_DEBUG_TIMER,
459 1.1 rh ("wp_settimer(%p, %u): clock = %u, prescale = %u, divide = %u\n",
460 1.1 rh ess, freq, clock, prescale, divide));
461 1.1 rh
462 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
463 1.1 rh wp_wrreg(ess, WPREG_TIMER_FREQ,
464 1.1 rh (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
465 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
466 1.1 rh }
467 1.1 rh
468 1.1 rh static inline void
469 1.1 rh wp_starttimer(struct esm_softc *ess)
470 1.1 rh {
471 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 1);
472 1.1 rh }
473 1.1 rh
474 1.1 rh static inline void
475 1.1 rh wp_stoptimer(struct esm_softc *ess)
476 1.1 rh {
477 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 0);
478 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
479 1.1 rh }
480 1.1 rh
481 1.1 rh /* WaveCache */
482 1.1 rh
483 1.1 rh static inline u_int16_t
484 1.1 rh wc_rdreg(struct esm_softc *ess, u_int16_t reg)
485 1.1 rh {
486 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
487 1.1 rh return bus_space_read_2(ess->st, ess->sh, PORT_WAVCACHE_DATA);
488 1.1 rh }
489 1.1 rh
490 1.1 rh static inline void
491 1.1 rh wc_wrreg(struct esm_softc *ess, u_int16_t reg, u_int16_t data)
492 1.1 rh {
493 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
494 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_DATA, data);
495 1.1 rh }
496 1.1 rh
497 1.1 rh static inline u_int16_t
498 1.1 rh wc_rdchctl(struct esm_softc *ess, int ch)
499 1.1 rh {
500 1.1 rh return wc_rdreg(ess, ch << 3);
501 1.1 rh }
502 1.1 rh
503 1.1 rh static inline void
504 1.1 rh wc_wrchctl(struct esm_softc *ess, int ch, u_int16_t data)
505 1.1 rh {
506 1.1 rh wc_wrreg(ess, ch << 3, data);
507 1.1 rh }
508 1.1 rh
509 1.1 rh /* Power management */
510 1.1 rh
511 1.1 rh void
512 1.1 rh esm_power(struct esm_softc *ess, int status)
513 1.1 rh {
514 1.13 pooka pcireg_t data;
515 1.13 pooka int pmcapreg;
516 1.1 rh
517 1.13 pooka if (pci_get_capability(ess->pc, ess->tag, PCI_CAP_PWRMGMT,
518 1.13 pooka &pmcapreg, 0)) {
519 1.17 tsutsui data = pci_conf_read(ess->pc, ess->tag, pmcapreg + PCI_PMCSR);
520 1.13 pooka if ((data && PCI_PMCSR_STATE_MASK) != status)
521 1.17 tsutsui pci_conf_write(ess->pc, ess->tag,
522 1.17 tsutsui pmcapreg + PCI_PMCSR, status);
523 1.13 pooka }
524 1.1 rh }
525 1.1 rh
526 1.1 rh
527 1.1 rh /* -----------------------------
528 1.1 rh * Controller.
529 1.1 rh */
530 1.1 rh
531 1.1 rh int
532 1.1 rh esm_attach_codec(void *sc, struct ac97_codec_if *codec_if)
533 1.1 rh {
534 1.1 rh struct esm_softc *ess = sc;
535 1.1 rh
536 1.1 rh ess->codec_if = codec_if;
537 1.1 rh
538 1.1 rh return 0;
539 1.1 rh }
540 1.1 rh
541 1.1 rh void
542 1.1 rh esm_reset_codec(void *sc)
543 1.1 rh {
544 1.1 rh }
545 1.1 rh
546 1.1 rh
547 1.3 rh enum ac97_host_flags
548 1.3 rh esm_flags_codec(void *sc)
549 1.3 rh {
550 1.3 rh struct esm_softc *ess = sc;
551 1.3 rh
552 1.3 rh return ess->codec_flags;
553 1.3 rh }
554 1.3 rh
555 1.3 rh
556 1.1 rh void
557 1.1 rh esm_initcodec(struct esm_softc *ess)
558 1.1 rh {
559 1.1 rh u_int16_t data;
560 1.1 rh
561 1.1 rh DPRINTF(ESM_DEBUG_CODEC, ("esm_initcodec(%p)\n", ess));
562 1.1 rh
563 1.1 rh if (bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL)
564 1.1 rh & RINGBUS_CTRL_ACLINK_ENABLED) {
565 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
566 1.1 rh delay(104); /* 20.8us * (4 + 1) */
567 1.1 rh }
568 1.1 rh /* XXX - 2nd codec should be looked at. */
569 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
570 1.1 rh RINGBUS_CTRL_AC97_SWRESET);
571 1.1 rh delay(2);
572 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
573 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED);
574 1.1 rh delay(21);
575 1.1 rh
576 1.1 rh esm_read_codec(ess, 0, &data);
577 1.1 rh if (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
578 1.1 rh & CODEC_STAT_MASK) {
579 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
580 1.1 rh delay(21);
581 1.1 rh
582 1.1 rh /* Try cold reset. */
583 1.1 rh printf("%s: will perform cold reset.\n", ess->sc_dev.dv_xname);
584 1.1 rh data = bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR);
585 1.1 rh if (pci_conf_read(ess->pc, ess->tag, 0x58) & 1)
586 1.1 rh data |= 0x10;
587 1.1 rh data |= 0x009 &
588 1.1 rh ~bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DATA);
589 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0xff6);
590 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
591 1.1 rh data | 0x009);
592 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x000);
593 1.1 rh delay(2);
594 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x001);
595 1.1 rh delay(1);
596 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x009);
597 1.1 rh delay(500000);
598 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, data);
599 1.1 rh delay(84); /* 20.8us * 4 */
600 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
601 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED);
602 1.1 rh delay(21);
603 1.1 rh }
604 1.1 rh }
605 1.1 rh
606 1.1 rh void
607 1.1 rh esm_init(struct esm_softc *ess)
608 1.1 rh {
609 1.1 rh /* Reset direct sound. */
610 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
611 1.1 rh HOSTINT_CTRL_DSOUND_RESET);
612 1.1 rh delay(10000);
613 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
614 1.1 rh delay(10000);
615 1.1 rh
616 1.1 rh /* Enable direct sound interruption. */
617 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
618 1.1 rh HOSTINT_CTRL_DSOUND_INT_ENABLED);
619 1.1 rh
620 1.1 rh /* Setup Wave Processor. */
621 1.1 rh
622 1.1 rh /* Enable WaveCache */
623 1.1 rh wp_wrreg(ess, WPREG_WAVE_ROMRAM,
624 1.1 rh WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
625 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_CTRL,
626 1.1 rh WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB);
627 1.1 rh
628 1.1 rh /* Setup Codec/Ringbus. */
629 1.1 rh esm_initcodec(ess);
630 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
631 1.1 rh RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED);
632 1.1 rh
633 1.18 fredette /* Undocumented registers from the Linux driver. */
634 1.18 fredette wp_wrreg(ess, 0x8, 0xB004);
635 1.18 fredette wp_wrreg(ess, 0x9, 0x001B);
636 1.18 fredette wp_wrreg(ess, 0xA, 0x8000);
637 1.18 fredette wp_wrreg(ess, 0xB, 0x3F37);
638 1.18 fredette wp_wrreg(ess, 0xD, 0x7632);
639 1.18 fredette
640 1.18 fredette wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
641 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_ADC,
642 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
643 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
644 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
645 1.1 rh
646 1.1 rh /* Setup ASSP. Needed for Dell Inspiron 7500? */
647 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_B, 0x00);
648 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_A, 0x03);
649 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_C, 0x00);
650 1.1 rh
651 1.1 rh /*
652 1.1 rh * Setup GPIO.
653 1.1 rh * There seems to be speciality with NEC systems.
654 1.1 rh */
655 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_GPIO) {
656 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK,
657 1.3 rh 0x9ff);
658 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
659 1.3 rh bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR) |
660 1.3 rh 0x600);
661 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA,
662 1.3 rh 0x200);
663 1.1 rh }
664 1.1 rh
665 1.1 rh DUMPREG(ess);
666 1.1 rh }
667 1.1 rh
668 1.1 rh
669 1.1 rh /* Channel controller. */
670 1.1 rh
671 1.1 rh int
672 1.1 rh esm_init_output (void *sc, void *start, int size)
673 1.1 rh {
674 1.1 rh struct esm_softc *ess = sc;
675 1.1 rh struct esm_dma *p;
676 1.1 rh
677 1.18 fredette p = &ess->sc_dma;
678 1.18 fredette if ((caddr_t)start != p->addr + MAESTRO_PLAYBUF_OFF) {
679 1.1 rh printf("%s: esm_init_output: bad addr %p\n",
680 1.1 rh ess->sc_dev.dv_xname, start);
681 1.1 rh return EINVAL;
682 1.1 rh }
683 1.1 rh
684 1.18 fredette ess->pch.base = DMAADDR(p) + MAESTRO_PLAYBUF_OFF;
685 1.1 rh
686 1.1 rh DPRINTF(ESM_DEBUG_DMA, ("%s: pch.base = 0x%x\n",
687 1.1 rh ess->sc_dev.dv_xname, ess->pch.base));
688 1.1 rh
689 1.18 fredette return 0;
690 1.18 fredette }
691 1.18 fredette
692 1.18 fredette int
693 1.18 fredette esm_init_input (void *sc, void *start, int size)
694 1.18 fredette {
695 1.18 fredette struct esm_softc *ess = sc;
696 1.18 fredette struct esm_dma *p;
697 1.18 fredette
698 1.18 fredette p = &ess->sc_dma;
699 1.18 fredette if ((caddr_t)start != p->addr + MAESTRO_RECBUF_OFF) {
700 1.18 fredette printf("%s: esm_init_input: bad addr %p\n",
701 1.18 fredette ess->sc_dev.dv_xname, start);
702 1.18 fredette return EINVAL;
703 1.18 fredette }
704 1.18 fredette
705 1.18 fredette switch (ess->rch.aputype) {
706 1.18 fredette case APUTYPE_16BITSTEREO:
707 1.18 fredette ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_L_OFF;
708 1.18 fredette break;
709 1.18 fredette default:
710 1.18 fredette ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_OFF;
711 1.18 fredette break;
712 1.18 fredette }
713 1.18 fredette
714 1.18 fredette DPRINTF(ESM_DEBUG_DMA, ("%s: rch.base = 0x%x\n",
715 1.18 fredette ess->sc_dev.dv_xname, ess->rch.base));
716 1.1 rh
717 1.1 rh return 0;
718 1.1 rh }
719 1.1 rh
720 1.1 rh int
721 1.1 rh esm_trigger_output(void *sc, void *start, void *end, int blksize,
722 1.1 rh void (*intr)(void *), void *arg, struct audio_params *param)
723 1.1 rh {
724 1.1 rh struct esm_softc *ess = sc;
725 1.1 rh struct esm_chinfo *ch = &ess->pch;
726 1.1 rh struct esm_dma *p;
727 1.1 rh int pan = 0, choffset;
728 1.3 rh int i, nch = 1;
729 1.1 rh unsigned speed = ch->sample_rate, offset, wpwa, dv;
730 1.1 rh size_t size;
731 1.1 rh u_int16_t apuch = ch->num << 1;
732 1.1 rh
733 1.1 rh DPRINTF(ESM_DEBUG_DMA,
734 1.1 rh ("esm_trigger_output(%p, %p, %p, 0x%x, %p, %p, %p)\n",
735 1.1 rh sc, start, end, blksize, intr, arg, param));
736 1.1 rh
737 1.1 rh #ifdef DIAGNOSTIC
738 1.1 rh if (ess->pactive) {
739 1.1 rh printf("%s: esm_trigger_output: already running",
740 1.1 rh ess->sc_dev.dv_xname);
741 1.1 rh return EINVAL;
742 1.1 rh }
743 1.1 rh #endif
744 1.1 rh
745 1.1 rh ess->sc_pintr = intr;
746 1.1 rh ess->sc_parg = arg;
747 1.18 fredette p = &ess->sc_dma;
748 1.18 fredette if ((caddr_t)start != p->addr + MAESTRO_PLAYBUF_OFF) {
749 1.1 rh printf("%s: esm_trigger_output: bad addr %p\n",
750 1.1 rh ess->sc_dev.dv_xname, start);
751 1.1 rh return EINVAL;
752 1.1 rh }
753 1.1 rh
754 1.1 rh ess->pch.blocksize = blksize;
755 1.1 rh ess->pch.apublk = blksize >> 1;
756 1.1 rh ess->pactive = 1;
757 1.1 rh
758 1.1 rh size = (size_t)(((caddr_t)end - (caddr_t)start) >> 1);
759 1.18 fredette choffset = MAESTRO_PLAYBUF_OFF;
760 1.1 rh offset = choffset >> 1;
761 1.18 fredette wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK);
762 1.1 rh
763 1.1 rh DPRINTF(ESM_DEBUG_DMA,
764 1.1 rh ("choffs=0x%x, wpwa=0x%x, size=0x%x words\n",
765 1.1 rh choffset, wpwa, size));
766 1.1 rh
767 1.1 rh switch (ch->aputype) {
768 1.1 rh case APUTYPE_16BITSTEREO:
769 1.1 rh ess->pch.apublk >>= 1;
770 1.1 rh wpwa >>= 1;
771 1.1 rh size >>= 1;
772 1.1 rh offset >>= 1;
773 1.1 rh /* FALLTHROUGH */
774 1.1 rh case APUTYPE_8BITSTEREO:
775 1.3 rh if (ess->codec_flags & AC97_HOST_SWAPPED_CHANNELS)
776 1.3 rh pan = 8;
777 1.3 rh else
778 1.3 rh pan = -8;
779 1.3 rh nch++;
780 1.1 rh break;
781 1.1 rh case APUTYPE_8BITLINEAR:
782 1.1 rh ess->pch.apublk <<= 1;
783 1.1 rh speed >>= 1;
784 1.1 rh break;
785 1.1 rh }
786 1.1 rh
787 1.18 fredette ess->pch.apubase = offset;
788 1.1 rh ess->pch.apubuf = size;
789 1.1 rh ess->pch.nextirq = ess->pch.apublk;
790 1.1 rh
791 1.1 rh set_timer(ess);
792 1.1 rh wp_starttimer(ess);
793 1.1 rh
794 1.1 rh dv = (((speed % 48000) << 16) + 24000) / 48000
795 1.1 rh + ((speed / 48000) << 16);
796 1.1 rh
797 1.3 rh for (i = nch-1; i >= 0; i--) {
798 1.3 rh wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa & 0xff00);
799 1.3 rh wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset);
800 1.3 rh wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size);
801 1.3 rh wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1);
802 1.3 rh wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800);
803 1.3 rh wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00
804 1.1 rh | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
805 1.1 rh | ((PAN_FRONT + pan) << APU_PAN_SHIFT));
806 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB
807 1.1 rh | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
808 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8);
809 1.1 rh
810 1.1 rh if (ch->aputype == APUTYPE_16BITSTEREO)
811 1.1 rh wpwa |= APU_STEREO >> 1;
812 1.1 rh pan = -pan;
813 1.3 rh }
814 1.1 rh
815 1.1 rh wc_wrchctl(ess, apuch, ch->wcreg_tpl);
816 1.3 rh if (nch > 1)
817 1.3 rh wc_wrchctl(ess, apuch + 1, ch->wcreg_tpl);
818 1.1 rh
819 1.1 rh wp_wrapu(ess, apuch, APUREG_APUTYPE,
820 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
821 1.1 rh if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO)
822 1.1 rh wp_wrapu(ess, apuch + 1, APUREG_APUTYPE,
823 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
824 1.1 rh
825 1.1 rh return 0;
826 1.1 rh }
827 1.1 rh
828 1.1 rh
829 1.1 rh int
830 1.1 rh esm_trigger_input(void *sc, void *start, void *end, int blksize,
831 1.1 rh void (*intr)(void *), void *arg, struct audio_params *param)
832 1.1 rh {
833 1.18 fredette struct esm_softc *ess = sc;
834 1.18 fredette struct esm_chinfo *ch = &ess->rch;
835 1.18 fredette struct esm_dma *p;
836 1.18 fredette u_int32_t chctl, choffset;
837 1.18 fredette int i, nch = 1;
838 1.18 fredette u_int32_t speed = ch->sample_rate, offset, wpwa, dv;
839 1.18 fredette size_t size;
840 1.18 fredette u_int16_t apuch = ch->num << 1;
841 1.18 fredette u_int32_t mixoffset, mixdv;
842 1.18 fredette size_t mixsize;
843 1.18 fredette u_int16_t reg;
844 1.18 fredette
845 1.18 fredette DPRINTF(ESM_DEBUG_DMA,
846 1.18 fredette ("esm_trigger_input(%p, %p, %p, 0x%x, %p, %p, %p)\n",
847 1.18 fredette sc, start, end, blksize, intr, arg, param));
848 1.18 fredette
849 1.18 fredette #ifdef DIAGNOSTIC
850 1.18 fredette if (ess->ractive) {
851 1.18 fredette printf("%s: esm_trigger_input: already running",
852 1.18 fredette ess->sc_dev.dv_xname);
853 1.18 fredette return EINVAL;
854 1.18 fredette }
855 1.18 fredette #endif
856 1.18 fredette
857 1.18 fredette ess->sc_rintr = intr;
858 1.18 fredette ess->sc_rarg = arg;
859 1.18 fredette p = &ess->sc_dma;
860 1.18 fredette if ((caddr_t)start != p->addr + MAESTRO_RECBUF_OFF) {
861 1.18 fredette printf("%s: esm_trigger_input: bad addr %p\n",
862 1.18 fredette ess->sc_dev.dv_xname, start);
863 1.18 fredette return EINVAL;
864 1.18 fredette }
865 1.18 fredette
866 1.18 fredette ess->rch.buffer = (caddr_t)start;
867 1.18 fredette ess->rch.offset = 0;
868 1.18 fredette ess->rch.blocksize = blksize;
869 1.18 fredette ess->rch.bufsize = ((caddr_t)end - (caddr_t)start);
870 1.18 fredette ess->rch.apublk = blksize >> 1;
871 1.18 fredette ess->ractive = 1;
872 1.18 fredette
873 1.18 fredette size = (size_t)(((caddr_t)end - (caddr_t)start) >> 1);
874 1.18 fredette choffset = MAESTRO_RECBUF_OFF;
875 1.18 fredette switch (ch->aputype) {
876 1.18 fredette case APUTYPE_16BITSTEREO:
877 1.18 fredette size >>= 1;
878 1.18 fredette choffset = MAESTRO_RECBUF_L_OFF;
879 1.18 fredette ess->rch.apublk >>= 1;
880 1.18 fredette nch++;
881 1.18 fredette break;
882 1.18 fredette case APUTYPE_16BITLINEAR:
883 1.18 fredette break;
884 1.18 fredette default:
885 1.18 fredette ess->ractive = 0;
886 1.18 fredette return EINVAL;
887 1.18 fredette }
888 1.18 fredette
889 1.18 fredette mixsize = (MAESTRO_MIXBUF_SZ >> 1) >> 1;
890 1.18 fredette mixoffset = MAESTRO_MIXBUF_OFF;
891 1.18 fredette
892 1.18 fredette ess->rch.apubase = (choffset >> 1);
893 1.18 fredette ess->rch.apubuf = size;
894 1.18 fredette ess->rch.nextirq = ess->rch.apublk;
895 1.18 fredette
896 1.18 fredette set_timer(ess);
897 1.18 fredette wp_starttimer(ess);
898 1.18 fredette
899 1.18 fredette if (speed > 47999) speed = 47999;
900 1.18 fredette if (speed < 4000) speed = 4000;
901 1.18 fredette dv = (((speed % 48000) << 16) + 24000) / 48000
902 1.18 fredette + ((speed / 48000) << 16);
903 1.18 fredette mixdv = 65536; /* 48KHz */
904 1.18 fredette
905 1.18 fredette for (i = 0; i < nch; i++) {
906 1.18 fredette
907 1.18 fredette /* Clear all rate conversion WP channel registers first. */
908 1.18 fredette for (reg = 0; reg < 15; reg++)
909 1.18 fredette wp_wrapu(ess, apuch + i, reg, 0);
910 1.18 fredette
911 1.18 fredette /* Program the WaveCache for the rate conversion WP channel. */
912 1.18 fredette chctl = (DMAADDR(p) + choffset - 0x10) &
913 1.18 fredette WAVCACHE_CHCTL_ADDRTAG_MASK;
914 1.18 fredette wc_wrchctl(ess, apuch + i, chctl);
915 1.18 fredette
916 1.18 fredette /* Program the rate conversion WP channel. */
917 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB
918 1.18 fredette | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT) | 0x08);
919 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8);
920 1.18 fredette offset = choffset >> 1;
921 1.18 fredette wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK);
922 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa);
923 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset);
924 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size);
925 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1);
926 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_EFFECTS_ENV, 0x00f0);
927 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800);
928 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00
929 1.18 fredette | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
930 1.18 fredette | (PAN_FRONT << APU_PAN_SHIFT));
931 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_ROUTE, apuch + 2 + i);
932 1.18 fredette
933 1.18 fredette DPRINTF(ESM_DEBUG_DMA,
934 1.18 fredette ("choffs=0x%x, wpwa=0x%x, offset=0x%x words, size=0x%x words\n",
935 1.18 fredette choffset, wpwa, offset, size));
936 1.18 fredette
937 1.18 fredette /* Clear all mixer WP channel registers first. */
938 1.18 fredette for (reg = 0; reg < 15; reg++)
939 1.18 fredette wp_wrapu(ess, apuch + 2 + i, reg, 0);
940 1.18 fredette
941 1.18 fredette /* Program the WaveCache for the mixer WP channel. */
942 1.18 fredette chctl = (ess->rch.base + mixoffset - 0x10) &
943 1.18 fredette WAVCACHE_CHCTL_ADDRTAG_MASK;
944 1.18 fredette wc_wrchctl(ess, apuch + 2 + i, chctl);
945 1.18 fredette
946 1.18 fredette /* Program the mixer WP channel. */
947 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_FREQ_LOBYTE, APU_plus6dB
948 1.18 fredette | ((mixdv & 0xff) << APU_FREQ_LOBYTE_SHIFT) | 0x08);
949 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_FREQ_HIWORD, mixdv >> 8);
950 1.18 fredette offset = mixoffset >> 1;
951 1.18 fredette wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK);
952 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_WAVESPACE, wpwa);
953 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_CURPTR, offset);
954 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_ENDPTR,
955 1.18 fredette offset + mixsize);
956 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_LOOPLEN, mixsize);
957 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_EFFECTS_ENV, 0x00f0);
958 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_AMPLITUDE, 0xe800);
959 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_POSITION, 0x8f00
960 1.18 fredette | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
961 1.18 fredette | (PAN_FRONT << APU_PAN_SHIFT));
962 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_ROUTE,
963 1.18 fredette ROUTE_PARALLEL + i);
964 1.18 fredette
965 1.18 fredette DPRINTF(ESM_DEBUG_DMA,
966 1.18 fredette ("mixoffs=0x%x, wpwa=0x%x, offset=0x%x words, size=0x%x words\n",
967 1.18 fredette mixoffset, wpwa, offset, mixsize));
968 1.18 fredette
969 1.18 fredette /* Assume we're going to loop to do the right channel. */
970 1.18 fredette choffset += MAESTRO_RECBUF_L_SZ;
971 1.18 fredette mixoffset += MAESTRO_MIXBUF_SZ >> 1;
972 1.18 fredette }
973 1.18 fredette
974 1.18 fredette wp_wrapu(ess, apuch, APUREG_APUTYPE,
975 1.18 fredette (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) |
976 1.18 fredette APU_DMA_ENABLED | 0xf);
977 1.18 fredette if (nch > 1)
978 1.18 fredette wp_wrapu(ess, apuch + 1, APUREG_APUTYPE,
979 1.18 fredette (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) |
980 1.18 fredette APU_DMA_ENABLED | 0xf);
981 1.18 fredette wp_wrapu(ess, apuch + 2, APUREG_APUTYPE,
982 1.18 fredette (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) |
983 1.18 fredette APU_DMA_ENABLED | 0xf);
984 1.18 fredette if (nch > 1)
985 1.18 fredette wp_wrapu(ess, apuch + 3, APUREG_APUTYPE,
986 1.18 fredette (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) |
987 1.18 fredette APU_DMA_ENABLED | 0xf);
988 1.18 fredette
989 1.1 rh return 0;
990 1.1 rh }
991 1.1 rh
992 1.1 rh
993 1.1 rh int
994 1.1 rh esm_halt_output(void *sc)
995 1.1 rh {
996 1.1 rh struct esm_softc *ess = sc;
997 1.1 rh struct esm_chinfo *ch = &ess->pch;
998 1.1 rh
999 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_output(%p)\n", sc));
1000 1.1 rh
1001 1.1 rh wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE,
1002 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1003 1.1 rh wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE,
1004 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1005 1.1 rh
1006 1.1 rh ess->pactive = 0;
1007 1.1 rh if (!ess->ractive)
1008 1.1 rh wp_stoptimer(ess);
1009 1.1 rh
1010 1.1 rh return 0;
1011 1.1 rh }
1012 1.1 rh
1013 1.1 rh
1014 1.1 rh int
1015 1.1 rh esm_halt_input(void *sc)
1016 1.1 rh {
1017 1.18 fredette struct esm_softc *ess = sc;
1018 1.18 fredette struct esm_chinfo *ch = &ess->rch;
1019 1.18 fredette
1020 1.18 fredette DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_input(%p)\n", sc));
1021 1.18 fredette
1022 1.18 fredette wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE,
1023 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1024 1.18 fredette wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE,
1025 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1026 1.18 fredette wp_wrapu(ess, (ch->num << 1) + 2, APUREG_APUTYPE,
1027 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1028 1.18 fredette wp_wrapu(ess, (ch->num << 1) + 3, APUREG_APUTYPE,
1029 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1030 1.18 fredette
1031 1.18 fredette ess->ractive = 0;
1032 1.18 fredette if (!ess->pactive)
1033 1.18 fredette wp_stoptimer(ess);
1034 1.18 fredette
1035 1.1 rh return 0;
1036 1.1 rh }
1037 1.1 rh
1038 1.1 rh
1039 1.1 rh static inline u_int
1040 1.1 rh calc_timer_freq(struct esm_chinfo *ch)
1041 1.1 rh {
1042 1.1 rh u_int freq;
1043 1.1 rh
1044 1.1 rh freq = (ch->sample_rate + ch->apublk - 1) / ch->apublk;
1045 1.1 rh
1046 1.1 rh DPRINTF(ESM_DEBUG_TIMER,
1047 1.1 rh ("calc_timer_freq(%p): rate = %u, blk = 0x%x (0x%x): freq = %u\n",
1048 1.1 rh ch, ch->sample_rate, ch->apublk, ch->blocksize, freq));
1049 1.1 rh
1050 1.1 rh return freq;
1051 1.1 rh }
1052 1.1 rh
1053 1.1 rh static void
1054 1.1 rh set_timer(struct esm_softc *ess)
1055 1.1 rh {
1056 1.1 rh unsigned freq = 0, freq2;
1057 1.1 rh
1058 1.1 rh if (ess->pactive)
1059 1.1 rh freq = calc_timer_freq(&ess->pch);
1060 1.1 rh
1061 1.1 rh if (ess->ractive) {
1062 1.1 rh freq2 = calc_timer_freq(&ess->rch);
1063 1.18 fredette if (freq2 > freq)
1064 1.1 rh freq = freq2;
1065 1.1 rh }
1066 1.1 rh
1067 1.18 fredette KASSERT(freq != 0);
1068 1.18 fredette
1069 1.1 rh for (; freq < MAESTRO_MINFREQ; freq <<= 1)
1070 1.1 rh ;
1071 1.1 rh
1072 1.1 rh if (freq > 0)
1073 1.1 rh wp_settimer(ess, freq);
1074 1.1 rh }
1075 1.1 rh
1076 1.1 rh
1077 1.1 rh static void
1078 1.1 rh esmch_set_format(struct esm_chinfo *ch, struct audio_params *p)
1079 1.1 rh {
1080 1.1 rh u_int16_t wcreg_tpl = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
1081 1.1 rh u_int16_t aputype = APUTYPE_16BITLINEAR;
1082 1.1 rh
1083 1.1 rh if (p->channels == 2) {
1084 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_STEREO;
1085 1.1 rh aputype++;
1086 1.1 rh }
1087 1.1 rh if (p->precision * p->factor == 8) {
1088 1.1 rh aputype += 2;
1089 1.1 rh if (p->encoding == AUDIO_ENCODING_ULINEAR)
1090 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_U8;
1091 1.1 rh }
1092 1.1 rh ch->wcreg_tpl = wcreg_tpl;
1093 1.1 rh ch->aputype = aputype;
1094 1.1 rh ch->sample_rate = p->sample_rate;
1095 1.1 rh
1096 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esmch_set_format: "
1097 1.1 rh "numch=%d, prec=%d*%d, tpl=0x%x, aputype=%d, rate=%ld\n",
1098 1.1 rh p->channels, p->precision, p->factor, wcreg_tpl, aputype,
1099 1.1 rh p->sample_rate));
1100 1.1 rh }
1101 1.1 rh
1102 1.18 fredette /*
1103 1.18 fredette * Since we can't record in true stereo, this function combines
1104 1.18 fredette * the separately recorded left and right channels into the final
1105 1.18 fredette * buffer for the upper layer.
1106 1.18 fredette */
1107 1.18 fredette static void
1108 1.18 fredette esmch_combine_input(struct esm_softc *ess, struct esm_chinfo *ch)
1109 1.18 fredette {
1110 1.18 fredette u_int32_t *dst32s;
1111 1.18 fredette size_t offset, resid, count;
1112 1.18 fredette const u_int32_t *left32s, *right32s;
1113 1.18 fredette u_int32_t left32, right32;
1114 1.18 fredette
1115 1.18 fredette /* The current offset into the upper layer buffer. */
1116 1.18 fredette offset = ch->offset;
1117 1.18 fredette
1118 1.18 fredette /* The number of bytes left to combine. */
1119 1.18 fredette resid = ch->blocksize;
1120 1.18 fredette
1121 1.18 fredette while (resid > 0) {
1122 1.18 fredette
1123 1.18 fredette /* The 32-bit words for the left channel. */
1124 1.18 fredette left32s = (const u_int32_t *)(ess->sc_dma.addr +
1125 1.18 fredette MAESTRO_RECBUF_L_OFF + offset / 2);
1126 1.18 fredette
1127 1.18 fredette /* The 32-bit words for the right channel. */
1128 1.18 fredette right32s = (const u_int32_t *)(ess->sc_dma.addr +
1129 1.18 fredette MAESTRO_RECBUF_R_OFF + offset / 2);
1130 1.18 fredette
1131 1.18 fredette /* The pointer to the 32-bit words we will write. */
1132 1.18 fredette dst32s = (u_int32_t *)(ch->buffer + offset);
1133 1.18 fredette
1134 1.18 fredette /* Get the number of bytes we will combine now. */
1135 1.18 fredette count = ch->bufsize - offset;
1136 1.18 fredette if (count > resid)
1137 1.18 fredette count = resid;
1138 1.18 fredette resid -= count;
1139 1.18 fredette offset += count;
1140 1.18 fredette if (offset == ch->bufsize)
1141 1.18 fredette offset = 0;
1142 1.18 fredette
1143 1.18 fredette /* Combine, writing two 32-bit words at a time. */
1144 1.18 fredette KASSERT((count & (sizeof(uint32_t) * 2 - 1)) == 0);
1145 1.18 fredette count /= (sizeof(u_int32_t) * 2);
1146 1.18 fredette while (count > 0) {
1147 1.18 fredette left32 = *(left32s++);
1148 1.18 fredette right32 = *(right32s++);
1149 1.18 fredette /* XXX this endian handling is half-baked at best */
1150 1.18 fredette #if BYTE_ORDER == LITTLE_ENDIAN
1151 1.18 fredette *(dst32s++) = (left32 & 0xFFFF) | (right32 << 16);
1152 1.18 fredette *(dst32s++) = (left32 >> 16) | (right32 & 0xFFFF0000);
1153 1.18 fredette #else /* BYTE_ORDER == BIG_ENDIAN */
1154 1.18 fredette *(dst32s++) = (left32 & 0xFFFF0000) | (right32 >> 16);
1155 1.18 fredette *(dst32s++) = (left32 << 16) | (right32 & 0xFFFF);
1156 1.18 fredette #endif /* BYTE_ORDER == BIG_ENDIAN */
1157 1.18 fredette count--;
1158 1.18 fredette }
1159 1.18 fredette }
1160 1.18 fredette
1161 1.18 fredette /* Update the offset. */
1162 1.18 fredette ch->offset = offset;
1163 1.18 fredette }
1164 1.1 rh
1165 1.1 rh /*
1166 1.1 rh * Audio interface glue functions
1167 1.1 rh */
1168 1.1 rh
1169 1.1 rh int
1170 1.1 rh esm_open(void *sc, int flags)
1171 1.1 rh {
1172 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_open(%p, 0x%x)\n", sc, flags));
1173 1.1 rh
1174 1.1 rh return 0;
1175 1.1 rh }
1176 1.1 rh
1177 1.1 rh
1178 1.1 rh void
1179 1.1 rh esm_close(void *sc)
1180 1.1 rh {
1181 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_close(%p)\n", sc));
1182 1.1 rh }
1183 1.1 rh
1184 1.1 rh
1185 1.1 rh int
1186 1.1 rh esm_getdev (void *sc, struct audio_device *adp)
1187 1.1 rh {
1188 1.1 rh *adp = esm_device;
1189 1.1 rh return 0;
1190 1.1 rh }
1191 1.1 rh
1192 1.1 rh
1193 1.1 rh int
1194 1.1 rh esm_round_blocksize (void *sc, int blk)
1195 1.1 rh {
1196 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
1197 1.1 rh ("esm_round_blocksize(%p, 0x%x)", sc, blk));
1198 1.1 rh
1199 1.1 rh blk &= ~0x3f; /* keep good alignment */
1200 1.1 rh
1201 1.1 rh DPRINTF(ESM_DEBUG_PARAM, (" = 0x%x\n", blk));
1202 1.1 rh
1203 1.1 rh return blk;
1204 1.1 rh }
1205 1.1 rh
1206 1.1 rh
1207 1.1 rh int
1208 1.1 rh esm_query_encoding(void *sc, struct audio_encoding *fp)
1209 1.1 rh {
1210 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
1211 1.1 rh ("esm_query_encoding(%p, %d)\n", sc, fp->index));
1212 1.1 rh
1213 1.1 rh if (fp->index < 0 || fp->index >= MAESTRO_NENCODINGS)
1214 1.1 rh return EINVAL;
1215 1.1 rh
1216 1.1 rh *fp = esm_encoding[fp->index];
1217 1.1 rh return 0;
1218 1.1 rh }
1219 1.1 rh
1220 1.1 rh
1221 1.1 rh int
1222 1.1 rh esm_set_params(void *sc, int setmode, int usemode,
1223 1.1 rh struct audio_params *play, struct audio_params *rec)
1224 1.1 rh {
1225 1.1 rh struct esm_softc *ess = sc;
1226 1.1 rh struct audio_params *p;
1227 1.1 rh int mode;
1228 1.1 rh
1229 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
1230 1.1 rh ("esm_set_params(%p, 0x%x, 0x%x, %p, %p)\n",
1231 1.1 rh sc, setmode, usemode, play, rec));
1232 1.1 rh
1233 1.1 rh for (mode = AUMODE_RECORD; mode != -1;
1234 1.1 rh mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
1235 1.1 rh if ((setmode & mode) == 0)
1236 1.1 rh continue;
1237 1.1 rh
1238 1.1 rh p = mode == AUMODE_PLAY ? play : rec;
1239 1.1 rh
1240 1.1 rh if (p->sample_rate < 4000 || p->sample_rate > 48000 ||
1241 1.1 rh (p->precision != 8 && p->precision != 16) ||
1242 1.1 rh (p->channels != 1 && p->channels != 2))
1243 1.1 rh return EINVAL;
1244 1.1 rh
1245 1.1 rh p->factor = 1;
1246 1.1 rh p->sw_code = 0;
1247 1.1 rh switch (p->encoding) {
1248 1.1 rh case AUDIO_ENCODING_SLINEAR_BE:
1249 1.1 rh if (p->precision == 16)
1250 1.1 rh p->sw_code = swap_bytes;
1251 1.1 rh else
1252 1.1 rh p->sw_code = change_sign8;
1253 1.1 rh break;
1254 1.1 rh case AUDIO_ENCODING_SLINEAR_LE:
1255 1.1 rh if (p->precision != 16)
1256 1.1 rh p->sw_code = change_sign8;
1257 1.1 rh break;
1258 1.1 rh case AUDIO_ENCODING_ULINEAR_BE:
1259 1.1 rh if (p->precision == 16) {
1260 1.1 rh if (mode == AUMODE_PLAY)
1261 1.1 rh p->sw_code = swap_bytes_change_sign16_le;
1262 1.1 rh else
1263 1.1 rh p->sw_code = change_sign16_swap_bytes_le;
1264 1.1 rh }
1265 1.1 rh break;
1266 1.1 rh case AUDIO_ENCODING_ULINEAR_LE:
1267 1.1 rh if (p->precision == 16)
1268 1.1 rh p->sw_code = change_sign16_le;
1269 1.1 rh break;
1270 1.1 rh case AUDIO_ENCODING_ULAW:
1271 1.1 rh if (mode == AUMODE_PLAY) {
1272 1.1 rh p->factor = 2;
1273 1.1 rh p->sw_code = mulaw_to_slinear16_le;
1274 1.1 rh } else
1275 1.1 rh p->sw_code = ulinear8_to_mulaw;
1276 1.1 rh break;
1277 1.1 rh case AUDIO_ENCODING_ALAW:
1278 1.1 rh if (mode == AUMODE_PLAY) {
1279 1.1 rh p->factor = 2;
1280 1.1 rh p->sw_code = alaw_to_slinear16_le;
1281 1.1 rh } else
1282 1.1 rh p->sw_code = ulinear8_to_alaw;
1283 1.1 rh break;
1284 1.1 rh default:
1285 1.1 rh return EINVAL;
1286 1.1 rh }
1287 1.1 rh }
1288 1.1 rh
1289 1.1 rh if (setmode & AUMODE_PLAY)
1290 1.1 rh esmch_set_format(&ess->pch, play);
1291 1.1 rh
1292 1.1 rh if (setmode & AUMODE_RECORD)
1293 1.1 rh esmch_set_format(&ess->rch, rec);
1294 1.1 rh
1295 1.1 rh return 0;
1296 1.1 rh }
1297 1.1 rh
1298 1.1 rh
1299 1.1 rh int
1300 1.1 rh esm_set_port(void *sc, mixer_ctrl_t *cp)
1301 1.1 rh {
1302 1.1 rh struct esm_softc *ess = sc;
1303 1.1 rh
1304 1.1 rh return (ess->codec_if->vtbl->mixer_set_port(ess->codec_if, cp));
1305 1.1 rh }
1306 1.1 rh
1307 1.1 rh
1308 1.1 rh int
1309 1.1 rh esm_get_port(void *sc, mixer_ctrl_t *cp)
1310 1.1 rh {
1311 1.1 rh struct esm_softc *ess = sc;
1312 1.1 rh
1313 1.1 rh return (ess->codec_if->vtbl->mixer_get_port(ess->codec_if, cp));
1314 1.1 rh }
1315 1.1 rh
1316 1.1 rh
1317 1.1 rh int
1318 1.1 rh esm_query_devinfo(void *sc, mixer_devinfo_t *dip)
1319 1.1 rh {
1320 1.1 rh struct esm_softc *ess = sc;
1321 1.1 rh
1322 1.1 rh return (ess->codec_if->vtbl->query_devinfo(ess->codec_if, dip));
1323 1.1 rh }
1324 1.1 rh
1325 1.1 rh
1326 1.1 rh void *
1327 1.1 rh esm_malloc(void *sc, int direction, size_t size, int pool, int flags)
1328 1.1 rh {
1329 1.1 rh struct esm_softc *ess = sc;
1330 1.18 fredette int off;
1331 1.1 rh
1332 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1333 1.1 rh ("esm_malloc(%p, %d, 0x%x, 0x%x, 0x%x)",
1334 1.1 rh sc, direction, size, pool, flags));
1335 1.1 rh
1336 1.18 fredette /*
1337 1.18 fredette * Each buffer can only be allocated once.
1338 1.18 fredette */
1339 1.18 fredette if (ess->rings_alloced & direction) {
1340 1.1 rh DPRINTF(ESM_DEBUG_DMA, (" = 0 (ENOMEM)\n"));
1341 1.1 rh return 0;
1342 1.1 rh }
1343 1.1 rh
1344 1.18 fredette /*
1345 1.18 fredette * Mark this buffer as allocated and return its
1346 1.18 fredette * kernel virtual address.
1347 1.18 fredette */
1348 1.18 fredette ess->rings_alloced |= direction;
1349 1.18 fredette off = (direction == AUMODE_PLAY ?
1350 1.18 fredette MAESTRO_PLAYBUF_OFF : MAESTRO_RECBUF_OFF);
1351 1.18 fredette DPRINTF(ESM_DEBUG_DMA, (" = %p (DMAADDR 0x%x)\n",
1352 1.18 fredette ess->sc_dma.addr + off,
1353 1.18 fredette (int)DMAADDR(&ess->sc_dma) + off));
1354 1.18 fredette return (ess->sc_dma.addr + off);
1355 1.1 rh }
1356 1.1 rh
1357 1.1 rh
1358 1.1 rh void
1359 1.1 rh esm_free(void *sc, void *ptr, int pool)
1360 1.1 rh {
1361 1.1 rh struct esm_softc *ess = sc;
1362 1.1 rh
1363 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1364 1.1 rh ("esm_free(%p, %p, 0x%x)\n",
1365 1.1 rh sc, ptr, pool));
1366 1.1 rh
1367 1.18 fredette if ((caddr_t)ptr == ess->sc_dma.addr + MAESTRO_PLAYBUF_OFF)
1368 1.18 fredette ess->rings_alloced &= ~AUMODE_PLAY;
1369 1.18 fredette else if ((caddr_t)ptr == ess->sc_dma.addr + MAESTRO_RECBUF_OFF)
1370 1.18 fredette ess->rings_alloced &= ~AUMODE_RECORD;
1371 1.1 rh }
1372 1.1 rh
1373 1.1 rh
1374 1.1 rh size_t
1375 1.1 rh esm_round_buffersize(void *sc, int direction, size_t size)
1376 1.1 rh {
1377 1.18 fredette if (size > MAESTRO_PLAYBUF_SZ)
1378 1.18 fredette size = MAESTRO_PLAYBUF_SZ;
1379 1.18 fredette if (size > MAESTRO_RECBUF_SZ)
1380 1.18 fredette size = MAESTRO_RECBUF_SZ;
1381 1.1 rh return size;
1382 1.1 rh }
1383 1.1 rh
1384 1.1 rh
1385 1.1 rh paddr_t
1386 1.1 rh esm_mappage(void *sc, void *mem, off_t off, int prot)
1387 1.1 rh {
1388 1.1 rh struct esm_softc *ess = sc;
1389 1.1 rh
1390 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1391 1.1 rh ("esm_mappage(%p, %p, 0x%lx, 0x%x)\n",
1392 1.1 rh sc, mem, (unsigned long)off, prot));
1393 1.1 rh
1394 1.1 rh if (off < 0)
1395 1.1 rh return (-1);
1396 1.1 rh
1397 1.18 fredette if ((caddr_t)mem == ess->sc_dma.addr + MAESTRO_PLAYBUF_OFF)
1398 1.18 fredette off += MAESTRO_PLAYBUF_OFF;
1399 1.18 fredette else if ((caddr_t)mem == ess->sc_dma.addr + MAESTRO_RECBUF_OFF)
1400 1.18 fredette off += MAESTRO_RECBUF_OFF;
1401 1.18 fredette else
1402 1.18 fredette return -1;
1403 1.18 fredette return bus_dmamem_mmap(ess->dmat, ess->sc_dma.segs, ess->sc_dma.nsegs,
1404 1.18 fredette off, prot, BUS_DMA_WAITOK);
1405 1.1 rh }
1406 1.1 rh
1407 1.1 rh
1408 1.1 rh int
1409 1.1 rh esm_get_props(void *sc)
1410 1.1 rh {
1411 1.1 rh return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1412 1.1 rh }
1413 1.1 rh
1414 1.1 rh
1415 1.1 rh /* -----------------------------
1416 1.1 rh * Bus space.
1417 1.1 rh */
1418 1.1 rh
1419 1.1 rh int
1420 1.1 rh esm_intr(void *sc)
1421 1.1 rh {
1422 1.1 rh struct esm_softc *ess = sc;
1423 1.1 rh u_int16_t status;
1424 1.1 rh u_int16_t pos;
1425 1.1 rh int ret = 0;
1426 1.1 rh
1427 1.1 rh status = bus_space_read_1(ess->st, ess->sh, PORT_HOSTINT_STAT);
1428 1.1 rh if (!status)
1429 1.1 rh return 0;
1430 1.1 rh
1431 1.1 rh /* Acknowledge all. */
1432 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
1433 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HOSTINT_STAT, 0);
1434 1.1 rh #if 0 /* XXX - HWVOL */
1435 1.1 rh if (status & HOSTINT_STAT_HWVOL) {
1436 1.1 rh u_int delta;
1437 1.1 rh delta = bus_space_read_1(ess->st, ess->sh, PORT_HWVOL_MASTER)
1438 1.1 rh - 0x88;
1439 1.1 rh if (delta & 0x11)
1440 1.1 rh mixer_set(device_get_softc(ess->dev),
1441 1.1 rh SOUND_MIXER_VOLUME, 0);
1442 1.1 rh else {
1443 1.1 rh mixer_set(device_get_softc(ess->dev),
1444 1.1 rh SOUND_MIXER_VOLUME,
1445 1.1 rh mixer_get(device_get_softc(ess->dev),
1446 1.1 rh SOUND_MIXER_VOLUME)
1447 1.1 rh + ((delta >> 5) & 0x7) - 4
1448 1.1 rh + ((delta << 7) & 0x700) - 0x400);
1449 1.1 rh }
1450 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HWVOL_MASTER, 0x88);
1451 1.1 rh ret++;
1452 1.1 rh }
1453 1.1 rh #endif /* XXX - HWVOL */
1454 1.1 rh
1455 1.1 rh if (ess->pactive) {
1456 1.1 rh pos = wp_rdapu(ess, ess->pch.num << 1, APUREG_CURPTR);
1457 1.1 rh
1458 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
1459 1.1 rh wp_rdapu(ess, (ess->pch.num<<1)+1, APUREG_CURPTR)));
1460 1.1 rh
1461 1.18 fredette pos -= ess->pch.apubase;
1462 1.1 rh if (pos >= ess->pch.nextirq &&
1463 1.1 rh pos - ess->pch.nextirq < ess->pch.apubuf / 2) {
1464 1.1 rh ess->pch.nextirq += ess->pch.apublk;
1465 1.1 rh
1466 1.1 rh if (ess->pch.nextirq >= ess->pch.apubuf)
1467 1.1 rh ess->pch.nextirq = 0;
1468 1.1 rh
1469 1.1 rh if (ess->sc_pintr) {
1470 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("P\n"));
1471 1.1 rh ess->sc_pintr(ess->sc_parg);
1472 1.1 rh }
1473 1.1 rh
1474 1.1 rh }
1475 1.1 rh ret++;
1476 1.1 rh }
1477 1.1 rh
1478 1.1 rh if (ess->ractive) {
1479 1.1 rh pos = wp_rdapu(ess, ess->rch.num << 1, APUREG_CURPTR);
1480 1.1 rh
1481 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
1482 1.1 rh wp_rdapu(ess, (ess->rch.num<<1)+1, APUREG_CURPTR)));
1483 1.1 rh
1484 1.18 fredette pos -= ess->rch.apubase;
1485 1.1 rh if (pos >= ess->rch.nextirq &&
1486 1.1 rh pos - ess->rch.nextirq < ess->rch.apubuf / 2) {
1487 1.1 rh ess->rch.nextirq += ess->rch.apublk;
1488 1.1 rh
1489 1.1 rh if (ess->rch.nextirq >= ess->rch.apubuf)
1490 1.1 rh ess->rch.nextirq = 0;
1491 1.1 rh
1492 1.1 rh if (ess->sc_rintr) {
1493 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("R\n"));
1494 1.18 fredette switch(ess->rch.aputype) {
1495 1.18 fredette case APUTYPE_16BITSTEREO:
1496 1.18 fredette esmch_combine_input(ess, &ess->rch);
1497 1.18 fredette break;
1498 1.18 fredette }
1499 1.18 fredette ess->sc_rintr(ess->sc_rarg);
1500 1.1 rh }
1501 1.1 rh
1502 1.1 rh }
1503 1.1 rh ret++;
1504 1.1 rh }
1505 1.1 rh
1506 1.1 rh return ret;
1507 1.1 rh }
1508 1.1 rh
1509 1.1 rh
1510 1.1 rh int
1511 1.1 rh esm_allocmem(struct esm_softc *sc, size_t size, size_t align,
1512 1.1 rh struct esm_dma *p)
1513 1.1 rh {
1514 1.1 rh int error;
1515 1.1 rh
1516 1.1 rh p->size = size;
1517 1.1 rh error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
1518 1.1 rh p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
1519 1.1 rh &p->nsegs, BUS_DMA_NOWAIT);
1520 1.1 rh if (error)
1521 1.1 rh return error;
1522 1.1 rh
1523 1.1 rh error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
1524 1.1 rh &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
1525 1.1 rh if (error)
1526 1.1 rh goto free;
1527 1.1 rh
1528 1.1 rh error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
1529 1.1 rh 0, BUS_DMA_NOWAIT, &p->map);
1530 1.1 rh if (error)
1531 1.1 rh goto unmap;
1532 1.1 rh
1533 1.1 rh error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
1534 1.1 rh BUS_DMA_NOWAIT);
1535 1.1 rh if (error)
1536 1.1 rh goto destroy;
1537 1.1 rh
1538 1.1 rh return 0;
1539 1.1 rh
1540 1.1 rh destroy:
1541 1.1 rh bus_dmamap_destroy(sc->dmat, p->map);
1542 1.1 rh unmap:
1543 1.1 rh bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1544 1.1 rh free:
1545 1.1 rh bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1546 1.1 rh
1547 1.1 rh return error;
1548 1.1 rh }
1549 1.1 rh
1550 1.1 rh
1551 1.1 rh int
1552 1.1 rh esm_freemem(struct esm_softc *sc, struct esm_dma *p)
1553 1.1 rh {
1554 1.1 rh bus_dmamap_unload(sc->dmat, p->map);
1555 1.1 rh bus_dmamap_destroy(sc->dmat, p->map);
1556 1.1 rh bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1557 1.1 rh bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1558 1.1 rh return 0;
1559 1.1 rh }
1560 1.1 rh
1561 1.1 rh
1562 1.1 rh int
1563 1.1 rh esm_match(struct device *dev, struct cfdata *match, void *aux)
1564 1.1 rh {
1565 1.1 rh struct pci_attach_args *pa = (struct pci_attach_args *) aux;
1566 1.1 rh
1567 1.1 rh switch (PCI_VENDOR(pa->pa_id)) {
1568 1.1 rh case PCI_VENDOR_ESSTECH:
1569 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) {
1570 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO1:
1571 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2:
1572 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2E:
1573 1.1 rh return 1;
1574 1.1 rh }
1575 1.1 rh
1576 1.1 rh case PCI_VENDOR_ESSTECH2:
1577 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) {
1578 1.1 rh case PCI_PRODUCT_ESSTECH2_MAESTRO1:
1579 1.1 rh return 1;
1580 1.1 rh }
1581 1.1 rh }
1582 1.1 rh return 0;
1583 1.1 rh }
1584 1.1 rh
1585 1.1 rh void
1586 1.1 rh esm_attach(struct device *parent, struct device *self, void *aux)
1587 1.1 rh {
1588 1.1 rh struct esm_softc *ess = (struct esm_softc *)self;
1589 1.1 rh struct pci_attach_args *pa = (struct pci_attach_args *)aux;
1590 1.1 rh pci_chipset_tag_t pc = pa->pa_pc;
1591 1.1 rh pcitag_t tag = pa->pa_tag;
1592 1.1 rh pci_intr_handle_t ih;
1593 1.1 rh pcireg_t csr, data;
1594 1.1 rh u_int16_t codec_data;
1595 1.18 fredette u_int16_t pcmbar;
1596 1.1 rh const char *intrstr;
1597 1.1 rh int revision;
1598 1.1 rh char devinfo[256];
1599 1.1 rh
1600 1.1 rh pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
1601 1.1 rh revision = PCI_REVISION(pa->pa_class);
1602 1.1 rh printf(": %s (rev. 0x%02x)\n", devinfo, revision);
1603 1.1 rh
1604 1.1 rh /* Enable the device. */
1605 1.1 rh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
1606 1.1 rh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
1607 1.1 rh csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
1608 1.1 rh
1609 1.1 rh /* Map I/O register */
1610 1.1 rh if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
1611 1.1 rh &ess->st, &ess->sh, NULL, NULL)) {
1612 1.1 rh printf("%s: can't map i/o space\n", ess->sc_dev.dv_xname);
1613 1.1 rh return;
1614 1.1 rh }
1615 1.1 rh
1616 1.1 rh /* Initialize softc */
1617 1.1 rh ess->pch.num = 0;
1618 1.18 fredette ess->rch.num = 1;
1619 1.1 rh ess->dmat = pa->pa_dmat;
1620 1.1 rh ess->tag = tag;
1621 1.1 rh ess->pc = pc;
1622 1.1 rh ess->subid = pci_conf_read(pc, tag, PCI_SUBSYS_ID_REG);
1623 1.1 rh
1624 1.3 rh DPRINTF(ESM_DEBUG_PCI,
1625 1.3 rh ("%s: sub-system vendor 0x%4.4x, product 0x%4.4x\n",
1626 1.3 rh ess->sc_dev.dv_xname,
1627 1.3 rh PCI_VENDOR(ess->subid), PCI_PRODUCT(ess->subid)));
1628 1.3 rh
1629 1.1 rh /* Map and establish the interrupt. */
1630 1.1 rh if (pci_intr_map(pa, &ih)) {
1631 1.1 rh printf("%s: can't map interrupt\n", ess->sc_dev.dv_xname);
1632 1.1 rh return;
1633 1.1 rh }
1634 1.1 rh intrstr = pci_intr_string(pc, ih);
1635 1.1 rh ess->ih = pci_intr_establish(pc, ih, IPL_AUDIO, esm_intr, self);
1636 1.1 rh if (ess->ih == NULL) {
1637 1.1 rh printf("%s: can't establish interrupt", ess->sc_dev.dv_xname);
1638 1.1 rh if (intrstr != NULL)
1639 1.1 rh printf(" at %s", intrstr);
1640 1.1 rh printf("\n");
1641 1.1 rh return;
1642 1.1 rh }
1643 1.1 rh printf("%s: interrupting at %s\n", ess->sc_dev.dv_xname, intrstr);
1644 1.1 rh
1645 1.1 rh /*
1646 1.1 rh * Setup PCI config registers
1647 1.1 rh */
1648 1.1 rh
1649 1.1 rh /* set to power state D0 */
1650 1.13 pooka esm_power(ess, PCI_PMCSR_STATE_D0);
1651 1.1 rh delay(100000);
1652 1.1 rh
1653 1.1 rh /* Disable all legacy emulations. */
1654 1.1 rh data = pci_conf_read(pc, tag, CONF_LEGACY);
1655 1.1 rh pci_conf_write(pc, tag, CONF_LEGACY, data | LEGACY_DISABLED);
1656 1.1 rh
1657 1.1 rh /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
1658 1.1 rh * Enable posted write.
1659 1.1 rh * Prefer PCI timing rather than that of ISA.
1660 1.1 rh * Don't swap L/R. */
1661 1.1 rh data = pci_conf_read(pc, tag, CONF_MAESTRO);
1662 1.1 rh data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
1663 1.1 rh data &= ~MAESTRO_SWAP_LR;
1664 1.1 rh pci_conf_write(pc, tag, CONF_MAESTRO, data);
1665 1.1 rh
1666 1.1 rh /* initialize sound chip */
1667 1.1 rh esm_init(ess);
1668 1.1 rh
1669 1.1 rh esm_read_codec(ess, 0, &codec_data);
1670 1.1 rh if (codec_data == 0x80) {
1671 1.1 rh printf("%s: PT101 codec detected!\n", ess->sc_dev.dv_xname);
1672 1.1 rh return;
1673 1.1 rh }
1674 1.1 rh
1675 1.3 rh /*
1676 1.3 rh * Some cards and Notebooks appear to have left and right channels
1677 1.3 rh * reversed. Check if there is a corresponding quirk entry for
1678 1.3 rh * the subsystem vendor and product and if so, set the appropriate
1679 1.3 rh * codec flag.
1680 1.3 rh */
1681 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_SWAPPEDCH) {
1682 1.3 rh ess->codec_flags |= AC97_HOST_SWAPPED_CHANNELS;
1683 1.3 rh }
1684 1.5 rh ess->codec_flags |= AC97_HOST_DONT_READ;
1685 1.3 rh
1686 1.1 rh /* initialize AC97 host interface */
1687 1.1 rh ess->host_if.arg = self;
1688 1.1 rh ess->host_if.attach = esm_attach_codec;
1689 1.1 rh ess->host_if.read = esm_read_codec;
1690 1.1 rh ess->host_if.write = esm_write_codec;
1691 1.1 rh ess->host_if.reset = esm_reset_codec;
1692 1.3 rh ess->host_if.flags = esm_flags_codec;
1693 1.1 rh
1694 1.1 rh if (ac97_attach(&ess->host_if) != 0)
1695 1.1 rh return;
1696 1.18 fredette
1697 1.18 fredette /* allocate our DMA region */
1698 1.18 fredette if (esm_allocmem(ess, MAESTRO_DMA_SZ, MAESTRO_DMA_ALIGN,
1699 1.18 fredette &ess->sc_dma)) {
1700 1.18 fredette printf("%s: couldn't allocate memory!\n", ess->sc_dev.dv_xname);
1701 1.18 fredette return;
1702 1.18 fredette }
1703 1.18 fredette ess->rings_alloced = 0;
1704 1.18 fredette
1705 1.18 fredette /* set DMA base address */
1706 1.18 fredette for (pcmbar = WAVCACHE_PCMBAR; pcmbar < WAVCACHE_PCMBAR + 4; pcmbar++)
1707 1.18 fredette wc_wrreg(ess, pcmbar,
1708 1.18 fredette DMAADDR(&ess->sc_dma) >> WAVCACHE_BASEADDR_SHIFT);
1709 1.1 rh
1710 1.1 rh audio_attach_mi(&esm_hw_if, self, &ess->sc_dev);
1711 1.7 ichiro
1712 1.7 ichiro ess->esm_suspend = PWR_RESUME;
1713 1.7 ichiro ess->esm_powerhook = powerhook_establish(esm_powerhook, ess);
1714 1.7 ichiro }
1715 1.7 ichiro
1716 1.7 ichiro /* Power Hook */
1717 1.7 ichiro void
1718 1.7 ichiro esm_powerhook(why, v)
1719 1.7 ichiro int why;
1720 1.7 ichiro void *v;
1721 1.7 ichiro {
1722 1.7 ichiro struct esm_softc *ess = (struct esm_softc *)v;
1723 1.7 ichiro
1724 1.7 ichiro DPRINTF(ESM_DEBUG_PARAM,
1725 1.7 ichiro ("%s: ESS maestro 2E why=%d\n", ess->sc_dev.dv_xname, why));
1726 1.7 ichiro switch (why) {
1727 1.8 ichiro case PWR_SUSPEND:
1728 1.8 ichiro case PWR_STANDBY:
1729 1.8 ichiro ess->esm_suspend = why;
1730 1.8 ichiro esm_suspend(ess);
1731 1.9 rh DPRINTF(ESM_DEBUG_RESUME, ("esm_suspend\n"));
1732 1.8 ichiro break;
1733 1.8 ichiro
1734 1.7 ichiro case PWR_RESUME:
1735 1.7 ichiro ess->esm_suspend = why;
1736 1.8 ichiro esm_resume(ess);
1737 1.9 rh DPRINTF(ESM_DEBUG_RESUME, ("esm_resumed\n"));
1738 1.7 ichiro break;
1739 1.7 ichiro }
1740 1.1 rh }
1741 1.1 rh
1742 1.1 rh int
1743 1.1 rh esm_suspend(struct esm_softc *ess)
1744 1.1 rh {
1745 1.8 ichiro int x;
1746 1.1 rh
1747 1.1 rh x = splaudio();
1748 1.1 rh wp_stoptimer(ess);
1749 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1750 1.1 rh
1751 1.1 rh esm_halt_output(ess);
1752 1.1 rh esm_halt_input(ess);
1753 1.1 rh splx(x);
1754 1.1 rh
1755 1.1 rh /* Power down everything except clock. */
1756 1.1 rh esm_write_codec(ess, AC97_REG_POWER, 0xdf00);
1757 1.1 rh delay(20);
1758 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
1759 1.1 rh delay(1);
1760 1.13 pooka esm_power(ess, PCI_PMCSR_STATE_D3);
1761 1.1 rh
1762 1.1 rh return 0;
1763 1.1 rh }
1764 1.1 rh
1765 1.1 rh int
1766 1.1 rh esm_resume(struct esm_softc *ess)
1767 1.1 rh {
1768 1.8 ichiro int x;
1769 1.1 rh
1770 1.13 pooka esm_power(ess, PCI_PMCSR_STATE_D0);
1771 1.1 rh delay(100000);
1772 1.1 rh esm_init(ess);
1773 1.8 ichiro
1774 1.8 ichiro (*ess->codec_if->vtbl->restore_ports)(ess->codec_if);
1775 1.8 ichiro #if 0
1776 1.1 rh if (mixer_reinit(dev)) {
1777 1.1 rh printf("%s: unable to reinitialize the mixer\n",
1778 1.1 rh ess->sc_dev.dv_xname);
1779 1.1 rh return ENXIO;
1780 1.1 rh }
1781 1.8 ichiro #endif
1782 1.1 rh
1783 1.1 rh x = splaudio();
1784 1.8 ichiro #if TODO
1785 1.1 rh if (ess->pactive)
1786 1.1 rh esm_start_output(ess);
1787 1.1 rh if (ess->ractive)
1788 1.1 rh esm_start_input(ess);
1789 1.8 ichiro #endif
1790 1.1 rh if (ess->pactive || ess->ractive) {
1791 1.1 rh set_timer(ess);
1792 1.1 rh wp_starttimer(ess);
1793 1.1 rh }
1794 1.1 rh splx(x);
1795 1.1 rh return 0;
1796 1.1 rh }
1797 1.1 rh
1798 1.8 ichiro #if 0
1799 1.1 rh int
1800 1.1 rh esm_shutdown(struct esm_softc *ess)
1801 1.1 rh {
1802 1.1 rh int i;
1803 1.1 rh
1804 1.1 rh wp_stoptimer(ess);
1805 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1806 1.1 rh
1807 1.1 rh esm_halt_output(ess);
1808 1.1 rh esm_halt_input(ess);
1809 1.1 rh
1810 1.1 rh return 0;
1811 1.1 rh }
1812 1.1 rh #endif
1813