esm.c revision 1.3 1 1.3 rh /* $NetBSD: esm.c,v 1.3 2001/01/09 23:27:07 rh Exp $ */
2 1.1 rh
3 1.1 rh /*-
4 1.1 rh * Copyright (c) 2000, 2001 Rene Hexel <rh (at) netbsd.org>
5 1.1 rh * All rights reserved.
6 1.1 rh *
7 1.1 rh * Copyright (c) 2000 Taku YAMAMOTO <taku (at) cent.saitama-u.ac.jp>
8 1.1 rh * All rights reserved.
9 1.1 rh *
10 1.1 rh * Redistribution and use in source and binary forms, with or without
11 1.1 rh * modification, are permitted provided that the following conditions
12 1.1 rh * are met:
13 1.1 rh * 1. Redistributions of source code must retain the above copyright
14 1.1 rh * notice, this list of conditions and the following disclaimer.
15 1.1 rh * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 rh * notice, this list of conditions and the following disclaimer in the
17 1.1 rh * documentation and/or other materials provided with the distribution.
18 1.1 rh *
19 1.1 rh * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 1.1 rh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 1.1 rh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 1.1 rh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 1.1 rh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 1.1 rh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 1.1 rh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 1.1 rh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 1.1 rh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 1.1 rh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 1.1 rh * SUCH DAMAGE.
30 1.1 rh *
31 1.1 rh * Taku Id: maestro.c,v 1.12 2000/09/06 03:32:34 taku Exp
32 1.1 rh * FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.4 2000/12/18 01:36:35 cg Exp
33 1.1 rh */
34 1.1 rh
35 1.1 rh /*
36 1.1 rh * TODO:
37 1.1 rh * - hardware volume support
38 1.1 rh * - recording
39 1.1 rh * - MIDI support
40 1.1 rh * - joystick support
41 1.1 rh * - power management hooks
42 1.1 rh *
43 1.1 rh *
44 1.1 rh * Credits:
45 1.1 rh *
46 1.1 rh * This code is based on the FreeBSD driver written by Taku YAMAMOTO
47 1.1 rh *
48 1.1 rh *
49 1.1 rh * Original credits from the FreeBSD driver:
50 1.1 rh *
51 1.1 rh * Part of this code (especially in many magic numbers) was heavily inspired
52 1.1 rh * by the Linux driver originally written by
53 1.1 rh * Alan Cox <alan.cox (at) linux.org>, modified heavily by
54 1.1 rh * Zach Brown <zab (at) zabbo.net>.
55 1.1 rh *
56 1.1 rh * busdma()-ize and buffer size reduction were suggested by
57 1.1 rh * Cameron Grant <gandalf (at) vilnya.demon.co.uk>.
58 1.1 rh * Also he showed me the way to use busdma() suite.
59 1.1 rh *
60 1.1 rh * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
61 1.1 rh * were looked at by
62 1.1 rh * Munehiro Matsuda <haro (at) tk.kubota.co.jp>,
63 1.1 rh * who brought patches based on the Linux driver with some simplification.
64 1.1 rh */
65 1.1 rh
66 1.1 rh #include <sys/param.h>
67 1.1 rh #include <sys/systm.h>
68 1.1 rh #include <sys/kernel.h>
69 1.1 rh #include <sys/malloc.h>
70 1.1 rh #include <sys/device.h>
71 1.1 rh
72 1.1 rh #include <machine/bus.h>
73 1.1 rh
74 1.1 rh #include <sys/audioio.h>
75 1.1 rh #include <dev/audio_if.h>
76 1.1 rh #include <dev/mulaw.h>
77 1.1 rh #include <dev/auconv.h>
78 1.1 rh #include <dev/ic/ac97var.h>
79 1.1 rh
80 1.1 rh #include <dev/pci/pcidevs.h>
81 1.1 rh #include <dev/pci/pcivar.h>
82 1.1 rh
83 1.1 rh #include <dev/pci/esmreg.h>
84 1.1 rh #include <dev/pci/esmvar.h>
85 1.1 rh
86 1.1 rh #define PCI_CBIO 0x10 /* Configuration Base I/O Address */
87 1.1 rh
88 1.1 rh /* Debug */
89 1.1 rh #ifdef AUDIO_DEBUG
90 1.1 rh #define DPRINTF(l,x) do { if (esm_debug & (l)) printf x; } while(0)
91 1.1 rh #define DUMPREG(x) do { if (esm_debug & ESM_DEBUG_REG) \
92 1.1 rh esm_dump_regs(x); } while(0)
93 1.1 rh int esm_debug = 0xfffc;
94 1.1 rh #define ESM_DEBUG_CODECIO 0x0001
95 1.1 rh #define ESM_DEBUG_IRQ 0x0002
96 1.1 rh #define ESM_DEBUG_DMA 0x0004
97 1.1 rh #define ESM_DEBUG_TIMER 0x0008
98 1.1 rh #define ESM_DEBUG_REG 0x0010
99 1.1 rh #define ESM_DEBUG_PARAM 0x0020
100 1.1 rh #define ESM_DEBUG_APU 0x0040
101 1.1 rh #define ESM_DEBUG_CODEC 0x0080
102 1.3 rh #define ESM_DEBUG_PCI 0x0100
103 1.1 rh #else
104 1.1 rh #define DPRINTF(x,y) /* nothing */
105 1.1 rh #define DUMPREG(x) /* nothing */
106 1.1 rh #endif
107 1.1 rh
108 1.1 rh #ifdef DIAGNOSTIC
109 1.1 rh #define RANGE(n, l, h) if ((n) < (l) || (n) >= (h)) \
110 1.1 rh printf (#n "=%d out of range (%d, %d) in " \
111 1.1 rh __FILE__ ", line %d\n", (n), (l), (h), __LINE__)
112 1.1 rh #else
113 1.1 rh #define RANGE(x,y,z) /* nothing */
114 1.1 rh #endif
115 1.1 rh
116 1.1 rh #define inline __inline
117 1.1 rh
118 1.1 rh static inline void ringbus_setdest(struct esm_softc *, int, int);
119 1.1 rh
120 1.1 rh static inline u_int16_t wp_rdreg(struct esm_softc *, u_int16_t);
121 1.1 rh static inline void wp_wrreg(struct esm_softc *, u_int16_t, u_int16_t);
122 1.1 rh static inline u_int16_t wp_rdapu(struct esm_softc *, int, u_int16_t);
123 1.1 rh static inline void wp_wrapu(struct esm_softc *, int, u_int16_t,
124 1.1 rh u_int16_t);
125 1.1 rh static inline void wp_settimer(struct esm_softc *, u_int);
126 1.1 rh static inline void wp_starttimer(struct esm_softc *);
127 1.1 rh static inline void wp_stoptimer(struct esm_softc *);
128 1.1 rh
129 1.1 rh static inline u_int16_t wc_rdreg(struct esm_softc *, u_int16_t);
130 1.1 rh static inline void wc_wrreg(struct esm_softc *, u_int16_t, u_int16_t);
131 1.1 rh static inline u_int16_t wc_rdchctl(struct esm_softc *, int);
132 1.1 rh static inline void wc_wrchctl(struct esm_softc *, int, u_int16_t);
133 1.1 rh
134 1.1 rh static inline u_int calc_timer_freq(struct esm_chinfo*);
135 1.1 rh static void set_timer(struct esm_softc *);
136 1.1 rh
137 1.1 rh static void esmch_set_format(struct esm_chinfo *,
138 1.1 rh struct audio_params *p);
139 1.1 rh
140 1.1 rh struct cfattach esm_ca = {
141 1.1 rh sizeof(struct esm_softc), esm_match, esm_attach
142 1.1 rh };
143 1.1 rh
144 1.1 rh struct audio_hw_if esm_hw_if = {
145 1.1 rh esm_open,
146 1.1 rh esm_close,
147 1.1 rh NULL, /* drain */
148 1.1 rh esm_query_encoding,
149 1.1 rh esm_set_params,
150 1.1 rh esm_round_blocksize,
151 1.1 rh NULL, /* commit_settings */
152 1.1 rh esm_init_output,
153 1.1 rh NULL, /* init_input */
154 1.1 rh NULL, /* start_output */
155 1.1 rh NULL, /* start_input */
156 1.1 rh esm_halt_output,
157 1.1 rh esm_halt_input,
158 1.1 rh NULL, /* speaker_ctl */
159 1.1 rh esm_getdev,
160 1.1 rh NULL, /* getfd */
161 1.1 rh esm_set_port,
162 1.1 rh esm_get_port,
163 1.1 rh esm_query_devinfo,
164 1.1 rh esm_malloc,
165 1.1 rh esm_free,
166 1.1 rh esm_round_buffersize,
167 1.1 rh esm_mappage,
168 1.1 rh esm_get_props,
169 1.1 rh esm_trigger_output,
170 1.1 rh esm_trigger_input
171 1.1 rh };
172 1.1 rh
173 1.1 rh struct audio_device esm_device = {
174 1.1 rh "ESS Maestro",
175 1.1 rh "",
176 1.1 rh "esm"
177 1.1 rh };
178 1.1 rh
179 1.1 rh
180 1.1 rh static audio_encoding_t esm_encoding[] = {
181 1.1 rh { 0, AudioEulinear, AUDIO_ENCODING_ULINEAR, 8, 0 },
182 1.1 rh { 1, AudioEmulaw, AUDIO_ENCODING_ULAW, 8,
183 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
184 1.1 rh { 2, AudioEalaw, AUDIO_ENCODING_ALAW, 8, AUDIO_ENCODINGFLAG_EMULATED },
185 1.1 rh { 3, AudioEslinear, AUDIO_ENCODING_SLINEAR, 8, 0 },
186 1.1 rh { 4, AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 16, 0 },
187 1.1 rh { 5, AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 16,
188 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
189 1.1 rh { 6, AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 16,
190 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
191 1.1 rh { 7, AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 16,
192 1.1 rh AUDIO_ENCODINGFLAG_EMULATED },
193 1.1 rh };
194 1.1 rh
195 1.1 rh #define MAESTRO_NENCODINGS 8
196 1.1 rh
197 1.3 rh
198 1.3 rh static const struct esm_quirks esm_quirks[] = {
199 1.3 rh /* COMPAL 38W2 OEM Notebook, e.g. Dell INSPIRON 5000e */
200 1.3 rh { PCI_VENDOR_COMPAL, PCI_PRODUCT_COMPAL_38W2, ESM_QUIRKF_SWAPPEDCH },
201 1.3 rh
202 1.3 rh /* NEC Versa Pro LX VA26D */
203 1.3 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VA26D, ESM_QUIRKF_GPIO },
204 1.3 rh
205 1.3 rh /* NEC Versa LX */
206 1.3 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSALX, ESM_QUIRKF_GPIO }
207 1.3 rh };
208 1.3 rh
209 1.3 rh enum esm_quirk_flags
210 1.3 rh esm_get_quirks(pcireg_t subid)
211 1.3 rh {
212 1.3 rh int i;
213 1.3 rh
214 1.3 rh for (i = 0; i < (sizeof esm_quirks / sizeof esm_quirks[0]); i++) {
215 1.3 rh if (PCI_VENDOR(subid) == esm_quirks[i].eq_vendor &&
216 1.3 rh PCI_PRODUCT(subid) == esm_quirks[i].eq_product) {
217 1.3 rh return esm_quirks[i].eq_quirks;
218 1.3 rh }
219 1.3 rh }
220 1.3 rh
221 1.3 rh return 0;
222 1.3 rh }
223 1.3 rh
224 1.3 rh
225 1.1 rh #ifdef AUDIO_DEBUG
226 1.1 rh struct esm_reg_info {
227 1.1 rh int offset; /* register offset */
228 1.1 rh int width; /* 1/2/4 bytes */
229 1.1 rh } dump_regs[] = {
230 1.1 rh { PORT_WAVCACHE_CTRL, 2 },
231 1.1 rh { PORT_HOSTINT_CTRL, 2 },
232 1.1 rh { PORT_HOSTINT_STAT, 2 },
233 1.1 rh { PORT_HWVOL_VOICE_SHADOW, 1 },
234 1.1 rh { PORT_HWVOL_VOICE, 1 },
235 1.1 rh { PORT_HWVOL_MASTER_SHADOW, 1 },
236 1.1 rh { PORT_HWVOL_MASTER, 1 },
237 1.1 rh { PORT_RINGBUS_CTRL, 4 },
238 1.1 rh { PORT_GPIO_DATA, 2 },
239 1.1 rh { PORT_GPIO_MASK, 2 },
240 1.1 rh { PORT_GPIO_DIR, 2 },
241 1.1 rh { PORT_ASSP_CTRL_A, 1 },
242 1.1 rh { PORT_ASSP_CTRL_B, 1 },
243 1.1 rh { PORT_ASSP_CTRL_C, 1 },
244 1.3 rh { PORT_ASSP_INT_STAT, 1 }
245 1.1 rh };
246 1.1 rh
247 1.2 lukem static void
248 1.2 lukem esm_dump_regs(struct esm_softc *ess)
249 1.1 rh {
250 1.3 rh int i;
251 1.1 rh
252 1.1 rh printf("%s registers:", ess->sc_dev.dv_xname);
253 1.3 rh for (i = 0; i < (sizeof dump_regs / sizeof dump_regs[0]); i++) {
254 1.1 rh if (i % 5 == 0)
255 1.1 rh printf("\n");
256 1.1 rh printf("0x%2.2x: ", dump_regs[i].offset);
257 1.1 rh switch(dump_regs[i].width) {
258 1.1 rh case 4:
259 1.1 rh printf("%8.8x, ", bus_space_read_4(ess->st, ess->sh,
260 1.1 rh dump_regs[i].offset));
261 1.1 rh break;
262 1.1 rh case 2:
263 1.1 rh printf("%4.4x, ", bus_space_read_2(ess->st, ess->sh,
264 1.1 rh dump_regs[i].offset));
265 1.1 rh break;
266 1.1 rh default:
267 1.1 rh printf("%2.2x, ",
268 1.1 rh bus_space_read_1(ess->st, ess->sh,
269 1.1 rh dump_regs[i].offset));
270 1.1 rh }
271 1.1 rh }
272 1.1 rh printf("\n");
273 1.1 rh }
274 1.1 rh #endif
275 1.1 rh
276 1.3 rh
277 1.1 rh /* -----------------------------
278 1.1 rh * Subsystems.
279 1.1 rh */
280 1.1 rh
281 1.1 rh /* Codec/Ringbus */
282 1.1 rh
283 1.1 rh /* -------------------------------------------------------------------- */
284 1.1 rh
285 1.1 rh int
286 1.1 rh esm_read_codec(void *sc, u_int8_t regno, u_int16_t *result)
287 1.1 rh {
288 1.1 rh struct esm_softc *ess = sc;
289 1.1 rh unsigned t;
290 1.1 rh
291 1.1 rh /* We have to wait for a SAFE time to write addr/data */
292 1.1 rh for (t = 0; t < 20; t++) {
293 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
294 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
295 1.1 rh break;
296 1.1 rh delay(2); /* 20.8us / 13 */
297 1.1 rh }
298 1.1 rh if (t == 20)
299 1.1 rh printf("%s: esm_read_codec() PROGLESS timed out.\n",
300 1.1 rh ess->sc_dev.dv_xname);
301 1.1 rh
302 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
303 1.1 rh CODEC_CMD_READ | regno);
304 1.1 rh delay(21); /* AC97 cycle = 20.8usec */
305 1.1 rh
306 1.1 rh /* Wait for data retrieve */
307 1.1 rh for (t = 0; t < 20; t++) {
308 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
309 1.1 rh & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE)
310 1.1 rh break;
311 1.1 rh delay(2); /* 20.8us / 13 */
312 1.1 rh }
313 1.1 rh if (t == 20)
314 1.1 rh /* Timed out, but perform dummy read. */
315 1.1 rh printf("%s: esm_read_codec() RW_DONE timed out.\n",
316 1.1 rh ess->sc_dev.dv_xname);
317 1.1 rh
318 1.1 rh *result = bus_space_read_2(ess->st, ess->sh, PORT_CODEC_REG);
319 1.1 rh
320 1.1 rh return 0;
321 1.1 rh }
322 1.1 rh
323 1.1 rh int
324 1.1 rh esm_write_codec(void *sc, u_int8_t regno, u_int16_t data)
325 1.1 rh {
326 1.1 rh struct esm_softc *ess = sc;
327 1.1 rh unsigned t;
328 1.1 rh
329 1.1 rh /* We have to wait for a SAFE time to write addr/data */
330 1.1 rh for (t = 0; t < 20; t++) {
331 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
332 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
333 1.1 rh break;
334 1.1 rh delay(2); /* 20.8us / 13 */
335 1.1 rh }
336 1.1 rh if (t == 20) {
337 1.1 rh /* Timed out. Abort writing. */
338 1.1 rh printf("%s: esm_write_codec() PROGLESS timed out.\n",
339 1.1 rh ess->sc_dev.dv_xname);
340 1.1 rh return -1;
341 1.1 rh }
342 1.1 rh
343 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_CODEC_REG, data);
344 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
345 1.1 rh CODEC_CMD_WRITE | regno);
346 1.1 rh
347 1.1 rh return 0;
348 1.1 rh }
349 1.1 rh
350 1.1 rh /* -------------------------------------------------------------------- */
351 1.1 rh
352 1.1 rh static inline void
353 1.1 rh ringbus_setdest(struct esm_softc *ess, int src, int dest)
354 1.1 rh {
355 1.1 rh u_int32_t data;
356 1.1 rh
357 1.1 rh data = bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL);
358 1.1 rh data &= ~(0xfU << src);
359 1.1 rh data |= (0xfU & dest) << src;
360 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, data);
361 1.1 rh }
362 1.1 rh
363 1.1 rh /* Wave Processor */
364 1.1 rh
365 1.1 rh static inline u_int16_t
366 1.1 rh wp_rdreg(struct esm_softc *ess, u_int16_t reg)
367 1.1 rh {
368 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
369 1.1 rh return bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA);
370 1.1 rh }
371 1.1 rh
372 1.1 rh static inline void
373 1.1 rh wp_wrreg(struct esm_softc *ess, u_int16_t reg, u_int16_t data)
374 1.1 rh {
375 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
376 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
377 1.1 rh }
378 1.1 rh
379 1.1 rh static inline void
380 1.1 rh apu_setindex(struct esm_softc *ess, u_int16_t reg)
381 1.1 rh {
382 1.1 rh int t;
383 1.1 rh
384 1.1 rh wp_wrreg(ess, WPREG_CRAM_PTR, reg);
385 1.1 rh /* Sometimes WP fails to set apu register index. */
386 1.1 rh for (t = 0; t < 1000; t++) {
387 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == reg)
388 1.1 rh break;
389 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, reg);
390 1.1 rh }
391 1.1 rh if (t == 1000)
392 1.1 rh printf("%s: apu_setindex() timed out.\n", ess->sc_dev.dv_xname);
393 1.1 rh }
394 1.1 rh
395 1.1 rh static inline u_int16_t
396 1.1 rh wp_rdapu(struct esm_softc *ess, int ch, u_int16_t reg)
397 1.1 rh {
398 1.1 rh u_int16_t ret;
399 1.1 rh
400 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg);
401 1.1 rh ret = wp_rdreg(ess, WPREG_DATA_PORT);
402 1.1 rh return ret;
403 1.1 rh }
404 1.1 rh
405 1.1 rh static inline void
406 1.1 rh wp_wrapu(struct esm_softc *ess, int ch, u_int16_t reg, u_int16_t data)
407 1.1 rh {
408 1.1 rh int t;
409 1.1 rh
410 1.1 rh DPRINTF(ESM_DEBUG_APU,
411 1.1 rh ("wp_wrapu(%p, ch=%d, reg=0x%x, data=0x%04x)\n",
412 1.1 rh ess, ch, reg, data));
413 1.1 rh
414 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg);
415 1.1 rh wp_wrreg(ess, WPREG_DATA_PORT, data);
416 1.1 rh for (t = 0; t < 1000; t++) {
417 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == data)
418 1.1 rh break;
419 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
420 1.1 rh }
421 1.1 rh if (t == 1000)
422 1.1 rh printf("%s: wp_wrapu() timed out.\n", ess->sc_dev.dv_xname);
423 1.1 rh }
424 1.1 rh
425 1.1 rh static inline void
426 1.1 rh wp_settimer(struct esm_softc *ess, u_int freq)
427 1.1 rh {
428 1.1 rh u_int clock = 48000 << 2;
429 1.1 rh u_int prescale = 0, divide = (freq != 0) ? (clock / freq) : ~0;
430 1.1 rh
431 1.1 rh RANGE(divide, WPTIMER_MINDIV, WPTIMER_MAXDIV);
432 1.1 rh
433 1.1 rh for (; divide > 32 << 1; divide >>= 1)
434 1.1 rh prescale++;
435 1.1 rh divide = (divide + 1) >> 1;
436 1.1 rh
437 1.1 rh for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
438 1.1 rh prescale++;
439 1.1 rh
440 1.1 rh DPRINTF(ESM_DEBUG_TIMER,
441 1.1 rh ("wp_settimer(%p, %u): clock = %u, prescale = %u, divide = %u\n",
442 1.1 rh ess, freq, clock, prescale, divide));
443 1.1 rh
444 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
445 1.1 rh wp_wrreg(ess, WPREG_TIMER_FREQ,
446 1.1 rh (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
447 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
448 1.1 rh }
449 1.1 rh
450 1.1 rh static inline void
451 1.1 rh wp_starttimer(struct esm_softc *ess)
452 1.1 rh {
453 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 1);
454 1.1 rh }
455 1.1 rh
456 1.1 rh static inline void
457 1.1 rh wp_stoptimer(struct esm_softc *ess)
458 1.1 rh {
459 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 0);
460 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
461 1.1 rh }
462 1.1 rh
463 1.1 rh /* WaveCache */
464 1.1 rh
465 1.1 rh static inline u_int16_t
466 1.1 rh wc_rdreg(struct esm_softc *ess, u_int16_t reg)
467 1.1 rh {
468 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
469 1.1 rh return bus_space_read_2(ess->st, ess->sh, PORT_WAVCACHE_DATA);
470 1.1 rh }
471 1.1 rh
472 1.1 rh static inline void
473 1.1 rh wc_wrreg(struct esm_softc *ess, u_int16_t reg, u_int16_t data)
474 1.1 rh {
475 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
476 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_DATA, data);
477 1.1 rh }
478 1.1 rh
479 1.1 rh static inline u_int16_t
480 1.1 rh wc_rdchctl(struct esm_softc *ess, int ch)
481 1.1 rh {
482 1.1 rh return wc_rdreg(ess, ch << 3);
483 1.1 rh }
484 1.1 rh
485 1.1 rh static inline void
486 1.1 rh wc_wrchctl(struct esm_softc *ess, int ch, u_int16_t data)
487 1.1 rh {
488 1.1 rh wc_wrreg(ess, ch << 3, data);
489 1.1 rh }
490 1.1 rh
491 1.1 rh /* Power management */
492 1.1 rh
493 1.1 rh void
494 1.1 rh esm_power(struct esm_softc *ess, int status)
495 1.1 rh {
496 1.1 rh u_int8_t data;
497 1.1 rh
498 1.1 rh data = pci_conf_read(ess->pc, ess->tag, CONF_PM_PTR);
499 1.1 rh if ((pci_conf_read(ess->pc, ess->tag, data) & 0xff) == PPMI_CID)
500 1.1 rh pci_conf_write(ess->pc, ess->tag, data + PM_CTRL, status);
501 1.1 rh }
502 1.1 rh
503 1.1 rh
504 1.1 rh /* -----------------------------
505 1.1 rh * Controller.
506 1.1 rh */
507 1.1 rh
508 1.1 rh int
509 1.1 rh esm_attach_codec(void *sc, struct ac97_codec_if *codec_if)
510 1.1 rh {
511 1.1 rh struct esm_softc *ess = sc;
512 1.1 rh
513 1.1 rh ess->codec_if = codec_if;
514 1.1 rh
515 1.1 rh return 0;
516 1.1 rh }
517 1.1 rh
518 1.1 rh void
519 1.1 rh esm_reset_codec(void *sc)
520 1.1 rh {
521 1.1 rh }
522 1.1 rh
523 1.1 rh
524 1.3 rh enum ac97_host_flags
525 1.3 rh esm_flags_codec(void *sc)
526 1.3 rh {
527 1.3 rh struct esm_softc *ess = sc;
528 1.3 rh
529 1.3 rh return ess->codec_flags;
530 1.3 rh }
531 1.3 rh
532 1.3 rh
533 1.1 rh void
534 1.1 rh esm_initcodec(struct esm_softc *ess)
535 1.1 rh {
536 1.1 rh u_int16_t data;
537 1.1 rh
538 1.1 rh DPRINTF(ESM_DEBUG_CODEC, ("esm_initcodec(%p)\n", ess));
539 1.1 rh
540 1.1 rh if (bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL)
541 1.1 rh & RINGBUS_CTRL_ACLINK_ENABLED) {
542 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
543 1.1 rh delay(104); /* 20.8us * (4 + 1) */
544 1.1 rh }
545 1.1 rh /* XXX - 2nd codec should be looked at. */
546 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
547 1.1 rh RINGBUS_CTRL_AC97_SWRESET);
548 1.1 rh delay(2);
549 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
550 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED);
551 1.1 rh delay(21);
552 1.1 rh
553 1.1 rh esm_read_codec(ess, 0, &data);
554 1.1 rh if (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
555 1.1 rh & CODEC_STAT_MASK) {
556 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
557 1.1 rh delay(21);
558 1.1 rh
559 1.1 rh /* Try cold reset. */
560 1.1 rh printf("%s: will perform cold reset.\n", ess->sc_dev.dv_xname);
561 1.1 rh data = bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR);
562 1.1 rh if (pci_conf_read(ess->pc, ess->tag, 0x58) & 1)
563 1.1 rh data |= 0x10;
564 1.1 rh data |= 0x009 &
565 1.1 rh ~bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DATA);
566 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0xff6);
567 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
568 1.1 rh data | 0x009);
569 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x000);
570 1.1 rh delay(2);
571 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x001);
572 1.1 rh delay(1);
573 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x009);
574 1.1 rh delay(500000);
575 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, data);
576 1.1 rh delay(84); /* 20.8us * 4 */
577 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
578 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED);
579 1.1 rh delay(21);
580 1.1 rh }
581 1.1 rh }
582 1.1 rh
583 1.1 rh void
584 1.1 rh esm_init(struct esm_softc *ess)
585 1.1 rh {
586 1.1 rh /* Reset direct sound. */
587 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
588 1.1 rh HOSTINT_CTRL_DSOUND_RESET);
589 1.1 rh delay(10000);
590 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
591 1.1 rh delay(10000);
592 1.1 rh
593 1.1 rh /* Enable direct sound interruption. */
594 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
595 1.1 rh HOSTINT_CTRL_DSOUND_INT_ENABLED);
596 1.1 rh
597 1.1 rh /* Setup Wave Processor. */
598 1.1 rh
599 1.1 rh /* Enable WaveCache */
600 1.1 rh wp_wrreg(ess, WPREG_WAVE_ROMRAM,
601 1.1 rh WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
602 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_CTRL,
603 1.1 rh WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB);
604 1.1 rh
605 1.1 rh /* Setup Codec/Ringbus. */
606 1.1 rh esm_initcodec(ess);
607 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
608 1.1 rh RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED);
609 1.1 rh
610 1.1 rh wp_wrreg(ess, WPREG_BASE, 0x8500); /* Parallel I/O */
611 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_ADC,
612 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
613 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
614 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
615 1.1 rh
616 1.1 rh /* Setup ASSP. Needed for Dell Inspiron 7500? */
617 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_B, 0x00);
618 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_A, 0x03);
619 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_C, 0x00);
620 1.1 rh
621 1.1 rh /*
622 1.1 rh * Setup GPIO.
623 1.1 rh * There seems to be speciality with NEC systems.
624 1.1 rh */
625 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_GPIO) {
626 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK,
627 1.3 rh 0x9ff);
628 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
629 1.3 rh bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR) |
630 1.3 rh 0x600);
631 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA,
632 1.3 rh 0x200);
633 1.1 rh }
634 1.1 rh
635 1.1 rh DUMPREG(ess);
636 1.1 rh }
637 1.1 rh
638 1.1 rh
639 1.1 rh /* Channel controller. */
640 1.1 rh
641 1.1 rh int
642 1.1 rh esm_init_output (void *sc, void *start, int size)
643 1.1 rh {
644 1.1 rh struct esm_softc *ess = sc;
645 1.1 rh struct esm_dma *p;
646 1.1 rh u_int32_t data;
647 1.1 rh
648 1.1 rh for (p = ess->sc_dmas; p && KERNADDR(p) != start; p = p->next)
649 1.1 rh ;
650 1.1 rh if (!p) {
651 1.1 rh printf("%s: esm_init_output: bad addr %p\n",
652 1.1 rh ess->sc_dev.dv_xname, start);
653 1.1 rh return EINVAL;
654 1.1 rh }
655 1.1 rh
656 1.1 rh ess->pch.base = DMAADDR(p) & ~0xFFF;
657 1.1 rh
658 1.1 rh DPRINTF(ESM_DEBUG_DMA, ("%s: pch.base = 0x%x\n",
659 1.1 rh ess->sc_dev.dv_xname, ess->pch.base));
660 1.1 rh
661 1.1 rh /* set DMA base address */
662 1.1 rh for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
663 1.1 rh wc_wrreg(ess, data, ess->pch.base >> WAVCACHE_BASEADDR_SHIFT);
664 1.1 rh
665 1.1 rh return 0;
666 1.1 rh }
667 1.1 rh
668 1.1 rh
669 1.1 rh int
670 1.1 rh esm_trigger_output(void *sc, void *start, void *end, int blksize,
671 1.1 rh void (*intr)(void *), void *arg, struct audio_params *param)
672 1.1 rh {
673 1.1 rh struct esm_softc *ess = sc;
674 1.1 rh struct esm_chinfo *ch = &ess->pch;
675 1.1 rh struct esm_dma *p;
676 1.1 rh int pan = 0, choffset;
677 1.3 rh int i, nch = 1;
678 1.1 rh unsigned speed = ch->sample_rate, offset, wpwa, dv;
679 1.1 rh size_t size;
680 1.1 rh u_int16_t apuch = ch->num << 1;
681 1.1 rh
682 1.1 rh DPRINTF(ESM_DEBUG_DMA,
683 1.1 rh ("esm_trigger_output(%p, %p, %p, 0x%x, %p, %p, %p)\n",
684 1.1 rh sc, start, end, blksize, intr, arg, param));
685 1.1 rh
686 1.1 rh #ifdef DIAGNOSTIC
687 1.1 rh if (ess->pactive) {
688 1.1 rh printf("%s: esm_trigger_output: already running",
689 1.1 rh ess->sc_dev.dv_xname);
690 1.1 rh return EINVAL;
691 1.1 rh }
692 1.1 rh #endif
693 1.1 rh
694 1.1 rh ess->sc_pintr = intr;
695 1.1 rh ess->sc_parg = arg;
696 1.1 rh for (p = ess->sc_dmas; p && KERNADDR(p) != start; p = p->next)
697 1.1 rh ;
698 1.1 rh if (!p) {
699 1.1 rh printf("%s: esm_trigger_output: bad addr %p\n",
700 1.1 rh ess->sc_dev.dv_xname, start);
701 1.1 rh return EINVAL;
702 1.1 rh }
703 1.1 rh
704 1.1 rh ess->pch.blocksize = blksize;
705 1.1 rh ess->pch.apublk = blksize >> 1;
706 1.1 rh ess->pactive = 1;
707 1.1 rh
708 1.1 rh size = (size_t)(((caddr_t)end - (caddr_t)start) >> 1);
709 1.1 rh choffset = DMAADDR(p) - ess->pch.base;
710 1.1 rh offset = choffset >> 1;
711 1.1 rh wpwa = APU_USE_SYSMEM | (offset >> 9);
712 1.1 rh
713 1.1 rh DPRINTF(ESM_DEBUG_DMA,
714 1.1 rh ("choffs=0x%x, wpwa=0x%x, size=0x%x words\n",
715 1.1 rh choffset, wpwa, size));
716 1.1 rh
717 1.1 rh switch (ch->aputype) {
718 1.1 rh case APUTYPE_16BITSTEREO:
719 1.1 rh ess->pch.apublk >>= 1;
720 1.1 rh wpwa >>= 1;
721 1.1 rh size >>= 1;
722 1.1 rh offset >>= 1;
723 1.1 rh /* FALLTHROUGH */
724 1.1 rh case APUTYPE_8BITSTEREO:
725 1.3 rh if (ess->codec_flags & AC97_HOST_SWAPPED_CHANNELS)
726 1.3 rh pan = 8;
727 1.3 rh else
728 1.3 rh pan = -8;
729 1.3 rh nch++;
730 1.1 rh break;
731 1.1 rh case APUTYPE_8BITLINEAR:
732 1.1 rh ess->pch.apublk <<= 1;
733 1.1 rh speed >>= 1;
734 1.1 rh break;
735 1.1 rh }
736 1.1 rh
737 1.1 rh ess->pch.apubuf = size;
738 1.1 rh ess->pch.nextirq = ess->pch.apublk;
739 1.1 rh
740 1.1 rh set_timer(ess);
741 1.1 rh wp_starttimer(ess);
742 1.1 rh
743 1.1 rh dv = (((speed % 48000) << 16) + 24000) / 48000
744 1.1 rh + ((speed / 48000) << 16);
745 1.1 rh
746 1.3 rh for (i = nch-1; i >= 0; i--) {
747 1.3 rh wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa & 0xff00);
748 1.3 rh wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset);
749 1.3 rh wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size);
750 1.3 rh wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1);
751 1.3 rh wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800);
752 1.3 rh wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00
753 1.1 rh | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
754 1.1 rh | ((PAN_FRONT + pan) << APU_PAN_SHIFT));
755 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB
756 1.1 rh | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
757 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8);
758 1.1 rh
759 1.1 rh if (ch->aputype == APUTYPE_16BITSTEREO)
760 1.1 rh wpwa |= APU_STEREO >> 1;
761 1.1 rh pan = -pan;
762 1.3 rh }
763 1.1 rh
764 1.1 rh wc_wrchctl(ess, apuch, ch->wcreg_tpl);
765 1.3 rh if (nch > 1)
766 1.3 rh wc_wrchctl(ess, apuch + 1, ch->wcreg_tpl);
767 1.1 rh
768 1.1 rh wp_wrapu(ess, apuch, APUREG_APUTYPE,
769 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
770 1.1 rh if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO)
771 1.1 rh wp_wrapu(ess, apuch + 1, APUREG_APUTYPE,
772 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
773 1.1 rh
774 1.1 rh return 0;
775 1.1 rh }
776 1.1 rh
777 1.1 rh
778 1.1 rh int
779 1.1 rh esm_trigger_input(void *sc, void *start, void *end, int blksize,
780 1.1 rh void (*intr)(void *), void *arg, struct audio_params *param)
781 1.1 rh {
782 1.1 rh return 0;
783 1.1 rh }
784 1.1 rh
785 1.1 rh
786 1.1 rh int
787 1.1 rh esm_halt_output(void *sc)
788 1.1 rh {
789 1.1 rh struct esm_softc *ess = sc;
790 1.1 rh struct esm_chinfo *ch = &ess->pch;
791 1.1 rh
792 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_output(%p)\n", sc));
793 1.1 rh
794 1.1 rh wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE,
795 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
796 1.1 rh wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE,
797 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
798 1.1 rh
799 1.1 rh ess->pactive = 0;
800 1.1 rh if (!ess->ractive)
801 1.1 rh wp_stoptimer(ess);
802 1.1 rh
803 1.1 rh return 0;
804 1.1 rh }
805 1.1 rh
806 1.1 rh
807 1.1 rh int
808 1.1 rh esm_halt_input(void *sc)
809 1.1 rh {
810 1.1 rh return 0;
811 1.1 rh }
812 1.1 rh
813 1.1 rh
814 1.1 rh static inline u_int
815 1.1 rh calc_timer_freq(struct esm_chinfo *ch)
816 1.1 rh {
817 1.1 rh u_int freq;
818 1.1 rh
819 1.1 rh freq = (ch->sample_rate + ch->apublk - 1) / ch->apublk;
820 1.1 rh
821 1.1 rh DPRINTF(ESM_DEBUG_TIMER,
822 1.1 rh ("calc_timer_freq(%p): rate = %u, blk = 0x%x (0x%x): freq = %u\n",
823 1.1 rh ch, ch->sample_rate, ch->apublk, ch->blocksize, freq));
824 1.1 rh
825 1.1 rh return freq;
826 1.1 rh }
827 1.1 rh
828 1.1 rh static void
829 1.1 rh set_timer(struct esm_softc *ess)
830 1.1 rh {
831 1.1 rh unsigned freq = 0, freq2;
832 1.1 rh
833 1.1 rh if (ess->pactive)
834 1.1 rh freq = calc_timer_freq(&ess->pch);
835 1.1 rh
836 1.1 rh if (ess->ractive) {
837 1.1 rh freq2 = calc_timer_freq(&ess->rch);
838 1.1 rh if (freq2 < freq)
839 1.1 rh freq = freq2;
840 1.1 rh }
841 1.1 rh
842 1.1 rh for (; freq < MAESTRO_MINFREQ; freq <<= 1)
843 1.1 rh ;
844 1.1 rh
845 1.1 rh if (freq > 0)
846 1.1 rh wp_settimer(ess, freq);
847 1.1 rh }
848 1.1 rh
849 1.1 rh
850 1.1 rh static void
851 1.1 rh esmch_set_format(struct esm_chinfo *ch, struct audio_params *p)
852 1.1 rh {
853 1.1 rh u_int16_t wcreg_tpl = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
854 1.1 rh u_int16_t aputype = APUTYPE_16BITLINEAR;
855 1.1 rh
856 1.1 rh if (p->channels == 2) {
857 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_STEREO;
858 1.1 rh aputype++;
859 1.1 rh }
860 1.1 rh if (p->precision * p->factor == 8) {
861 1.1 rh aputype += 2;
862 1.1 rh if (p->encoding == AUDIO_ENCODING_ULINEAR)
863 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_U8;
864 1.1 rh }
865 1.1 rh ch->wcreg_tpl = wcreg_tpl;
866 1.1 rh ch->aputype = aputype;
867 1.1 rh ch->sample_rate = p->sample_rate;
868 1.1 rh
869 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esmch_set_format: "
870 1.1 rh "numch=%d, prec=%d*%d, tpl=0x%x, aputype=%d, rate=%ld\n",
871 1.1 rh p->channels, p->precision, p->factor, wcreg_tpl, aputype,
872 1.1 rh p->sample_rate));
873 1.1 rh }
874 1.1 rh
875 1.1 rh
876 1.1 rh /*
877 1.1 rh * Audio interface glue functions
878 1.1 rh */
879 1.1 rh
880 1.1 rh int
881 1.1 rh esm_open(void *sc, int flags)
882 1.1 rh {
883 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_open(%p, 0x%x)\n", sc, flags));
884 1.1 rh
885 1.1 rh return 0;
886 1.1 rh }
887 1.1 rh
888 1.1 rh
889 1.1 rh void
890 1.1 rh esm_close(void *sc)
891 1.1 rh {
892 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_close(%p)\n", sc));
893 1.1 rh }
894 1.1 rh
895 1.1 rh
896 1.1 rh int
897 1.1 rh esm_getdev (void *sc, struct audio_device *adp)
898 1.1 rh {
899 1.1 rh *adp = esm_device;
900 1.1 rh return 0;
901 1.1 rh }
902 1.1 rh
903 1.1 rh
904 1.1 rh int
905 1.1 rh esm_round_blocksize (void *sc, int blk)
906 1.1 rh {
907 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
908 1.1 rh ("esm_round_blocksize(%p, 0x%x)", sc, blk));
909 1.1 rh
910 1.1 rh blk &= ~0x3f; /* keep good alignment */
911 1.1 rh
912 1.1 rh DPRINTF(ESM_DEBUG_PARAM, (" = 0x%x\n", blk));
913 1.1 rh
914 1.1 rh return blk;
915 1.1 rh }
916 1.1 rh
917 1.1 rh
918 1.1 rh int
919 1.1 rh esm_query_encoding(void *sc, struct audio_encoding *fp)
920 1.1 rh {
921 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
922 1.1 rh ("esm_query_encoding(%p, %d)\n", sc, fp->index));
923 1.1 rh
924 1.1 rh if (fp->index < 0 || fp->index >= MAESTRO_NENCODINGS)
925 1.1 rh return EINVAL;
926 1.1 rh
927 1.1 rh *fp = esm_encoding[fp->index];
928 1.1 rh return 0;
929 1.1 rh }
930 1.1 rh
931 1.1 rh
932 1.1 rh int
933 1.1 rh esm_set_params(void *sc, int setmode, int usemode,
934 1.1 rh struct audio_params *play, struct audio_params *rec)
935 1.1 rh {
936 1.1 rh struct esm_softc *ess = sc;
937 1.1 rh struct audio_params *p;
938 1.1 rh int mode;
939 1.1 rh
940 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
941 1.1 rh ("esm_set_params(%p, 0x%x, 0x%x, %p, %p)\n",
942 1.1 rh sc, setmode, usemode, play, rec));
943 1.1 rh
944 1.1 rh for (mode = AUMODE_RECORD; mode != -1;
945 1.1 rh mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
946 1.1 rh if ((setmode & mode) == 0)
947 1.1 rh continue;
948 1.1 rh
949 1.1 rh p = mode == AUMODE_PLAY ? play : rec;
950 1.1 rh
951 1.1 rh if (p->sample_rate < 4000 || p->sample_rate > 48000 ||
952 1.1 rh (p->precision != 8 && p->precision != 16) ||
953 1.1 rh (p->channels != 1 && p->channels != 2))
954 1.1 rh return EINVAL;
955 1.1 rh
956 1.1 rh p->factor = 1;
957 1.1 rh p->sw_code = 0;
958 1.1 rh switch (p->encoding) {
959 1.1 rh case AUDIO_ENCODING_SLINEAR_BE:
960 1.1 rh if (p->precision == 16)
961 1.1 rh p->sw_code = swap_bytes;
962 1.1 rh else
963 1.1 rh p->sw_code = change_sign8;
964 1.1 rh break;
965 1.1 rh case AUDIO_ENCODING_SLINEAR_LE:
966 1.1 rh if (p->precision != 16)
967 1.1 rh p->sw_code = change_sign8;
968 1.1 rh break;
969 1.1 rh case AUDIO_ENCODING_ULINEAR_BE:
970 1.1 rh if (p->precision == 16) {
971 1.1 rh if (mode == AUMODE_PLAY)
972 1.1 rh p->sw_code = swap_bytes_change_sign16_le;
973 1.1 rh else
974 1.1 rh p->sw_code = change_sign16_swap_bytes_le;
975 1.1 rh }
976 1.1 rh break;
977 1.1 rh case AUDIO_ENCODING_ULINEAR_LE:
978 1.1 rh if (p->precision == 16)
979 1.1 rh p->sw_code = change_sign16_le;
980 1.1 rh break;
981 1.1 rh case AUDIO_ENCODING_ULAW:
982 1.1 rh if (mode == AUMODE_PLAY) {
983 1.1 rh p->factor = 2;
984 1.1 rh p->sw_code = mulaw_to_slinear16_le;
985 1.1 rh } else
986 1.1 rh p->sw_code = ulinear8_to_mulaw;
987 1.1 rh break;
988 1.1 rh case AUDIO_ENCODING_ALAW:
989 1.1 rh if (mode == AUMODE_PLAY) {
990 1.1 rh p->factor = 2;
991 1.1 rh p->sw_code = alaw_to_slinear16_le;
992 1.1 rh } else
993 1.1 rh p->sw_code = ulinear8_to_alaw;
994 1.1 rh break;
995 1.1 rh default:
996 1.1 rh return EINVAL;
997 1.1 rh }
998 1.1 rh }
999 1.1 rh
1000 1.1 rh if (setmode & AUMODE_PLAY)
1001 1.1 rh esmch_set_format(&ess->pch, play);
1002 1.1 rh
1003 1.1 rh if (setmode & AUMODE_RECORD)
1004 1.1 rh esmch_set_format(&ess->rch, rec);
1005 1.1 rh
1006 1.1 rh return 0;
1007 1.1 rh }
1008 1.1 rh
1009 1.1 rh
1010 1.1 rh int
1011 1.1 rh esm_set_port(void *sc, mixer_ctrl_t *cp)
1012 1.1 rh {
1013 1.1 rh struct esm_softc *ess = sc;
1014 1.1 rh
1015 1.1 rh return (ess->codec_if->vtbl->mixer_set_port(ess->codec_if, cp));
1016 1.1 rh }
1017 1.1 rh
1018 1.1 rh
1019 1.1 rh int
1020 1.1 rh esm_get_port(void *sc, mixer_ctrl_t *cp)
1021 1.1 rh {
1022 1.1 rh struct esm_softc *ess = sc;
1023 1.1 rh
1024 1.1 rh return (ess->codec_if->vtbl->mixer_get_port(ess->codec_if, cp));
1025 1.1 rh }
1026 1.1 rh
1027 1.1 rh
1028 1.1 rh int
1029 1.1 rh esm_query_devinfo(void *sc, mixer_devinfo_t *dip)
1030 1.1 rh {
1031 1.1 rh struct esm_softc *ess = sc;
1032 1.1 rh
1033 1.1 rh return (ess->codec_if->vtbl->query_devinfo(ess->codec_if, dip));
1034 1.1 rh }
1035 1.1 rh
1036 1.1 rh
1037 1.1 rh void *
1038 1.1 rh esm_malloc(void *sc, int direction, size_t size, int pool, int flags)
1039 1.1 rh {
1040 1.1 rh struct esm_softc *ess = sc;
1041 1.1 rh struct esm_dma *p;
1042 1.1 rh int error;
1043 1.1 rh
1044 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1045 1.1 rh ("esm_malloc(%p, %d, 0x%x, 0x%x, 0x%x)",
1046 1.1 rh sc, direction, size, pool, flags));
1047 1.1 rh
1048 1.1 rh p = malloc(sizeof(*p), pool, flags);
1049 1.1 rh if (!p)
1050 1.1 rh return 0;
1051 1.1 rh error = esm_allocmem(ess, size, 16, p);
1052 1.1 rh if (error) {
1053 1.1 rh free(p, pool);
1054 1.1 rh DPRINTF(ESM_DEBUG_DMA, (" = 0 (ENOMEM)\n"));
1055 1.1 rh return 0;
1056 1.1 rh }
1057 1.1 rh p->next = ess->sc_dmas;
1058 1.1 rh ess->sc_dmas = p;
1059 1.1 rh
1060 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1061 1.1 rh (": KERNADDR(%p) = %p (DMAADDR 0x%x)\n", p, KERNADDR(p), (int)DMAADDR(p)));
1062 1.1 rh
1063 1.1 rh return KERNADDR(p);
1064 1.1 rh }
1065 1.1 rh
1066 1.1 rh
1067 1.1 rh void
1068 1.1 rh esm_free(void *sc, void *ptr, int pool)
1069 1.1 rh {
1070 1.1 rh struct esm_softc *ess = sc;
1071 1.1 rh struct esm_dma *p, **pp;
1072 1.1 rh
1073 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1074 1.1 rh ("esm_free(%p, %p, 0x%x)\n",
1075 1.1 rh sc, ptr, pool));
1076 1.1 rh
1077 1.1 rh for (pp = &ess->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
1078 1.1 rh if (KERNADDR(p) == ptr) {
1079 1.1 rh esm_freemem(ess, p);
1080 1.1 rh *pp = p->next;
1081 1.1 rh free(p, pool);
1082 1.1 rh return;
1083 1.1 rh }
1084 1.1 rh }
1085 1.1 rh }
1086 1.1 rh
1087 1.1 rh
1088 1.1 rh size_t
1089 1.1 rh esm_round_buffersize(void *sc, int direction, size_t size)
1090 1.1 rh {
1091 1.1 rh return size;
1092 1.1 rh }
1093 1.1 rh
1094 1.1 rh
1095 1.1 rh paddr_t
1096 1.1 rh esm_mappage(void *sc, void *mem, off_t off, int prot)
1097 1.1 rh {
1098 1.1 rh struct esm_softc *ess = sc;
1099 1.1 rh struct esm_dma *p;
1100 1.1 rh
1101 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1102 1.1 rh ("esm_mappage(%p, %p, 0x%lx, 0x%x)\n",
1103 1.1 rh sc, mem, (unsigned long)off, prot));
1104 1.1 rh
1105 1.1 rh if (off < 0)
1106 1.1 rh return (-1);
1107 1.1 rh
1108 1.1 rh for (p = ess->sc_dmas; p && KERNADDR(p) != mem; p = p->next)
1109 1.1 rh ;
1110 1.1 rh if (!p)
1111 1.1 rh return (-1);
1112 1.1 rh return bus_dmamem_mmap(ess->dmat, p->segs, p->nsegs, off,
1113 1.1 rh prot, BUS_DMA_WAITOK);
1114 1.1 rh }
1115 1.1 rh
1116 1.1 rh
1117 1.1 rh int
1118 1.1 rh esm_get_props(void *sc)
1119 1.1 rh {
1120 1.1 rh return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1121 1.1 rh }
1122 1.1 rh
1123 1.1 rh
1124 1.1 rh /* -----------------------------
1125 1.1 rh * Bus space.
1126 1.1 rh */
1127 1.1 rh
1128 1.1 rh int
1129 1.1 rh esm_intr(void *sc)
1130 1.1 rh {
1131 1.1 rh struct esm_softc *ess = sc;
1132 1.1 rh u_int16_t status;
1133 1.1 rh u_int16_t pos;
1134 1.1 rh int ret = 0;
1135 1.1 rh
1136 1.1 rh status = bus_space_read_1(ess->st, ess->sh, PORT_HOSTINT_STAT);
1137 1.1 rh if (!status)
1138 1.1 rh return 0;
1139 1.1 rh
1140 1.1 rh /* Acknowledge all. */
1141 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
1142 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HOSTINT_STAT, 0);
1143 1.1 rh #if 0 /* XXX - HWVOL */
1144 1.1 rh if (status & HOSTINT_STAT_HWVOL) {
1145 1.1 rh u_int delta;
1146 1.1 rh delta = bus_space_read_1(ess->st, ess->sh, PORT_HWVOL_MASTER)
1147 1.1 rh - 0x88;
1148 1.1 rh if (delta & 0x11)
1149 1.1 rh mixer_set(device_get_softc(ess->dev),
1150 1.1 rh SOUND_MIXER_VOLUME, 0);
1151 1.1 rh else {
1152 1.1 rh mixer_set(device_get_softc(ess->dev),
1153 1.1 rh SOUND_MIXER_VOLUME,
1154 1.1 rh mixer_get(device_get_softc(ess->dev),
1155 1.1 rh SOUND_MIXER_VOLUME)
1156 1.1 rh + ((delta >> 5) & 0x7) - 4
1157 1.1 rh + ((delta << 7) & 0x700) - 0x400);
1158 1.1 rh }
1159 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HWVOL_MASTER, 0x88);
1160 1.1 rh ret++;
1161 1.1 rh }
1162 1.1 rh #endif /* XXX - HWVOL */
1163 1.1 rh
1164 1.1 rh if (ess->pactive) {
1165 1.1 rh pos = wp_rdapu(ess, ess->pch.num << 1, APUREG_CURPTR);
1166 1.1 rh
1167 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
1168 1.1 rh wp_rdapu(ess, (ess->pch.num<<1)+1, APUREG_CURPTR)));
1169 1.1 rh
1170 1.1 rh if (pos >= ess->pch.nextirq &&
1171 1.1 rh pos - ess->pch.nextirq < ess->pch.apubuf / 2) {
1172 1.1 rh ess->pch.nextirq += ess->pch.apublk;
1173 1.1 rh
1174 1.1 rh if (ess->pch.nextirq >= ess->pch.apubuf)
1175 1.1 rh ess->pch.nextirq = 0;
1176 1.1 rh
1177 1.1 rh if (ess->sc_pintr) {
1178 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("P\n"));
1179 1.1 rh ess->sc_pintr(ess->sc_parg);
1180 1.1 rh }
1181 1.1 rh
1182 1.1 rh }
1183 1.1 rh ret++;
1184 1.1 rh }
1185 1.1 rh
1186 1.1 rh if (ess->ractive) {
1187 1.1 rh pos = wp_rdapu(ess, ess->rch.num << 1, APUREG_CURPTR);
1188 1.1 rh
1189 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
1190 1.1 rh wp_rdapu(ess, (ess->rch.num<<1)+1, APUREG_CURPTR)));
1191 1.1 rh
1192 1.1 rh if (pos >= ess->rch.nextirq &&
1193 1.1 rh pos - ess->rch.nextirq < ess->rch.apubuf / 2) {
1194 1.1 rh ess->rch.nextirq += ess->rch.apublk;
1195 1.1 rh
1196 1.1 rh if (ess->rch.nextirq >= ess->rch.apubuf)
1197 1.1 rh ess->rch.nextirq = 0;
1198 1.1 rh
1199 1.1 rh if (ess->sc_rintr) {
1200 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("R\n"));
1201 1.1 rh ess->sc_rintr(ess->sc_parg);
1202 1.1 rh }
1203 1.1 rh
1204 1.1 rh }
1205 1.1 rh ret++;
1206 1.1 rh }
1207 1.1 rh
1208 1.1 rh return ret;
1209 1.1 rh }
1210 1.1 rh
1211 1.1 rh
1212 1.1 rh int
1213 1.1 rh esm_allocmem(struct esm_softc *sc, size_t size, size_t align,
1214 1.1 rh struct esm_dma *p)
1215 1.1 rh {
1216 1.1 rh int error;
1217 1.1 rh
1218 1.1 rh p->size = size;
1219 1.1 rh error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
1220 1.1 rh p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
1221 1.1 rh &p->nsegs, BUS_DMA_NOWAIT);
1222 1.1 rh if (error)
1223 1.1 rh return error;
1224 1.1 rh
1225 1.1 rh error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
1226 1.1 rh &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
1227 1.1 rh if (error)
1228 1.1 rh goto free;
1229 1.1 rh
1230 1.1 rh error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
1231 1.1 rh 0, BUS_DMA_NOWAIT, &p->map);
1232 1.1 rh if (error)
1233 1.1 rh goto unmap;
1234 1.1 rh
1235 1.1 rh error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
1236 1.1 rh BUS_DMA_NOWAIT);
1237 1.1 rh if (error)
1238 1.1 rh goto destroy;
1239 1.1 rh
1240 1.1 rh return 0;
1241 1.1 rh
1242 1.1 rh destroy:
1243 1.1 rh bus_dmamap_destroy(sc->dmat, p->map);
1244 1.1 rh unmap:
1245 1.1 rh bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1246 1.1 rh free:
1247 1.1 rh bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1248 1.1 rh
1249 1.1 rh return error;
1250 1.1 rh }
1251 1.1 rh
1252 1.1 rh
1253 1.1 rh int
1254 1.1 rh esm_freemem(struct esm_softc *sc, struct esm_dma *p)
1255 1.1 rh {
1256 1.1 rh bus_dmamap_unload(sc->dmat, p->map);
1257 1.1 rh bus_dmamap_destroy(sc->dmat, p->map);
1258 1.1 rh bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1259 1.1 rh bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1260 1.1 rh return 0;
1261 1.1 rh }
1262 1.1 rh
1263 1.1 rh
1264 1.1 rh int
1265 1.1 rh esm_match(struct device *dev, struct cfdata *match, void *aux)
1266 1.1 rh {
1267 1.1 rh struct pci_attach_args *pa = (struct pci_attach_args *) aux;
1268 1.1 rh
1269 1.1 rh switch (PCI_VENDOR(pa->pa_id)) {
1270 1.1 rh case PCI_VENDOR_ESSTECH:
1271 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) {
1272 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO1:
1273 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2:
1274 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2E:
1275 1.1 rh return 1;
1276 1.1 rh }
1277 1.1 rh
1278 1.1 rh case PCI_VENDOR_ESSTECH2:
1279 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) {
1280 1.1 rh case PCI_PRODUCT_ESSTECH2_MAESTRO1:
1281 1.1 rh return 1;
1282 1.1 rh }
1283 1.1 rh }
1284 1.1 rh return 0;
1285 1.1 rh }
1286 1.1 rh
1287 1.1 rh void
1288 1.1 rh esm_attach(struct device *parent, struct device *self, void *aux)
1289 1.1 rh {
1290 1.1 rh struct esm_softc *ess = (struct esm_softc *)self;
1291 1.1 rh struct pci_attach_args *pa = (struct pci_attach_args *)aux;
1292 1.1 rh pci_chipset_tag_t pc = pa->pa_pc;
1293 1.1 rh pcitag_t tag = pa->pa_tag;
1294 1.1 rh pci_intr_handle_t ih;
1295 1.1 rh pcireg_t csr, data;
1296 1.1 rh u_int16_t codec_data;
1297 1.1 rh const char *intrstr;
1298 1.1 rh int revision;
1299 1.1 rh char devinfo[256];
1300 1.1 rh
1301 1.1 rh pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
1302 1.1 rh revision = PCI_REVISION(pa->pa_class);
1303 1.1 rh printf(": %s (rev. 0x%02x)\n", devinfo, revision);
1304 1.1 rh
1305 1.1 rh /* Enable the device. */
1306 1.1 rh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
1307 1.1 rh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
1308 1.1 rh csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
1309 1.1 rh
1310 1.1 rh /* Map I/O register */
1311 1.1 rh if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
1312 1.1 rh &ess->st, &ess->sh, NULL, NULL)) {
1313 1.1 rh printf("%s: can't map i/o space\n", ess->sc_dev.dv_xname);
1314 1.1 rh return;
1315 1.1 rh }
1316 1.1 rh
1317 1.1 rh /* Initialize softc */
1318 1.1 rh ess->pch.num = 0;
1319 1.1 rh ess->rch.num = 2;
1320 1.1 rh ess->dmat = pa->pa_dmat;
1321 1.1 rh ess->tag = tag;
1322 1.1 rh ess->pc = pc;
1323 1.1 rh ess->subid = pci_conf_read(pc, tag, PCI_SUBSYS_ID_REG);
1324 1.1 rh
1325 1.3 rh DPRINTF(ESM_DEBUG_PCI,
1326 1.3 rh ("%s: sub-system vendor 0x%4.4x, product 0x%4.4x\n",
1327 1.3 rh ess->sc_dev.dv_xname,
1328 1.3 rh PCI_VENDOR(ess->subid), PCI_PRODUCT(ess->subid)));
1329 1.3 rh
1330 1.1 rh /* Map and establish the interrupt. */
1331 1.1 rh if (pci_intr_map(pa, &ih)) {
1332 1.1 rh printf("%s: can't map interrupt\n", ess->sc_dev.dv_xname);
1333 1.1 rh return;
1334 1.1 rh }
1335 1.1 rh intrstr = pci_intr_string(pc, ih);
1336 1.1 rh ess->ih = pci_intr_establish(pc, ih, IPL_AUDIO, esm_intr, self);
1337 1.1 rh if (ess->ih == NULL) {
1338 1.1 rh printf("%s: can't establish interrupt", ess->sc_dev.dv_xname);
1339 1.1 rh if (intrstr != NULL)
1340 1.1 rh printf(" at %s", intrstr);
1341 1.1 rh printf("\n");
1342 1.1 rh return;
1343 1.1 rh }
1344 1.1 rh printf("%s: interrupting at %s\n", ess->sc_dev.dv_xname, intrstr);
1345 1.1 rh
1346 1.1 rh /*
1347 1.1 rh * Setup PCI config registers
1348 1.1 rh */
1349 1.1 rh
1350 1.1 rh /* set to power state D0 */
1351 1.1 rh esm_power(ess, PPMI_D0);
1352 1.1 rh delay(100000);
1353 1.1 rh
1354 1.1 rh /* Disable all legacy emulations. */
1355 1.1 rh data = pci_conf_read(pc, tag, CONF_LEGACY);
1356 1.1 rh pci_conf_write(pc, tag, CONF_LEGACY, data | LEGACY_DISABLED);
1357 1.1 rh
1358 1.1 rh /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
1359 1.1 rh * Enable posted write.
1360 1.1 rh * Prefer PCI timing rather than that of ISA.
1361 1.1 rh * Don't swap L/R. */
1362 1.1 rh data = pci_conf_read(pc, tag, CONF_MAESTRO);
1363 1.1 rh data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
1364 1.1 rh data &= ~MAESTRO_SWAP_LR;
1365 1.1 rh pci_conf_write(pc, tag, CONF_MAESTRO, data);
1366 1.1 rh
1367 1.1 rh /* initialize sound chip */
1368 1.1 rh esm_init(ess);
1369 1.1 rh
1370 1.1 rh esm_read_codec(ess, 0, &codec_data);
1371 1.1 rh if (codec_data == 0x80) {
1372 1.1 rh printf("%s: PT101 codec detected!\n", ess->sc_dev.dv_xname);
1373 1.1 rh return;
1374 1.1 rh }
1375 1.1 rh
1376 1.3 rh /*
1377 1.3 rh * Some cards and Notebooks appear to have left and right channels
1378 1.3 rh * reversed. Check if there is a corresponding quirk entry for
1379 1.3 rh * the subsystem vendor and product and if so, set the appropriate
1380 1.3 rh * codec flag.
1381 1.3 rh */
1382 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_SWAPPEDCH) {
1383 1.3 rh ess->codec_flags |= AC97_HOST_SWAPPED_CHANNELS;
1384 1.3 rh }
1385 1.3 rh
1386 1.1 rh /* initialize AC97 host interface */
1387 1.1 rh ess->host_if.arg = self;
1388 1.1 rh ess->host_if.attach = esm_attach_codec;
1389 1.1 rh ess->host_if.read = esm_read_codec;
1390 1.1 rh ess->host_if.write = esm_write_codec;
1391 1.1 rh ess->host_if.reset = esm_reset_codec;
1392 1.3 rh ess->host_if.flags = esm_flags_codec;
1393 1.1 rh
1394 1.1 rh if (ac97_attach(&ess->host_if) != 0)
1395 1.1 rh return;
1396 1.1 rh
1397 1.1 rh audio_attach_mi(&esm_hw_if, self, &ess->sc_dev);
1398 1.1 rh }
1399 1.1 rh
1400 1.1 rh #if 0
1401 1.1 rh int
1402 1.1 rh esm_suspend(struct esm_softc *ess)
1403 1.1 rh {
1404 1.1 rh int i, x;
1405 1.1 rh
1406 1.1 rh x = splaudio();
1407 1.1 rh wp_stoptimer(ess);
1408 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1409 1.1 rh
1410 1.1 rh esm_halt_output(ess);
1411 1.1 rh esm_halt_input(ess);
1412 1.1 rh splx(x);
1413 1.1 rh
1414 1.1 rh /* Power down everything except clock. */
1415 1.1 rh esm_write_codec(ess, AC97_REG_POWER, 0xdf00);
1416 1.1 rh delay(20);
1417 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
1418 1.1 rh delay(1);
1419 1.1 rh esm_power(ess, PPMI_D3);
1420 1.1 rh
1421 1.1 rh return 0;
1422 1.1 rh }
1423 1.1 rh
1424 1.1 rh
1425 1.1 rh int
1426 1.1 rh esm_resume(struct esm_softc *ess)
1427 1.1 rh {
1428 1.1 rh int i, x;
1429 1.1 rh
1430 1.1 rh esm_power(ess, PPMI_D0);
1431 1.1 rh delay(100000);
1432 1.1 rh esm_init(ess);
1433 1.1 rh if (mixer_reinit(dev)) {
1434 1.1 rh printf("%s: unable to reinitialize the mixer\n",
1435 1.1 rh ess->sc_dev.dv_xname);
1436 1.1 rh return ENXIO;
1437 1.1 rh }
1438 1.1 rh
1439 1.1 rh x = splaudio();
1440 1.1 rh if (ess->pactive)
1441 1.1 rh esm_start_output(ess);
1442 1.1 rh if (ess->ractive)
1443 1.1 rh esm_start_input(ess);
1444 1.1 rh if (ess->pactive || ess->ractive) {
1445 1.1 rh set_timer(ess);
1446 1.1 rh wp_starttimer(ess);
1447 1.1 rh }
1448 1.1 rh splx(x);
1449 1.1 rh return 0;
1450 1.1 rh }
1451 1.1 rh
1452 1.1 rh
1453 1.1 rh int
1454 1.1 rh esm_shutdown(struct esm_softc *ess)
1455 1.1 rh {
1456 1.1 rh int i;
1457 1.1 rh
1458 1.1 rh wp_stoptimer(ess);
1459 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1460 1.1 rh
1461 1.1 rh esm_halt_output(ess);
1462 1.1 rh esm_halt_input(ess);
1463 1.1 rh
1464 1.1 rh return 0;
1465 1.1 rh }
1466 1.1 rh #endif
1467