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esm.c revision 1.51
      1  1.51     njoly /*      $NetBSD: esm.c,v 1.51 2009/11/26 15:17:09 njoly Exp $      */
      2   1.1        rh 
      3   1.1        rh /*-
      4  1.18  fredette  * Copyright (c) 2002, 2003 Matt Fredette
      5  1.18  fredette  * All rights reserved.
      6  1.18  fredette  *
      7  1.23    keihan  * Copyright (c) 2000, 2001 Rene Hexel <rh (at) NetBSD.org>
      8   1.1        rh  * All rights reserved.
      9   1.1        rh  *
     10   1.1        rh  * Copyright (c) 2000 Taku YAMAMOTO <taku (at) cent.saitama-u.ac.jp>
     11   1.1        rh  * All rights reserved.
     12   1.1        rh  *
     13   1.1        rh  * Redistribution and use in source and binary forms, with or without
     14   1.1        rh  * modification, are permitted provided that the following conditions
     15   1.1        rh  * are met:
     16   1.1        rh  * 1. Redistributions of source code must retain the above copyright
     17   1.1        rh  *    notice, this list of conditions and the following disclaimer.
     18   1.1        rh  * 2. Redistributions in binary form must reproduce the above copyright
     19   1.1        rh  *    notice, this list of conditions and the following disclaimer in the
     20   1.1        rh  *    documentation and/or other materials provided with the distribution.
     21   1.1        rh  *
     22   1.1        rh  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     23   1.1        rh  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24   1.1        rh  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25   1.1        rh  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     26   1.1        rh  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27   1.1        rh  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28   1.1        rh  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29   1.1        rh  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30   1.1        rh  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31   1.1        rh  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32   1.1        rh  * SUCH DAMAGE.
     33   1.1        rh  *
     34   1.1        rh  * Taku Id: maestro.c,v 1.12 2000/09/06 03:32:34 taku Exp
     35   1.1        rh  * FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.4 2000/12/18 01:36:35 cg Exp
     36   1.1        rh  */
     37   1.1        rh 
     38   1.1        rh /*
     39   1.1        rh  * TODO:
     40   1.1        rh  *	- hardware volume support
     41  1.18  fredette  *	- fix 16-bit stereo recording, add 8-bit recording
     42   1.1        rh  *	- MIDI support
     43   1.1        rh  *	- joystick support
     44   1.1        rh  *
     45   1.1        rh  *
     46   1.1        rh  * Credits:
     47   1.1        rh  *
     48   1.1        rh  * This code is based on the FreeBSD driver written by Taku YAMAMOTO
     49   1.1        rh  *
     50   1.1        rh  *
     51   1.1        rh  * Original credits from the FreeBSD driver:
     52   1.1        rh  *
     53   1.1        rh  * Part of this code (especially in many magic numbers) was heavily inspired
     54   1.1        rh  * by the Linux driver originally written by
     55   1.1        rh  * Alan Cox <alan.cox (at) linux.org>, modified heavily by
     56   1.1        rh  * Zach Brown <zab (at) zabbo.net>.
     57   1.1        rh  *
     58   1.1        rh  * busdma()-ize and buffer size reduction were suggested by
     59   1.1        rh  * Cameron Grant <gandalf (at) vilnya.demon.co.uk>.
     60   1.1        rh  * Also he showed me the way to use busdma() suite.
     61   1.1        rh  *
     62   1.1        rh  * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
     63   1.1        rh  * were looked at by
     64   1.1        rh  * Munehiro Matsuda <haro (at) tk.kubota.co.jp>,
     65   1.1        rh  * who brought patches based on the Linux driver with some simplification.
     66   1.1        rh  */
     67  1.12     lukem 
     68  1.12     lukem #include <sys/cdefs.h>
     69  1.51     njoly __KERNEL_RCSID(0, "$NetBSD: esm.c,v 1.51 2009/11/26 15:17:09 njoly Exp $");
     70   1.1        rh 
     71   1.1        rh #include <sys/param.h>
     72   1.1        rh #include <sys/systm.h>
     73   1.1        rh #include <sys/kernel.h>
     74   1.1        rh #include <sys/malloc.h>
     75   1.1        rh #include <sys/device.h>
     76   1.1        rh 
     77  1.43        ad #include <sys/bus.h>
     78   1.1        rh 
     79   1.1        rh #include <sys/audioio.h>
     80   1.1        rh #include <dev/audio_if.h>
     81   1.1        rh #include <dev/mulaw.h>
     82   1.1        rh #include <dev/auconv.h>
     83   1.1        rh #include <dev/ic/ac97var.h>
     84   1.8    ichiro #include <dev/ic/ac97reg.h>
     85   1.1        rh 
     86   1.1        rh #include <dev/pci/pcidevs.h>
     87   1.1        rh #include <dev/pci/pcivar.h>
     88   1.1        rh 
     89   1.1        rh #include <dev/pci/esmreg.h>
     90   1.1        rh #include <dev/pci/esmvar.h>
     91   1.1        rh 
     92   1.1        rh #define	PCI_CBIO		0x10	/* Configuration Base I/O Address */
     93   1.1        rh 
     94   1.1        rh /* Debug */
     95   1.1        rh #ifdef AUDIO_DEBUG
     96   1.1        rh #define DPRINTF(l,x)	do { if (esm_debug & (l)) printf x; } while(0)
     97   1.1        rh #define DUMPREG(x)	do { if (esm_debug & ESM_DEBUG_REG)	\
     98   1.1        rh 				 esm_dump_regs(x); } while(0)
     99   1.1        rh int esm_debug = 0xfffc;
    100   1.1        rh #define ESM_DEBUG_CODECIO	0x0001
    101   1.1        rh #define ESM_DEBUG_IRQ		0x0002
    102   1.1        rh #define ESM_DEBUG_DMA		0x0004
    103   1.1        rh #define ESM_DEBUG_TIMER		0x0008
    104   1.1        rh #define ESM_DEBUG_REG		0x0010
    105   1.1        rh #define ESM_DEBUG_PARAM		0x0020
    106   1.1        rh #define ESM_DEBUG_APU		0x0040
    107   1.1        rh #define ESM_DEBUG_CODEC		0x0080
    108   1.3        rh #define ESM_DEBUG_PCI		0x0100
    109   1.8    ichiro #define ESM_DEBUG_RESUME	0x0200
    110   1.1        rh #else
    111   1.1        rh #define DPRINTF(x,y)	/* nothing */
    112   1.1        rh #define DUMPREG(x)	/* nothing */
    113   1.1        rh #endif
    114   1.1        rh 
    115   1.1        rh #ifdef DIAGNOSTIC
    116   1.1        rh #define RANGE(n, l, h)	if ((n) < (l) || (n) >= (h))			\
    117   1.1        rh 		printf (#n "=%d out of range (%d, %d) in "		\
    118   1.1        rh 		__FILE__ ", line %d\n", (n), (l), (h), __LINE__)
    119   1.1        rh #else
    120   1.1        rh #define RANGE(x,y,z)	/* nothing */
    121   1.1        rh #endif
    122   1.1        rh 
    123  1.32     perry #define inline inline
    124   1.1        rh 
    125  1.30      kent static inline void	ringbus_setdest(struct esm_softc *, int, int);
    126   1.1        rh 
    127  1.30      kent static inline uint16_t	wp_rdreg(struct esm_softc *, uint16_t);
    128  1.30      kent static inline void	wp_wrreg(struct esm_softc *, uint16_t, uint16_t);
    129  1.30      kent static inline uint16_t	wp_rdapu(struct esm_softc *, int, uint16_t);
    130  1.30      kent static inline void	wp_wrapu(struct esm_softc *, int, uint16_t,
    131  1.30      kent 			    uint16_t);
    132   1.1        rh static inline void	wp_settimer(struct esm_softc *, u_int);
    133   1.1        rh static inline void	wp_starttimer(struct esm_softc *);
    134   1.1        rh static inline void	wp_stoptimer(struct esm_softc *);
    135   1.1        rh 
    136  1.30      kent static inline uint16_t	wc_rdreg(struct esm_softc *, uint16_t);
    137  1.30      kent static inline void	wc_wrreg(struct esm_softc *, uint16_t, uint16_t);
    138  1.30      kent static inline uint16_t	wc_rdchctl(struct esm_softc *, int);
    139  1.30      kent static inline void	wc_wrchctl(struct esm_softc *, int, uint16_t);
    140   1.1        rh 
    141   1.1        rh static inline u_int	calc_timer_freq(struct esm_chinfo*);
    142   1.1        rh static void		set_timer(struct esm_softc *);
    143   1.1        rh 
    144   1.1        rh static void		esmch_set_format(struct esm_chinfo *,
    145  1.29      kent 			    const audio_params_t *);
    146  1.18  fredette static void		esmch_combine_input(struct esm_softc *,
    147  1.29      kent 			    struct esm_chinfo *);
    148   1.1        rh 
    149  1.45    dyoung static bool		esm_suspend(device_t PMF_FN_PROTO);
    150  1.45    dyoung static bool		esm_resume(device_t PMF_FN_PROTO);
    151  1.45    dyoung static void		esm_childdet(device_t, device_t);
    152  1.48    cegger static int		esm_match(device_t, cfdata_t, void *);
    153  1.45    dyoung static void		esm_attach(device_t, device_t, void *);
    154  1.45    dyoung static int		esm_detach(device_t, int);
    155  1.45    dyoung static int		esm_intr(void *);
    156  1.45    dyoung 
    157  1.45    dyoung static void		esm_freemem(struct esm_softc *, struct esm_dma *);
    158  1.45    dyoung static int		esm_allocmem(struct esm_softc *, size_t, size_t,
    159  1.45    dyoung 			             struct esm_dma *);
    160   1.7    ichiro 
    161  1.45    dyoung 
    162  1.49    cegger CFATTACH_DECL2_NEW(esm, sizeof(struct esm_softc),
    163  1.45    dyoung     esm_match, esm_attach, esm_detach, NULL, NULL, esm_childdet);
    164   1.1        rh 
    165  1.28      yamt const struct audio_hw_if esm_hw_if = {
    166  1.29      kent 	NULL,				/* open */
    167  1.29      kent 	NULL,				/* close */
    168   1.1        rh 	NULL,				/* drain */
    169   1.1        rh 	esm_query_encoding,
    170   1.1        rh 	esm_set_params,
    171   1.1        rh 	esm_round_blocksize,
    172   1.1        rh 	NULL,				/* commit_settings */
    173   1.1        rh 	esm_init_output,
    174  1.18  fredette 	esm_init_input,
    175   1.1        rh 	NULL,				/* start_output */
    176   1.1        rh 	NULL,				/* start_input */
    177   1.1        rh 	esm_halt_output,
    178   1.1        rh 	esm_halt_input,
    179   1.1        rh 	NULL,				/* speaker_ctl */
    180   1.1        rh 	esm_getdev,
    181   1.1        rh 	NULL,				/* getfd */
    182   1.1        rh 	esm_set_port,
    183   1.1        rh 	esm_get_port,
    184   1.1        rh 	esm_query_devinfo,
    185   1.1        rh 	esm_malloc,
    186   1.1        rh 	esm_free,
    187   1.1        rh 	esm_round_buffersize,
    188   1.1        rh 	esm_mappage,
    189   1.1        rh 	esm_get_props,
    190   1.1        rh 	esm_trigger_output,
    191  1.11  augustss 	esm_trigger_input,
    192  1.11  augustss 	NULL,
    193  1.36  christos 	NULL,
    194   1.1        rh };
    195   1.1        rh 
    196   1.1        rh struct audio_device esm_device = {
    197   1.1        rh 	"ESS Maestro",
    198   1.1        rh 	"",
    199   1.1        rh 	"esm"
    200   1.1        rh };
    201   1.1        rh 
    202  1.30      kent #define MAESTRO_NENCODINGS 8
    203  1.30      kent static audio_encoding_t esm_encoding[MAESTRO_NENCODINGS] = {
    204  1.30      kent 	{ 0, AudioEulinear, AUDIO_ENCODING_ULINEAR, 8, 0 },
    205   1.1        rh 	{ 1, AudioEmulaw, AUDIO_ENCODING_ULAW, 8,
    206  1.30      kent 		AUDIO_ENCODINGFLAG_EMULATED },
    207  1.30      kent 	{ 2, AudioEalaw, AUDIO_ENCODING_ALAW, 8, AUDIO_ENCODINGFLAG_EMULATED },
    208  1.30      kent 	{ 3, AudioEslinear, AUDIO_ENCODING_SLINEAR, 8, 0 },
    209  1.30      kent 	{ 4, AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 16, 0 },
    210   1.1        rh 	{ 5, AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 16,
    211  1.30      kent 		AUDIO_ENCODINGFLAG_EMULATED },
    212   1.1        rh 	{ 6, AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 16,
    213  1.30      kent 		AUDIO_ENCODINGFLAG_EMULATED },
    214   1.1        rh 	{ 7, AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 16,
    215  1.30      kent 		AUDIO_ENCODINGFLAG_EMULATED },
    216   1.1        rh };
    217   1.1        rh 
    218  1.29      kent #define ESM_NFORMATS	4
    219  1.29      kent static const struct audio_format esm_formats[ESM_NFORMATS] = {
    220  1.29      kent 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
    221  1.29      kent 	 2, AUFMT_STEREO, 0, {4000, 48000}},
    222  1.29      kent 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
    223  1.29      kent 	 1, AUFMT_MONAURAL, 0, {4000, 48000}},
    224  1.29      kent 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR_LE, 8, 8,
    225  1.29      kent 	 2, AUFMT_STEREO, 0, {4000, 48000}},
    226  1.29      kent 	{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR_LE, 8, 8,
    227  1.29      kent 	 1, AUFMT_MONAURAL, 0, {4000, 48000}},
    228  1.29      kent };
    229   1.3        rh 
    230   1.3        rh static const struct esm_quirks esm_quirks[] = {
    231   1.3        rh 	/* COMPAL 38W2 OEM Notebook, e.g. Dell INSPIRON 5000e */
    232   1.3        rh 	{ PCI_VENDOR_COMPAL, PCI_PRODUCT_COMPAL_38W2, ESM_QUIRKF_SWAPPEDCH },
    233   1.3        rh 
    234   1.5        rh 	/* COMPAQ Armada M700 Notebook */
    235   1.5        rh 	{ PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_M700, ESM_QUIRKF_SWAPPEDCH },
    236   1.5        rh 
    237   1.3        rh 	/* NEC Versa Pro LX VA26D */
    238   1.3        rh 	{ PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VA26D, ESM_QUIRKF_GPIO },
    239   1.3        rh 
    240   1.3        rh 	/* NEC Versa LX */
    241   1.6        rh 	{ PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSALX, ESM_QUIRKF_GPIO },
    242   1.6        rh 
    243  1.10    simonb 	/* Toshiba Portege */
    244  1.10    simonb 	{ PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_PORTEGE, ESM_QUIRKF_SWAPPEDCH }
    245   1.3        rh };
    246   1.3        rh 
    247   1.3        rh enum esm_quirk_flags
    248   1.3        rh esm_get_quirks(pcireg_t subid)
    249   1.3        rh {
    250   1.3        rh 	int i;
    251   1.3        rh 
    252  1.50    cegger 	for (i = 0; i < __arraycount(esm_quirks); i++) {
    253   1.3        rh 		if (PCI_VENDOR(subid) == esm_quirks[i].eq_vendor &&
    254   1.3        rh 		    PCI_PRODUCT(subid) == esm_quirks[i].eq_product) {
    255   1.3        rh 			return esm_quirks[i].eq_quirks;
    256   1.3        rh 		}
    257   1.3        rh 	}
    258   1.3        rh 
    259   1.3        rh 	return 0;
    260   1.3        rh }
    261   1.3        rh 
    262   1.3        rh 
    263   1.1        rh #ifdef AUDIO_DEBUG
    264   1.1        rh struct esm_reg_info {
    265   1.1        rh 	int	offset;			/* register offset */
    266   1.1        rh 	int	width;			/* 1/2/4 bytes */
    267   1.1        rh } dump_regs[] = {
    268   1.1        rh 	{ PORT_WAVCACHE_CTRL,		2 },
    269   1.1        rh 	{ PORT_HOSTINT_CTRL,		2 },
    270   1.1        rh 	{ PORT_HOSTINT_STAT,		2 },
    271   1.1        rh 	{ PORT_HWVOL_VOICE_SHADOW,	1 },
    272   1.1        rh 	{ PORT_HWVOL_VOICE,		1 },
    273   1.1        rh 	{ PORT_HWVOL_MASTER_SHADOW,	1 },
    274   1.1        rh 	{ PORT_HWVOL_MASTER,		1 },
    275   1.1        rh 	{ PORT_RINGBUS_CTRL,		4 },
    276   1.1        rh 	{ PORT_GPIO_DATA,		2 },
    277   1.1        rh 	{ PORT_GPIO_MASK,		2 },
    278   1.1        rh 	{ PORT_GPIO_DIR,		2 },
    279   1.1        rh 	{ PORT_ASSP_CTRL_A,		1 },
    280   1.1        rh 	{ PORT_ASSP_CTRL_B,		1 },
    281   1.1        rh 	{ PORT_ASSP_CTRL_C,		1 },
    282   1.3        rh 	{ PORT_ASSP_INT_STAT,		1 }
    283   1.1        rh };
    284   1.1        rh 
    285   1.2     lukem static void
    286   1.2     lukem esm_dump_regs(struct esm_softc *ess)
    287   1.1        rh {
    288   1.3        rh 	int i;
    289   1.1        rh 
    290  1.49    cegger 	printf("%s registers:", device_xname(ess->sc_dev));
    291  1.50    cegger 	for (i = 0; i < __arraycount(dump_regs); i++) {
    292   1.1        rh 		if (i % 5 == 0)
    293   1.1        rh 			printf("\n");
    294   1.1        rh 		printf("0x%2.2x: ", dump_regs[i].offset);
    295   1.1        rh 		switch(dump_regs[i].width) {
    296   1.1        rh 		case 4:
    297   1.1        rh 			printf("%8.8x, ", bus_space_read_4(ess->st, ess->sh,
    298   1.1        rh 			    dump_regs[i].offset));
    299   1.1        rh 			break;
    300   1.1        rh 		case 2:
    301   1.1        rh 			printf("%4.4x,     ", bus_space_read_2(ess->st, ess->sh,
    302   1.1        rh 			    dump_regs[i].offset));
    303   1.1        rh 			break;
    304   1.1        rh 		default:
    305   1.1        rh 			printf("%2.2x,       ",
    306   1.1        rh 			    bus_space_read_1(ess->st, ess->sh,
    307   1.1        rh 			    dump_regs[i].offset));
    308   1.1        rh 		}
    309   1.1        rh 	}
    310   1.1        rh 	printf("\n");
    311   1.1        rh }
    312   1.1        rh #endif
    313   1.1        rh 
    314   1.3        rh 
    315   1.1        rh /* -----------------------------
    316   1.1        rh  * Subsystems.
    317   1.1        rh  */
    318   1.1        rh 
    319   1.1        rh /* Codec/Ringbus */
    320   1.1        rh 
    321   1.1        rh /* -------------------------------------------------------------------- */
    322   1.1        rh 
    323   1.1        rh int
    324  1.30      kent esm_read_codec(void *sc, uint8_t regno, uint16_t *result)
    325   1.1        rh {
    326  1.30      kent 	struct esm_softc *ess;
    327   1.1        rh 	unsigned t;
    328   1.1        rh 
    329  1.30      kent 	ess = sc;
    330   1.1        rh 	/* We have to wait for a SAFE time to write addr/data */
    331   1.1        rh 	for (t = 0; t < 20; t++) {
    332   1.1        rh 		if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
    333   1.1        rh 		    & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
    334   1.1        rh 			break;
    335   1.1        rh 		delay(2);	/* 20.8us / 13 */
    336   1.1        rh 	}
    337   1.1        rh 	if (t == 20)
    338   1.1        rh 		printf("%s: esm_read_codec() PROGLESS timed out.\n",
    339  1.49    cegger 		    device_xname(ess->sc_dev));
    340   1.1        rh 
    341   1.1        rh 	bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
    342   1.1        rh 	    CODEC_CMD_READ | regno);
    343   1.1        rh 	delay(21);	/* AC97 cycle = 20.8usec */
    344   1.1        rh 
    345   1.1        rh 	/* Wait for data retrieve */
    346   1.1        rh 	for (t = 0; t < 20; t++) {
    347   1.1        rh 		if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
    348   1.1        rh 		    & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE)
    349   1.1        rh 			break;
    350   1.1        rh 		delay(2);	/* 20.8us / 13 */
    351   1.1        rh 	}
    352   1.1        rh 	if (t == 20)
    353   1.1        rh 		/* Timed out, but perform dummy read. */
    354   1.1        rh 		printf("%s: esm_read_codec() RW_DONE timed out.\n",
    355  1.49    cegger 		    device_xname(ess->sc_dev));
    356   1.1        rh 
    357   1.1        rh 	*result = bus_space_read_2(ess->st, ess->sh, PORT_CODEC_REG);
    358   1.1        rh 
    359   1.1        rh 	return 0;
    360   1.1        rh }
    361   1.1        rh 
    362   1.1        rh int
    363  1.30      kent esm_write_codec(void *sc, uint8_t regno, uint16_t data)
    364   1.1        rh {
    365  1.30      kent 	struct esm_softc *ess;
    366   1.1        rh 	unsigned t;
    367   1.1        rh 
    368  1.30      kent 	ess = sc;
    369   1.1        rh 	/* We have to wait for a SAFE time to write addr/data */
    370   1.1        rh 	for (t = 0; t < 20; t++) {
    371   1.1        rh 		if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
    372   1.1        rh 		    & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
    373   1.1        rh 			break;
    374   1.1        rh 		delay(2);	/* 20.8us / 13 */
    375   1.1        rh 	}
    376   1.1        rh 	if (t == 20) {
    377   1.1        rh 		/* Timed out. Abort writing. */
    378   1.1        rh 		printf("%s: esm_write_codec() PROGLESS timed out.\n",
    379  1.49    cegger 		    device_xname(ess->sc_dev));
    380   1.1        rh 		return -1;
    381   1.1        rh 	}
    382   1.1        rh 
    383   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_CODEC_REG, data);
    384   1.1        rh 	bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
    385   1.1        rh 	    CODEC_CMD_WRITE | regno);
    386   1.1        rh 
    387   1.1        rh 	return 0;
    388   1.1        rh }
    389   1.1        rh 
    390   1.1        rh /* -------------------------------------------------------------------- */
    391   1.1        rh 
    392   1.1        rh static inline void
    393   1.1        rh ringbus_setdest(struct esm_softc *ess, int src, int dest)
    394   1.1        rh {
    395  1.30      kent 	uint32_t data;
    396   1.1        rh 
    397   1.1        rh 	data = bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL);
    398   1.1        rh 	data &= ~(0xfU << src);
    399   1.1        rh 	data |= (0xfU & dest) << src;
    400   1.1        rh 	bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, data);
    401   1.1        rh }
    402   1.1        rh 
    403   1.1        rh /* Wave Processor */
    404   1.1        rh 
    405  1.30      kent static inline uint16_t
    406  1.30      kent wp_rdreg(struct esm_softc *ess, uint16_t reg)
    407   1.1        rh {
    408  1.30      kent 
    409   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
    410   1.1        rh 	return bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA);
    411   1.1        rh }
    412   1.1        rh 
    413   1.1        rh static inline void
    414  1.30      kent wp_wrreg(struct esm_softc *ess, uint16_t reg, uint16_t data)
    415   1.1        rh {
    416  1.30      kent 
    417   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
    418   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
    419   1.1        rh }
    420   1.1        rh 
    421   1.1        rh static inline void
    422  1.30      kent apu_setindex(struct esm_softc *ess, uint16_t reg)
    423   1.1        rh {
    424   1.1        rh 	int t;
    425   1.1        rh 
    426   1.1        rh 	wp_wrreg(ess, WPREG_CRAM_PTR, reg);
    427   1.1        rh 	/* Sometimes WP fails to set apu register index. */
    428   1.1        rh 	for (t = 0; t < 1000; t++) {
    429   1.1        rh 		if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == reg)
    430   1.1        rh 			break;
    431   1.1        rh 		bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, reg);
    432   1.1        rh 	}
    433   1.1        rh 	if (t == 1000)
    434  1.49    cegger 		printf("%s: apu_setindex() timed out.\n", device_xname(ess->sc_dev));
    435   1.1        rh }
    436   1.1        rh 
    437  1.30      kent static inline uint16_t
    438  1.30      kent wp_rdapu(struct esm_softc *ess, int ch, uint16_t reg)
    439   1.1        rh {
    440  1.30      kent 	uint16_t ret;
    441   1.1        rh 
    442   1.1        rh 	apu_setindex(ess, ((unsigned)ch << 4) + reg);
    443   1.1        rh 	ret = wp_rdreg(ess, WPREG_DATA_PORT);
    444   1.1        rh 	return ret;
    445   1.1        rh }
    446   1.1        rh 
    447   1.1        rh static inline void
    448  1.30      kent wp_wrapu(struct esm_softc *ess, int ch, uint16_t reg, uint16_t data)
    449   1.1        rh {
    450   1.1        rh 	int t;
    451   1.1        rh 
    452   1.1        rh 	DPRINTF(ESM_DEBUG_APU,
    453   1.1        rh 	    ("wp_wrapu(%p, ch=%d, reg=0x%x, data=0x%04x)\n",
    454   1.1        rh 	    ess, ch, reg, data));
    455   1.1        rh 
    456   1.1        rh 	apu_setindex(ess, ((unsigned)ch << 4) + reg);
    457   1.1        rh 	wp_wrreg(ess, WPREG_DATA_PORT, data);
    458   1.1        rh 	for (t = 0; t < 1000; t++) {
    459   1.1        rh 		if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == data)
    460   1.1        rh 			break;
    461   1.1        rh 		bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
    462   1.1        rh 	}
    463   1.1        rh 	if (t == 1000)
    464  1.49    cegger 		printf("%s: wp_wrapu() timed out.\n", device_xname(ess->sc_dev));
    465   1.1        rh }
    466   1.1        rh 
    467   1.1        rh static inline void
    468   1.1        rh wp_settimer(struct esm_softc *ess, u_int freq)
    469   1.1        rh {
    470  1.30      kent 	u_int clock;
    471  1.30      kent 	u_int prescale, divide;
    472   1.1        rh 
    473  1.30      kent 	clock = 48000 << 2;
    474  1.30      kent 	prescale = 0;
    475  1.30      kent 	divide = (freq != 0) ? (clock / freq) : ~0;
    476   1.1        rh 	RANGE(divide, WPTIMER_MINDIV, WPTIMER_MAXDIV);
    477   1.1        rh 
    478   1.1        rh 	for (; divide > 32 << 1; divide >>= 1)
    479   1.1        rh 		prescale++;
    480   1.1        rh 	divide = (divide + 1) >> 1;
    481   1.1        rh 
    482   1.1        rh 	for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
    483   1.1        rh 		prescale++;
    484   1.1        rh 
    485   1.1        rh 	DPRINTF(ESM_DEBUG_TIMER,
    486   1.1        rh 	    ("wp_settimer(%p, %u): clock = %u, prescale = %u, divide = %u\n",
    487   1.1        rh 	    ess, freq, clock, prescale, divide));
    488   1.1        rh 
    489   1.1        rh 	wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
    490   1.1        rh 	wp_wrreg(ess, WPREG_TIMER_FREQ,
    491   1.1        rh 	    (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
    492   1.1        rh 	wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
    493   1.1        rh }
    494   1.1        rh 
    495   1.1        rh static inline void
    496   1.1        rh wp_starttimer(struct esm_softc *ess)
    497   1.1        rh {
    498  1.30      kent 
    499   1.1        rh 	wp_wrreg(ess, WPREG_TIMER_START, 1);
    500   1.1        rh }
    501   1.1        rh 
    502   1.1        rh static inline void
    503   1.1        rh wp_stoptimer(struct esm_softc *ess)
    504   1.1        rh {
    505  1.30      kent 
    506   1.1        rh 	wp_wrreg(ess, WPREG_TIMER_START, 0);
    507   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
    508   1.1        rh }
    509   1.1        rh 
    510   1.1        rh /* WaveCache */
    511   1.1        rh 
    512  1.30      kent static inline uint16_t
    513  1.30      kent wc_rdreg(struct esm_softc *ess, uint16_t reg)
    514   1.1        rh {
    515  1.30      kent 
    516   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
    517   1.1        rh 	return bus_space_read_2(ess->st, ess->sh, PORT_WAVCACHE_DATA);
    518   1.1        rh }
    519   1.1        rh 
    520   1.1        rh static inline void
    521  1.30      kent wc_wrreg(struct esm_softc *ess, uint16_t reg, uint16_t data)
    522   1.1        rh {
    523  1.30      kent 
    524   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
    525   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_DATA, data);
    526   1.1        rh }
    527   1.1        rh 
    528  1.30      kent static inline uint16_t
    529   1.1        rh wc_rdchctl(struct esm_softc *ess, int ch)
    530   1.1        rh {
    531  1.30      kent 
    532   1.1        rh 	return wc_rdreg(ess, ch << 3);
    533   1.1        rh }
    534   1.1        rh 
    535   1.1        rh static inline void
    536  1.30      kent wc_wrchctl(struct esm_softc *ess, int ch, uint16_t data)
    537   1.1        rh {
    538  1.30      kent 
    539   1.1        rh 	wc_wrreg(ess, ch << 3, data);
    540   1.1        rh }
    541   1.1        rh 
    542   1.1        rh /* -----------------------------
    543   1.1        rh  * Controller.
    544   1.1        rh  */
    545   1.1        rh 
    546   1.1        rh int
    547   1.1        rh esm_attach_codec(void *sc, struct ac97_codec_if *codec_if)
    548   1.1        rh {
    549  1.30      kent 	struct esm_softc *ess;
    550   1.1        rh 
    551  1.30      kent 	ess = sc;
    552   1.1        rh 	ess->codec_if = codec_if;
    553   1.1        rh 
    554   1.1        rh 	return 0;
    555   1.1        rh }
    556   1.1        rh 
    557  1.27      kent int
    558  1.41  christos esm_reset_codec(void *sc)
    559   1.1        rh {
    560  1.30      kent 
    561  1.27      kent 	return 0;
    562   1.1        rh }
    563   1.1        rh 
    564   1.1        rh 
    565   1.3        rh enum ac97_host_flags
    566   1.3        rh esm_flags_codec(void *sc)
    567   1.3        rh {
    568  1.30      kent 	struct esm_softc *ess;
    569   1.3        rh 
    570  1.30      kent 	ess = sc;
    571   1.3        rh 	return ess->codec_flags;
    572   1.3        rh }
    573   1.3        rh 
    574   1.3        rh 
    575   1.1        rh void
    576   1.1        rh esm_initcodec(struct esm_softc *ess)
    577   1.1        rh {
    578  1.30      kent 	uint16_t data;
    579   1.1        rh 
    580   1.1        rh 	DPRINTF(ESM_DEBUG_CODEC, ("esm_initcodec(%p)\n", ess));
    581   1.1        rh 
    582   1.1        rh 	if (bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL)
    583   1.1        rh 	    & RINGBUS_CTRL_ACLINK_ENABLED) {
    584   1.1        rh 		bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
    585   1.1        rh 		delay(104);	/* 20.8us * (4 + 1) */
    586   1.1        rh 	}
    587   1.1        rh 	/* XXX - 2nd codec should be looked at. */
    588   1.1        rh 	bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
    589   1.1        rh 	    RINGBUS_CTRL_AC97_SWRESET);
    590   1.1        rh 	delay(2);
    591   1.1        rh 	bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
    592   1.1        rh 	    RINGBUS_CTRL_ACLINK_ENABLED);
    593   1.1        rh 	delay(21);
    594   1.1        rh 
    595   1.1        rh 	esm_read_codec(ess, 0, &data);
    596   1.1        rh 	if (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
    597   1.1        rh 	    & CODEC_STAT_MASK) {
    598   1.1        rh 		bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
    599   1.1        rh 		delay(21);
    600   1.1        rh 
    601   1.1        rh 		/* Try cold reset. */
    602  1.49    cegger 		printf("%s: will perform cold reset.\n", device_xname(ess->sc_dev));
    603   1.1        rh 		data = bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR);
    604   1.1        rh 		if (pci_conf_read(ess->pc, ess->tag, 0x58) & 1)
    605   1.1        rh 			data |= 0x10;
    606   1.1        rh 		data |= 0x009 &
    607   1.1        rh 		    ~bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DATA);
    608   1.1        rh 		bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0xff6);
    609   1.1        rh 		bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
    610   1.1        rh 		    data | 0x009);
    611   1.1        rh 		bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x000);
    612   1.1        rh 		delay(2);
    613   1.1        rh 		bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x001);
    614   1.1        rh 		delay(1);
    615   1.1        rh 		bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x009);
    616   1.1        rh 		delay(500000);
    617   1.1        rh 		bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, data);
    618   1.1        rh 		delay(84);	/* 20.8us * 4 */
    619   1.1        rh 		bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
    620   1.1        rh 		    RINGBUS_CTRL_ACLINK_ENABLED);
    621   1.1        rh 		delay(21);
    622   1.1        rh 	}
    623   1.1        rh }
    624   1.1        rh 
    625   1.1        rh void
    626   1.1        rh esm_init(struct esm_softc *ess)
    627   1.1        rh {
    628  1.30      kent 
    629   1.1        rh 	/* Reset direct sound. */
    630   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
    631   1.1        rh 	    HOSTINT_CTRL_DSOUND_RESET);
    632   1.1        rh 	delay(10000);
    633   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
    634   1.1        rh 	delay(10000);
    635   1.1        rh 
    636   1.1        rh 	/* Enable direct sound interruption. */
    637   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
    638   1.1        rh 	    HOSTINT_CTRL_DSOUND_INT_ENABLED);
    639   1.1        rh 
    640   1.1        rh 	/* Setup Wave Processor. */
    641   1.1        rh 
    642   1.1        rh 	/* Enable WaveCache */
    643   1.1        rh 	wp_wrreg(ess, WPREG_WAVE_ROMRAM,
    644   1.1        rh 	    WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
    645   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_CTRL,
    646   1.1        rh 	    WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB);
    647   1.1        rh 
    648   1.1        rh 	/* Setup Codec/Ringbus. */
    649   1.1        rh 	esm_initcodec(ess);
    650   1.1        rh 	bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
    651   1.1        rh 	    RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED);
    652   1.1        rh 
    653  1.18  fredette 	/* Undocumented registers from the Linux driver. */
    654  1.18  fredette 	wp_wrreg(ess, 0x8, 0xB004);
    655  1.18  fredette 	wp_wrreg(ess, 0x9, 0x001B);
    656  1.18  fredette 	wp_wrreg(ess, 0xA, 0x8000);
    657  1.18  fredette 	wp_wrreg(ess, 0xB, 0x3F37);
    658  1.18  fredette 	wp_wrreg(ess, 0xD, 0x7632);
    659  1.18  fredette 
    660  1.18  fredette 	wp_wrreg(ess, WPREG_BASE, 0x8598);	/* Parallel I/O */
    661   1.1        rh 	ringbus_setdest(ess, RINGBUS_SRC_ADC,
    662   1.1        rh 	    RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
    663   1.1        rh 	ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
    664   1.1        rh 	    RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
    665   1.1        rh 
    666   1.1        rh 	/* Setup ASSP. Needed for Dell Inspiron 7500? */
    667   1.1        rh 	bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_B, 0x00);
    668   1.1        rh 	bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_A, 0x03);
    669   1.1        rh 	bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_C, 0x00);
    670   1.1        rh 
    671   1.1        rh 	/*
    672   1.1        rh 	 * Setup GPIO.
    673   1.1        rh 	 * There seems to be speciality with NEC systems.
    674   1.1        rh 	 */
    675   1.3        rh 	if (esm_get_quirks(ess->subid) & ESM_QUIRKF_GPIO) {
    676   1.3        rh 		bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK,
    677   1.3        rh 		    0x9ff);
    678   1.3        rh 		bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
    679   1.3        rh 		    bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR) |
    680   1.3        rh 			0x600);
    681   1.3        rh 		bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA,
    682   1.3        rh 		    0x200);
    683   1.1        rh 	}
    684   1.1        rh 
    685   1.1        rh 	DUMPREG(ess);
    686   1.1        rh }
    687   1.1        rh 
    688   1.1        rh /* Channel controller. */
    689   1.1        rh 
    690   1.1        rh int
    691  1.41  christos esm_init_output (void *sc, void *start, int size)
    692   1.1        rh {
    693  1.30      kent 	struct esm_softc *ess;
    694   1.1        rh 	struct esm_dma *p;
    695   1.1        rh 
    696  1.30      kent 	ess = sc;
    697  1.18  fredette 	p = &ess->sc_dma;
    698  1.42  christos 	if ((char *)start != (char *)p->addr + MAESTRO_PLAYBUF_OFF) {
    699   1.1        rh 		printf("%s: esm_init_output: bad addr %p\n",
    700  1.49    cegger 		    device_xname(ess->sc_dev), start);
    701   1.1        rh 		return EINVAL;
    702   1.1        rh 	}
    703   1.1        rh 
    704  1.18  fredette 	ess->pch.base = DMAADDR(p) + MAESTRO_PLAYBUF_OFF;
    705   1.1        rh 
    706   1.1        rh 	DPRINTF(ESM_DEBUG_DMA, ("%s: pch.base = 0x%x\n",
    707  1.49    cegger 		device_xname(ess->sc_dev), ess->pch.base));
    708   1.1        rh 
    709  1.18  fredette 	return 0;
    710  1.18  fredette }
    711  1.18  fredette 
    712  1.18  fredette int
    713  1.41  christos esm_init_input (void *sc, void *start, int size)
    714  1.18  fredette {
    715  1.30      kent 	struct esm_softc *ess;
    716  1.18  fredette 	struct esm_dma *p;
    717  1.18  fredette 
    718  1.30      kent 	ess = sc;
    719  1.18  fredette 	p = &ess->sc_dma;
    720  1.42  christos 	if ((char *)start != (char *)p->addr + MAESTRO_RECBUF_OFF) {
    721  1.18  fredette 		printf("%s: esm_init_input: bad addr %p\n",
    722  1.49    cegger 		    device_xname(ess->sc_dev), start);
    723  1.18  fredette 		return EINVAL;
    724  1.18  fredette 	}
    725  1.18  fredette 
    726  1.18  fredette 	switch (ess->rch.aputype) {
    727  1.18  fredette 	case APUTYPE_16BITSTEREO:
    728  1.18  fredette 		ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_L_OFF;
    729  1.18  fredette 		break;
    730  1.18  fredette 	default:
    731  1.18  fredette 		ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_OFF;
    732  1.18  fredette 		break;
    733  1.18  fredette 	}
    734  1.18  fredette 
    735  1.18  fredette 	DPRINTF(ESM_DEBUG_DMA, ("%s: rch.base = 0x%x\n",
    736  1.49    cegger 		device_xname(ess->sc_dev), ess->rch.base));
    737   1.1        rh 
    738   1.1        rh 	return 0;
    739   1.1        rh }
    740   1.1        rh 
    741   1.1        rh int
    742   1.1        rh esm_trigger_output(void *sc, void *start, void *end, int blksize,
    743  1.41  christos     void (*intr)(void *), void *arg, const audio_params_t *param)
    744   1.1        rh {
    745  1.30      kent 	size_t size;
    746  1.30      kent 	struct esm_softc *ess;
    747  1.30      kent 	struct esm_chinfo *ch;
    748   1.1        rh 	struct esm_dma *p;
    749  1.30      kent 	int pan, choffset;
    750  1.30      kent 	int i, nch;
    751  1.30      kent 	unsigned speed, offset, wpwa, dv;
    752  1.30      kent 	uint16_t apuch;
    753   1.1        rh 
    754   1.1        rh 	DPRINTF(ESM_DEBUG_DMA,
    755   1.1        rh 	    ("esm_trigger_output(%p, %p, %p, 0x%x, %p, %p, %p)\n",
    756   1.1        rh 	    sc, start, end, blksize, intr, arg, param));
    757  1.30      kent 	ess = sc;
    758  1.30      kent 	ch = &ess->pch;
    759  1.30      kent 	pan = 0;
    760  1.30      kent 	nch = 1;
    761  1.30      kent 	speed = ch->sample_rate;
    762  1.30      kent 	apuch = ch->num << 1;
    763   1.1        rh 
    764   1.1        rh #ifdef DIAGNOSTIC
    765   1.1        rh 	if (ess->pactive) {
    766   1.1        rh 		printf("%s: esm_trigger_output: already running",
    767  1.49    cegger 		    device_xname(ess->sc_dev));
    768   1.1        rh 		return EINVAL;
    769   1.1        rh 	}
    770   1.1        rh #endif
    771   1.1        rh 
    772   1.1        rh 	ess->sc_pintr = intr;
    773   1.1        rh 	ess->sc_parg = arg;
    774  1.18  fredette 	p = &ess->sc_dma;
    775  1.42  christos 	if ((char *)start != (char *)p->addr + MAESTRO_PLAYBUF_OFF) {
    776   1.1        rh 		printf("%s: esm_trigger_output: bad addr %p\n",
    777  1.49    cegger 		    device_xname(ess->sc_dev), start);
    778   1.1        rh 		return EINVAL;
    779   1.1        rh 	}
    780   1.1        rh 
    781   1.1        rh 	ess->pch.blocksize = blksize;
    782   1.1        rh 	ess->pch.apublk = blksize >> 1;
    783   1.1        rh 	ess->pactive = 1;
    784   1.1        rh 
    785  1.42  christos 	size = (size_t)(((char *)end - (char *)start) >> 1);
    786  1.18  fredette 	choffset = MAESTRO_PLAYBUF_OFF;
    787   1.1        rh 	offset = choffset >> 1;
    788  1.18  fredette 	wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK);
    789   1.1        rh 
    790   1.1        rh 	DPRINTF(ESM_DEBUG_DMA,
    791  1.26    kleink 	    ("choffs=0x%x, wpwa=0x%x, size=0x%lx words\n",
    792  1.26    kleink 	    choffset, wpwa, (unsigned long int)size));
    793   1.1        rh 
    794   1.1        rh 	switch (ch->aputype) {
    795   1.1        rh 	case APUTYPE_16BITSTEREO:
    796   1.1        rh 		ess->pch.apublk >>= 1;
    797   1.1        rh 		wpwa >>= 1;
    798   1.1        rh 		size >>= 1;
    799   1.1        rh 		offset >>= 1;
    800   1.1        rh 		/* FALLTHROUGH */
    801   1.1        rh 	case APUTYPE_8BITSTEREO:
    802   1.3        rh 		if (ess->codec_flags & AC97_HOST_SWAPPED_CHANNELS)
    803   1.3        rh 			pan = 8;
    804   1.3        rh 		else
    805   1.3        rh 			pan = -8;
    806   1.3        rh 		nch++;
    807   1.1        rh 		break;
    808   1.1        rh 	case APUTYPE_8BITLINEAR:
    809   1.1        rh 		ess->pch.apublk <<= 1;
    810   1.1        rh 		speed >>= 1;
    811   1.1        rh 		break;
    812   1.1        rh 	}
    813   1.1        rh 
    814  1.18  fredette 	ess->pch.apubase = offset;
    815   1.1        rh 	ess->pch.apubuf = size;
    816   1.1        rh 	ess->pch.nextirq = ess->pch.apublk;
    817   1.1        rh 
    818   1.1        rh 	set_timer(ess);
    819   1.1        rh 	wp_starttimer(ess);
    820   1.1        rh 
    821   1.1        rh 	dv = (((speed % 48000) << 16) + 24000) / 48000
    822   1.1        rh 	    + ((speed / 48000) << 16);
    823   1.1        rh 
    824   1.3        rh 	for (i = nch-1; i >= 0; i--) {
    825   1.3        rh 		wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa & 0xff00);
    826   1.3        rh 		wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset);
    827   1.3        rh 		wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size);
    828   1.3        rh 		wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1);
    829   1.3        rh 		wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800);
    830   1.3        rh 		wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00
    831   1.1        rh 		    | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
    832   1.1        rh 		    | ((PAN_FRONT + pan) << APU_PAN_SHIFT));
    833   1.3        rh 		wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB
    834   1.1        rh 		    | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
    835   1.3        rh 		wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8);
    836   1.1        rh 
    837   1.1        rh 		if (ch->aputype == APUTYPE_16BITSTEREO)
    838   1.1        rh 			wpwa |= APU_STEREO >> 1;
    839   1.1        rh 		pan = -pan;
    840   1.3        rh 	}
    841   1.1        rh 
    842   1.1        rh 	wc_wrchctl(ess, apuch, ch->wcreg_tpl);
    843   1.3        rh 	if (nch > 1)
    844   1.3        rh 		wc_wrchctl(ess, apuch + 1, ch->wcreg_tpl);
    845   1.1        rh 
    846   1.1        rh 	wp_wrapu(ess, apuch, APUREG_APUTYPE,
    847   1.1        rh 	    (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
    848   1.1        rh 	if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO)
    849   1.1        rh 		wp_wrapu(ess, apuch + 1, APUREG_APUTYPE,
    850   1.1        rh 		    (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
    851   1.1        rh 
    852   1.1        rh 	return 0;
    853   1.1        rh }
    854   1.1        rh 
    855   1.1        rh int
    856   1.1        rh esm_trigger_input(void *sc, void *start, void *end, int blksize,
    857  1.41  christos     void (*intr)(void *), void *arg, const audio_params_t *param)
    858   1.1        rh {
    859  1.18  fredette 	size_t size;
    860  1.18  fredette 	size_t mixsize;
    861  1.30      kent 	struct esm_softc *ess;
    862  1.30      kent 	struct esm_chinfo *ch;
    863  1.30      kent 	struct esm_dma *p;
    864  1.30      kent 	uint32_t chctl, choffset;
    865  1.30      kent 	uint32_t speed, offset, wpwa, dv;
    866  1.30      kent 	uint32_t mixoffset, mixdv;
    867  1.30      kent 	int i, nch;
    868  1.30      kent 	uint16_t apuch;
    869  1.30      kent 	uint16_t reg;
    870  1.18  fredette 
    871  1.18  fredette 	DPRINTF(ESM_DEBUG_DMA,
    872  1.18  fredette 	    ("esm_trigger_input(%p, %p, %p, 0x%x, %p, %p, %p)\n",
    873  1.18  fredette 	    sc, start, end, blksize, intr, arg, param));
    874  1.30      kent 	ess = sc;
    875  1.30      kent 	ch = &ess->rch;
    876  1.30      kent 	nch = 1;
    877  1.30      kent 	speed = ch->sample_rate;
    878  1.30      kent 	apuch = ch->num << 1;
    879  1.18  fredette 
    880  1.18  fredette #ifdef DIAGNOSTIC
    881  1.18  fredette 	if (ess->ractive) {
    882  1.18  fredette 		printf("%s: esm_trigger_input: already running",
    883  1.49    cegger 		    device_xname(ess->sc_dev));
    884  1.18  fredette 		return EINVAL;
    885  1.18  fredette 	}
    886  1.18  fredette #endif
    887  1.18  fredette 
    888  1.18  fredette 	ess->sc_rintr = intr;
    889  1.18  fredette 	ess->sc_rarg = arg;
    890  1.18  fredette 	p = &ess->sc_dma;
    891  1.42  christos 	if ((char *)start != (char *)p->addr + MAESTRO_RECBUF_OFF) {
    892  1.18  fredette 		printf("%s: esm_trigger_input: bad addr %p\n",
    893  1.49    cegger 		    device_xname(ess->sc_dev), start);
    894  1.18  fredette 		return EINVAL;
    895  1.18  fredette 	}
    896  1.18  fredette 
    897  1.42  christos 	ess->rch.buffer = (void *)start;
    898  1.18  fredette 	ess->rch.offset = 0;
    899  1.18  fredette 	ess->rch.blocksize = blksize;
    900  1.42  christos 	ess->rch.bufsize = ((char *)end - (char *)start);
    901  1.18  fredette 	ess->rch.apublk = blksize >> 1;
    902  1.18  fredette 	ess->ractive = 1;
    903  1.18  fredette 
    904  1.42  christos 	size = (size_t)(((char *)end - (char *)start) >> 1);
    905  1.18  fredette 	choffset = MAESTRO_RECBUF_OFF;
    906  1.18  fredette 	switch (ch->aputype) {
    907  1.18  fredette 	case APUTYPE_16BITSTEREO:
    908  1.18  fredette 		size >>= 1;
    909  1.18  fredette 		choffset = MAESTRO_RECBUF_L_OFF;
    910  1.18  fredette 		ess->rch.apublk >>= 1;
    911  1.18  fredette 		nch++;
    912  1.18  fredette 		break;
    913  1.18  fredette 	case APUTYPE_16BITLINEAR:
    914  1.18  fredette 		break;
    915  1.18  fredette 	default:
    916  1.18  fredette 		ess->ractive = 0;
    917  1.18  fredette 		return EINVAL;
    918  1.18  fredette 	}
    919  1.18  fredette 
    920  1.18  fredette 	mixsize = (MAESTRO_MIXBUF_SZ >> 1) >> 1;
    921  1.18  fredette 	mixoffset = MAESTRO_MIXBUF_OFF;
    922  1.18  fredette 
    923  1.18  fredette 	ess->rch.apubase = (choffset >> 1);
    924  1.18  fredette 	ess->rch.apubuf = size;
    925  1.18  fredette 	ess->rch.nextirq = ess->rch.apublk;
    926  1.18  fredette 
    927  1.18  fredette 	set_timer(ess);
    928  1.18  fredette 	wp_starttimer(ess);
    929  1.18  fredette 
    930  1.18  fredette 	if (speed > 47999) speed = 47999;
    931  1.18  fredette 	if (speed < 4000) speed = 4000;
    932  1.18  fredette 	dv = (((speed % 48000) << 16) + 24000) / 48000
    933  1.18  fredette 	    + ((speed / 48000) << 16);
    934  1.33     lukem 	mixdv = 65536;	/* 48 kHz */
    935  1.18  fredette 
    936  1.18  fredette 	for (i = 0; i < nch; i++) {
    937  1.18  fredette 
    938  1.18  fredette 		/* Clear all rate conversion WP channel registers first. */
    939  1.18  fredette 		for (reg = 0; reg < 15; reg++)
    940  1.18  fredette 			wp_wrapu(ess, apuch + i, reg, 0);
    941  1.18  fredette 
    942  1.18  fredette 		/* Program the WaveCache for the rate conversion WP channel. */
    943  1.18  fredette 		chctl = (DMAADDR(p) + choffset - 0x10) &
    944  1.18  fredette 		    WAVCACHE_CHCTL_ADDRTAG_MASK;
    945  1.18  fredette 		wc_wrchctl(ess, apuch + i, chctl);
    946  1.18  fredette 
    947  1.18  fredette 		/* Program the rate conversion WP channel. */
    948  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB
    949  1.18  fredette 		    | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT) | 0x08);
    950  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8);
    951  1.18  fredette 		offset = choffset >> 1;
    952  1.18  fredette 		wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK);
    953  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa);
    954  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset);
    955  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size);
    956  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1);
    957  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_EFFECTS_ENV, 0x00f0);
    958  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800);
    959  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00
    960  1.18  fredette 		    | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
    961  1.18  fredette 		    | (PAN_FRONT << APU_PAN_SHIFT));
    962  1.18  fredette 		wp_wrapu(ess, apuch + i, APUREG_ROUTE, apuch + 2 + i);
    963  1.18  fredette 
    964  1.18  fredette 		DPRINTF(ESM_DEBUG_DMA,
    965  1.26    kleink 		    ("choffs=0x%x, wpwa=0x%x, offset=0x%x words, size=0x%lx words\n",
    966  1.26    kleink 		    choffset, wpwa, offset, (unsigned long int)size));
    967  1.18  fredette 
    968  1.18  fredette 		/* Clear all mixer WP channel registers first. */
    969  1.18  fredette 		for (reg = 0; reg < 15; reg++)
    970  1.18  fredette 			wp_wrapu(ess, apuch + 2 + i, reg, 0);
    971  1.18  fredette 
    972  1.18  fredette 		/* Program the WaveCache for the mixer WP channel. */
    973  1.18  fredette 		chctl = (ess->rch.base + mixoffset - 0x10) &
    974  1.18  fredette 		    WAVCACHE_CHCTL_ADDRTAG_MASK;
    975  1.18  fredette 		wc_wrchctl(ess, apuch + 2 + i, chctl);
    976  1.18  fredette 
    977  1.18  fredette 		/* Program the mixer WP channel. */
    978  1.18  fredette 		wp_wrapu(ess, apuch + 2 + i, APUREG_FREQ_LOBYTE, APU_plus6dB
    979  1.18  fredette 		    | ((mixdv & 0xff) << APU_FREQ_LOBYTE_SHIFT) | 0x08);
    980  1.18  fredette 		wp_wrapu(ess, apuch + 2 + i, APUREG_FREQ_HIWORD, mixdv >> 8);
    981  1.18  fredette 		offset = mixoffset >> 1;
    982  1.18  fredette 		wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK);
    983  1.18  fredette 		wp_wrapu(ess, apuch + 2 + i, APUREG_WAVESPACE, wpwa);
    984  1.18  fredette 		wp_wrapu(ess, apuch + 2 + i, APUREG_CURPTR, offset);
    985  1.30      kent 		wp_wrapu(ess, apuch + 2 + i, APUREG_ENDPTR,
    986  1.18  fredette 		    offset + mixsize);
    987  1.18  fredette 		wp_wrapu(ess, apuch + 2 + i, APUREG_LOOPLEN, mixsize);
    988  1.18  fredette 		wp_wrapu(ess, apuch + 2 + i, APUREG_EFFECTS_ENV, 0x00f0);
    989  1.18  fredette 		wp_wrapu(ess, apuch + 2 + i, APUREG_AMPLITUDE, 0xe800);
    990  1.18  fredette 		wp_wrapu(ess, apuch + 2 + i, APUREG_POSITION, 0x8f00
    991  1.18  fredette 		    | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
    992  1.18  fredette 		    | (PAN_FRONT << APU_PAN_SHIFT));
    993  1.18  fredette 		wp_wrapu(ess, apuch + 2 + i, APUREG_ROUTE,
    994  1.18  fredette 		    ROUTE_PARALLEL + i);
    995  1.18  fredette 
    996  1.18  fredette 		DPRINTF(ESM_DEBUG_DMA,
    997  1.26    kleink 		    ("mixoffs=0x%x, wpwa=0x%x, offset=0x%x words, size=0x%lx words\n",
    998  1.26    kleink 		    mixoffset, wpwa, offset, (unsigned long int)mixsize));
    999  1.18  fredette 
   1000  1.18  fredette 		/* Assume we're going to loop to do the right channel. */
   1001  1.18  fredette 		choffset += MAESTRO_RECBUF_L_SZ;
   1002  1.18  fredette 		mixoffset += MAESTRO_MIXBUF_SZ >> 1;
   1003  1.18  fredette 	}
   1004  1.18  fredette 
   1005  1.18  fredette 	wp_wrapu(ess, apuch, APUREG_APUTYPE,
   1006  1.18  fredette 	    (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) |
   1007  1.18  fredette 	    APU_DMA_ENABLED | 0xf);
   1008  1.18  fredette 	if (nch > 1)
   1009  1.18  fredette 		wp_wrapu(ess, apuch + 1, APUREG_APUTYPE,
   1010  1.18  fredette 		    (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) |
   1011  1.18  fredette 		    APU_DMA_ENABLED | 0xf);
   1012  1.18  fredette 	wp_wrapu(ess, apuch + 2, APUREG_APUTYPE,
   1013  1.18  fredette 	    (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) |
   1014  1.18  fredette 	    APU_DMA_ENABLED | 0xf);
   1015  1.18  fredette 	if (nch > 1)
   1016  1.18  fredette 		wp_wrapu(ess, apuch + 3, APUREG_APUTYPE,
   1017  1.18  fredette 		    (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) |
   1018  1.18  fredette 		    APU_DMA_ENABLED | 0xf);
   1019  1.18  fredette 
   1020   1.1        rh 	return 0;
   1021   1.1        rh }
   1022   1.1        rh 
   1023   1.1        rh int
   1024   1.1        rh esm_halt_output(void *sc)
   1025   1.1        rh {
   1026  1.30      kent 	struct esm_softc *ess;
   1027  1.30      kent 	struct esm_chinfo *ch;
   1028   1.1        rh 
   1029   1.1        rh 	DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_output(%p)\n", sc));
   1030  1.30      kent 	ess = sc;
   1031  1.30      kent 	ch = &ess->pch;
   1032   1.1        rh 
   1033   1.1        rh 	wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE,
   1034   1.1        rh 	    APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
   1035   1.1        rh 	wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE,
   1036   1.1        rh 	    APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
   1037   1.1        rh 
   1038   1.1        rh 	ess->pactive = 0;
   1039   1.1        rh 	if (!ess->ractive)
   1040   1.1        rh 		wp_stoptimer(ess);
   1041   1.1        rh 
   1042   1.1        rh 	return 0;
   1043   1.1        rh }
   1044   1.1        rh 
   1045   1.1        rh int
   1046   1.1        rh esm_halt_input(void *sc)
   1047   1.1        rh {
   1048  1.30      kent 	struct esm_softc *ess;
   1049  1.30      kent 	struct esm_chinfo *ch;
   1050  1.18  fredette 
   1051  1.18  fredette 	DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_input(%p)\n", sc));
   1052  1.30      kent 	ess = sc;
   1053  1.30      kent 	ch = &ess->rch;
   1054  1.18  fredette 
   1055  1.18  fredette 	wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE,
   1056  1.18  fredette 	    APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
   1057  1.18  fredette 	wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE,
   1058  1.18  fredette 	    APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
   1059  1.18  fredette 	wp_wrapu(ess, (ch->num << 1) + 2, APUREG_APUTYPE,
   1060  1.18  fredette 	    APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
   1061  1.18  fredette 	wp_wrapu(ess, (ch->num << 1) + 3, APUREG_APUTYPE,
   1062  1.18  fredette 	    APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
   1063  1.18  fredette 
   1064  1.18  fredette 	ess->ractive = 0;
   1065  1.18  fredette 	if (!ess->pactive)
   1066  1.18  fredette 		wp_stoptimer(ess);
   1067  1.18  fredette 
   1068   1.1        rh 	return 0;
   1069   1.1        rh }
   1070   1.1        rh 
   1071   1.1        rh static inline u_int
   1072   1.1        rh calc_timer_freq(struct esm_chinfo *ch)
   1073   1.1        rh {
   1074   1.1        rh 	u_int freq;
   1075   1.1        rh 
   1076   1.1        rh 	freq = (ch->sample_rate + ch->apublk - 1) / ch->apublk;
   1077   1.1        rh 
   1078   1.1        rh 	DPRINTF(ESM_DEBUG_TIMER,
   1079   1.1        rh 	    ("calc_timer_freq(%p): rate = %u, blk = 0x%x (0x%x): freq = %u\n",
   1080   1.1        rh 	    ch, ch->sample_rate, ch->apublk, ch->blocksize, freq));
   1081   1.1        rh 
   1082   1.1        rh 	return freq;
   1083   1.1        rh }
   1084   1.1        rh 
   1085   1.1        rh static void
   1086   1.1        rh set_timer(struct esm_softc *ess)
   1087   1.1        rh {
   1088  1.30      kent 	unsigned freq, freq2;
   1089   1.1        rh 
   1090  1.30      kent 	freq = 0;
   1091   1.1        rh 	if (ess->pactive)
   1092   1.1        rh 		freq = calc_timer_freq(&ess->pch);
   1093   1.1        rh 
   1094   1.1        rh 	if (ess->ractive) {
   1095   1.1        rh 		freq2 = calc_timer_freq(&ess->rch);
   1096  1.18  fredette 		if (freq2 > freq)
   1097   1.1        rh 			freq = freq2;
   1098   1.1        rh 	}
   1099   1.1        rh 
   1100  1.18  fredette 	KASSERT(freq != 0);
   1101  1.18  fredette 
   1102   1.1        rh 	for (; freq < MAESTRO_MINFREQ; freq <<= 1)
   1103  1.30      kent 		continue;
   1104   1.1        rh 
   1105   1.1        rh 	if (freq > 0)
   1106   1.1        rh 		wp_settimer(ess, freq);
   1107   1.1        rh }
   1108   1.1        rh 
   1109   1.1        rh static void
   1110  1.29      kent esmch_set_format(struct esm_chinfo *ch, const audio_params_t *p)
   1111   1.1        rh {
   1112  1.30      kent 	uint16_t wcreg_tpl;
   1113  1.30      kent 	uint16_t aputype;
   1114   1.1        rh 
   1115  1.30      kent 	wcreg_tpl = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
   1116  1.30      kent 	aputype = APUTYPE_16BITLINEAR;
   1117   1.1        rh 	if (p->channels == 2) {
   1118   1.1        rh 		wcreg_tpl |= WAVCACHE_CHCTL_STEREO;
   1119   1.1        rh 		aputype++;
   1120   1.1        rh 	}
   1121  1.29      kent 	if (p->precision == 8) {
   1122   1.1        rh 		aputype += 2;
   1123  1.25    simonb 		switch (p->encoding) {
   1124  1.25    simonb 		case AUDIO_ENCODING_ULINEAR:
   1125  1.25    simonb 		case AUDIO_ENCODING_ULINEAR_BE:
   1126  1.25    simonb 		case AUDIO_ENCODING_ULINEAR_LE:
   1127   1.1        rh 			wcreg_tpl |= WAVCACHE_CHCTL_U8;
   1128  1.25    simonb 			break;
   1129  1.25    simonb 		}
   1130   1.1        rh 	}
   1131   1.1        rh 	ch->wcreg_tpl = wcreg_tpl;
   1132   1.1        rh 	ch->aputype = aputype;
   1133   1.1        rh 	ch->sample_rate = p->sample_rate;
   1134   1.1        rh 
   1135   1.1        rh 	DPRINTF(ESM_DEBUG_PARAM, ("esmch_set_format: "
   1136  1.29      kent 	    "numch=%u, prec=%u, tpl=0x%x, aputype=%d, rate=%u\n",
   1137  1.29      kent 	    p->channels, p->precision, wcreg_tpl, aputype, p->sample_rate));
   1138   1.1        rh }
   1139   1.1        rh 
   1140  1.18  fredette /*
   1141  1.18  fredette  * Since we can't record in true stereo, this function combines
   1142  1.30      kent  * the separately recorded left and right channels into the final
   1143  1.18  fredette  * buffer for the upper layer.
   1144  1.18  fredette  */
   1145  1.18  fredette static void
   1146  1.18  fredette esmch_combine_input(struct esm_softc *ess, struct esm_chinfo *ch)
   1147  1.18  fredette {
   1148  1.18  fredette 	size_t offset, resid, count;
   1149  1.30      kent 	uint32_t *dst32s;
   1150  1.30      kent 	const uint32_t *left32s, *right32s;
   1151  1.30      kent 	uint32_t left32, right32;
   1152  1.18  fredette 
   1153  1.18  fredette 	/* The current offset into the upper layer buffer. */
   1154  1.18  fredette 	offset = ch->offset;
   1155  1.18  fredette 
   1156  1.18  fredette 	/* The number of bytes left to combine. */
   1157  1.18  fredette 	resid = ch->blocksize;
   1158  1.18  fredette 
   1159  1.18  fredette 	while (resid > 0) {
   1160  1.18  fredette 
   1161  1.18  fredette 		/* The 32-bit words for the left channel. */
   1162  1.42  christos 		left32s = (const uint32_t *)((char *)ess->sc_dma.addr +
   1163  1.18  fredette 		    MAESTRO_RECBUF_L_OFF + offset / 2);
   1164  1.18  fredette 
   1165  1.18  fredette 		/* The 32-bit words for the right channel. */
   1166  1.42  christos 		right32s = (const uint32_t *)((char *)ess->sc_dma.addr +
   1167  1.18  fredette 		    MAESTRO_RECBUF_R_OFF + offset / 2);
   1168  1.18  fredette 
   1169  1.18  fredette 		/* The pointer to the 32-bit words we will write. */
   1170  1.42  christos 		dst32s = (uint32_t *)((char *)ch->buffer + offset);
   1171  1.18  fredette 
   1172  1.18  fredette 		/* Get the number of bytes we will combine now. */
   1173  1.18  fredette 		count = ch->bufsize - offset;
   1174  1.18  fredette 		if (count > resid)
   1175  1.18  fredette 			count = resid;
   1176  1.18  fredette 		resid -= count;
   1177  1.18  fredette 		offset += count;
   1178  1.18  fredette 		if (offset == ch->bufsize)
   1179  1.18  fredette 			offset = 0;
   1180  1.18  fredette 
   1181  1.18  fredette 		/* Combine, writing two 32-bit words at a time. */
   1182  1.18  fredette 		KASSERT((count & (sizeof(uint32_t) * 2 - 1)) == 0);
   1183  1.30      kent 		count /= (sizeof(uint32_t) * 2);
   1184  1.18  fredette 		while (count > 0) {
   1185  1.18  fredette 			left32 = *(left32s++);
   1186  1.18  fredette 			right32 = *(right32s++);
   1187  1.18  fredette 			/* XXX this endian handling is half-baked at best */
   1188  1.18  fredette #if BYTE_ORDER == LITTLE_ENDIAN
   1189  1.18  fredette 			*(dst32s++) = (left32 & 0xFFFF) | (right32 << 16);
   1190  1.18  fredette 			*(dst32s++) = (left32 >> 16) | (right32 & 0xFFFF0000);
   1191  1.18  fredette #else  /* BYTE_ORDER == BIG_ENDIAN */
   1192  1.18  fredette 			*(dst32s++) = (left32 & 0xFFFF0000) | (right32 >> 16);
   1193  1.18  fredette 			*(dst32s++) = (left32 << 16) | (right32 & 0xFFFF);
   1194  1.18  fredette #endif /* BYTE_ORDER == BIG_ENDIAN */
   1195  1.18  fredette 			count--;
   1196  1.18  fredette 		}
   1197  1.18  fredette 	}
   1198  1.18  fredette 
   1199  1.18  fredette 	/* Update the offset. */
   1200  1.18  fredette 	ch->offset = offset;
   1201  1.18  fredette }
   1202   1.1        rh 
   1203   1.1        rh /*
   1204   1.1        rh  * Audio interface glue functions
   1205   1.1        rh  */
   1206   1.1        rh 
   1207   1.1        rh int
   1208  1.41  christos esm_getdev (void *sc, struct audio_device *adp)
   1209   1.1        rh {
   1210  1.30      kent 
   1211   1.1        rh 	*adp = esm_device;
   1212   1.1        rh 	return 0;
   1213   1.1        rh }
   1214   1.1        rh 
   1215   1.1        rh int
   1216  1.41  christos esm_round_blocksize(void *sc, int blk, int mode,
   1217  1.41  christos     const audio_params_t *param)
   1218   1.1        rh {
   1219  1.30      kent 
   1220   1.1        rh 	DPRINTF(ESM_DEBUG_PARAM,
   1221   1.1        rh 	    ("esm_round_blocksize(%p, 0x%x)", sc, blk));
   1222   1.1        rh 
   1223   1.1        rh 	blk &= ~0x3f;		/* keep good alignment */
   1224   1.1        rh 
   1225   1.1        rh 	DPRINTF(ESM_DEBUG_PARAM, (" = 0x%x\n", blk));
   1226   1.1        rh 
   1227   1.1        rh 	return blk;
   1228   1.1        rh }
   1229   1.1        rh 
   1230   1.1        rh int
   1231  1.41  christos esm_query_encoding(void *sc, struct audio_encoding *fp)
   1232   1.1        rh {
   1233  1.30      kent 
   1234   1.1        rh 	DPRINTF(ESM_DEBUG_PARAM,
   1235   1.1        rh 	    ("esm_query_encoding(%p, %d)\n", sc, fp->index));
   1236   1.1        rh 
   1237   1.1        rh 	if (fp->index < 0 || fp->index >= MAESTRO_NENCODINGS)
   1238   1.1        rh 		return EINVAL;
   1239   1.1        rh 
   1240   1.1        rh 	*fp = esm_encoding[fp->index];
   1241   1.1        rh 	return 0;
   1242   1.1        rh }
   1243   1.1        rh 
   1244   1.1        rh int
   1245  1.41  christos esm_set_params(void *sc, int setmode, int usemode,
   1246  1.29      kent 	audio_params_t *play, audio_params_t *rec,
   1247  1.29      kent 	stream_filter_list_t *pfil, stream_filter_list_t *rfil)
   1248   1.1        rh {
   1249  1.30      kent 	struct esm_softc *ess;
   1250  1.29      kent 	audio_params_t *p;
   1251  1.29      kent 	const audio_params_t *hw_play, *hw_rec;
   1252  1.29      kent 	stream_filter_list_t *fil;
   1253  1.29      kent 	int mode, i;
   1254   1.1        rh 
   1255   1.1        rh 	DPRINTF(ESM_DEBUG_PARAM,
   1256   1.1        rh 	    ("esm_set_params(%p, 0x%x, 0x%x, %p, %p)\n",
   1257   1.1        rh 	    sc, setmode, usemode, play, rec));
   1258  1.30      kent 	ess = sc;
   1259  1.29      kent 	hw_play = NULL;
   1260  1.29      kent 	hw_rec = NULL;
   1261  1.30      kent 	for (mode = AUMODE_RECORD; mode != -1;
   1262   1.1        rh 	     mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
   1263   1.1        rh 		if ((setmode & mode) == 0)
   1264   1.1        rh 			continue;
   1265   1.1        rh 
   1266   1.1        rh 		p = mode == AUMODE_PLAY ? play : rec;
   1267   1.1        rh 
   1268   1.1        rh 		if (p->sample_rate < 4000 || p->sample_rate > 48000 ||
   1269   1.1        rh 		    (p->precision != 8 && p->precision != 16) ||
   1270   1.1        rh 		    (p->channels != 1 && p->channels != 2))
   1271   1.1        rh 			return EINVAL;
   1272   1.1        rh 
   1273  1.29      kent 		fil = mode == AUMODE_PLAY ? pfil : rfil;
   1274  1.29      kent 		i = auconv_set_converter(esm_formats, ESM_NFORMATS,
   1275  1.29      kent 					 mode, p, FALSE, fil);
   1276  1.29      kent 		if (i < 0)
   1277   1.1        rh 			return EINVAL;
   1278  1.29      kent 		if (fil->req_size > 0)
   1279  1.29      kent 			p = &fil->filters[0].param;
   1280  1.29      kent 		if (mode == AUMODE_PLAY)
   1281  1.29      kent 			hw_play = p;
   1282  1.29      kent 		else
   1283  1.29      kent 			hw_rec = p;
   1284   1.1        rh 	}
   1285   1.1        rh 
   1286  1.34  christos 	if (hw_play)
   1287  1.29      kent 		esmch_set_format(&ess->pch, hw_play);
   1288   1.1        rh 
   1289  1.34  christos 	if (hw_rec)
   1290  1.29      kent 		esmch_set_format(&ess->rch, hw_rec);
   1291   1.1        rh 
   1292   1.1        rh 	return 0;
   1293   1.1        rh }
   1294   1.1        rh 
   1295   1.1        rh int
   1296   1.1        rh esm_set_port(void *sc, mixer_ctrl_t *cp)
   1297   1.1        rh {
   1298  1.30      kent 	struct esm_softc *ess;
   1299   1.1        rh 
   1300  1.30      kent 	ess = sc;
   1301  1.30      kent 	return ess->codec_if->vtbl->mixer_set_port(ess->codec_if, cp);
   1302   1.1        rh }
   1303   1.1        rh 
   1304   1.1        rh int
   1305   1.1        rh esm_get_port(void *sc, mixer_ctrl_t *cp)
   1306   1.1        rh {
   1307  1.30      kent 	struct esm_softc *ess;
   1308   1.1        rh 
   1309  1.30      kent 	ess = sc;
   1310  1.30      kent 	return ess->codec_if->vtbl->mixer_get_port(ess->codec_if, cp);
   1311   1.1        rh }
   1312   1.1        rh 
   1313   1.1        rh int
   1314   1.1        rh esm_query_devinfo(void *sc, mixer_devinfo_t *dip)
   1315   1.1        rh {
   1316  1.30      kent 	struct esm_softc *ess;
   1317   1.1        rh 
   1318  1.30      kent 	ess = sc;
   1319  1.30      kent 	return ess->codec_if->vtbl->query_devinfo(ess->codec_if, dip);
   1320   1.1        rh }
   1321   1.1        rh 
   1322   1.1        rh void *
   1323  1.41  christos esm_malloc(void *sc, int direction, size_t size,
   1324  1.41  christos     struct malloc_type *pool, int flags)
   1325   1.1        rh {
   1326  1.30      kent 	struct esm_softc *ess;
   1327  1.18  fredette 	int off;
   1328   1.1        rh 
   1329   1.1        rh 	DPRINTF(ESM_DEBUG_DMA,
   1330  1.26    kleink 	    ("esm_malloc(%p, %d, 0x%lx, %p, 0x%x)",
   1331  1.26    kleink 	    sc, direction, (unsigned long int)size, pool, flags));
   1332  1.30      kent 	ess = sc;
   1333  1.18  fredette 	/*
   1334  1.18  fredette 	 * Each buffer can only be allocated once.
   1335  1.18  fredette 	 */
   1336  1.18  fredette 	if (ess->rings_alloced & direction) {
   1337   1.1        rh 		DPRINTF(ESM_DEBUG_DMA, (" = 0 (ENOMEM)\n"));
   1338   1.1        rh 		return 0;
   1339   1.1        rh 	}
   1340   1.1        rh 
   1341  1.18  fredette 	/*
   1342  1.18  fredette 	 * Mark this buffer as allocated and return its
   1343  1.18  fredette 	 * kernel virtual address.
   1344  1.18  fredette 	 */
   1345  1.18  fredette 	ess->rings_alloced |= direction;
   1346  1.18  fredette 	off = (direction == AUMODE_PLAY ?
   1347  1.18  fredette 		MAESTRO_PLAYBUF_OFF : MAESTRO_RECBUF_OFF);
   1348  1.18  fredette 	DPRINTF(ESM_DEBUG_DMA, (" = %p (DMAADDR 0x%x)\n",
   1349  1.42  christos 				(char *)ess->sc_dma.addr + off,
   1350  1.18  fredette 				(int)DMAADDR(&ess->sc_dma) + off));
   1351  1.42  christos 	return (char *)ess->sc_dma.addr + off;
   1352   1.1        rh }
   1353   1.1        rh 
   1354   1.1        rh void
   1355  1.41  christos esm_free(void *sc, void *ptr, struct malloc_type *pool)
   1356   1.1        rh {
   1357  1.30      kent 	struct esm_softc *ess;
   1358   1.1        rh 
   1359   1.1        rh 	DPRINTF(ESM_DEBUG_DMA,
   1360  1.22    kleink 	    ("esm_free(%p, %p, %p)\n",
   1361   1.1        rh 	    sc, ptr, pool));
   1362  1.30      kent 	ess = sc;
   1363  1.42  christos 	if ((char *)ptr == (char *)ess->sc_dma.addr + MAESTRO_PLAYBUF_OFF)
   1364  1.18  fredette 		ess->rings_alloced &= ~AUMODE_PLAY;
   1365  1.42  christos 	else if ((char *)ptr == (char *)ess->sc_dma.addr + MAESTRO_RECBUF_OFF)
   1366  1.18  fredette 		ess->rings_alloced &= ~AUMODE_RECORD;
   1367   1.1        rh }
   1368   1.1        rh 
   1369   1.1        rh size_t
   1370  1.41  christos esm_round_buffersize(void *sc, int direction, size_t size)
   1371   1.1        rh {
   1372  1.30      kent 
   1373  1.18  fredette 	if (size > MAESTRO_PLAYBUF_SZ)
   1374  1.18  fredette 		size = MAESTRO_PLAYBUF_SZ;
   1375  1.18  fredette 	if (size > MAESTRO_RECBUF_SZ)
   1376  1.18  fredette 		size = MAESTRO_RECBUF_SZ;
   1377   1.1        rh 	return size;
   1378   1.1        rh }
   1379   1.1        rh 
   1380   1.1        rh paddr_t
   1381   1.1        rh esm_mappage(void *sc, void *mem, off_t off, int prot)
   1382   1.1        rh {
   1383  1.30      kent 	struct esm_softc *ess;
   1384   1.1        rh 
   1385   1.1        rh 	DPRINTF(ESM_DEBUG_DMA,
   1386   1.1        rh 	    ("esm_mappage(%p, %p, 0x%lx, 0x%x)\n",
   1387   1.1        rh 	    sc, mem, (unsigned long)off, prot));
   1388  1.30      kent 	ess = sc;
   1389   1.1        rh 	if (off < 0)
   1390  1.30      kent 		return -1;
   1391   1.1        rh 
   1392  1.42  christos 	if ((char *)mem == (char *)ess->sc_dma.addr + MAESTRO_PLAYBUF_OFF)
   1393  1.18  fredette 		off += MAESTRO_PLAYBUF_OFF;
   1394  1.42  christos 	else if ((char *)mem == (char *)ess->sc_dma.addr + MAESTRO_RECBUF_OFF)
   1395  1.18  fredette 		off += MAESTRO_RECBUF_OFF;
   1396  1.18  fredette 	else
   1397  1.18  fredette 		return -1;
   1398  1.18  fredette 	return bus_dmamem_mmap(ess->dmat, ess->sc_dma.segs, ess->sc_dma.nsegs,
   1399  1.18  fredette 	    off, prot, BUS_DMA_WAITOK);
   1400   1.1        rh }
   1401   1.1        rh 
   1402   1.1        rh int
   1403  1.41  christos esm_get_props(void *sc)
   1404   1.1        rh {
   1405  1.30      kent 
   1406   1.1        rh 	return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
   1407   1.1        rh }
   1408   1.1        rh 
   1409   1.1        rh 
   1410   1.1        rh /* -----------------------------
   1411   1.1        rh  * Bus space.
   1412   1.1        rh  */
   1413   1.1        rh 
   1414  1.45    dyoung static int
   1415   1.1        rh esm_intr(void *sc)
   1416   1.1        rh {
   1417  1.30      kent 	struct esm_softc *ess;
   1418  1.30      kent 	uint16_t status;
   1419  1.30      kent 	uint16_t pos;
   1420  1.30      kent 	int ret;
   1421   1.1        rh 
   1422  1.30      kent 	ess = sc;
   1423  1.30      kent 	ret = 0;
   1424   1.1        rh 	status = bus_space_read_1(ess->st, ess->sh, PORT_HOSTINT_STAT);
   1425   1.1        rh 	if (!status)
   1426   1.1        rh 		return 0;
   1427   1.1        rh 
   1428   1.1        rh 	/* Acknowledge all. */
   1429   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
   1430   1.1        rh 	bus_space_write_1(ess->st, ess->sh, PORT_HOSTINT_STAT, 0);
   1431   1.1        rh #if 0	/* XXX - HWVOL */
   1432   1.1        rh 	if (status & HOSTINT_STAT_HWVOL) {
   1433   1.1        rh 		u_int delta;
   1434   1.1        rh 		delta = bus_space_read_1(ess->st, ess->sh, PORT_HWVOL_MASTER)
   1435   1.1        rh 		    - 0x88;
   1436   1.1        rh 		if (delta & 0x11)
   1437   1.1        rh 			mixer_set(device_get_softc(ess->dev),
   1438   1.1        rh 			    SOUND_MIXER_VOLUME, 0);
   1439   1.1        rh 		else {
   1440   1.1        rh 			mixer_set(device_get_softc(ess->dev),
   1441   1.1        rh 			    SOUND_MIXER_VOLUME,
   1442   1.1        rh 			    mixer_get(device_get_softc(ess->dev),
   1443   1.1        rh 				SOUND_MIXER_VOLUME)
   1444   1.1        rh 			    + ((delta >> 5) & 0x7) - 4
   1445   1.1        rh 			    + ((delta << 7) & 0x700) - 0x400);
   1446   1.1        rh 		}
   1447   1.1        rh 		bus_space_write_1(ess->st, ess->sh, PORT_HWVOL_MASTER, 0x88);
   1448   1.1        rh 		ret++;
   1449   1.1        rh 	}
   1450   1.1        rh #endif	/* XXX - HWVOL */
   1451   1.1        rh 
   1452   1.1        rh 	if (ess->pactive) {
   1453   1.1        rh 		pos = wp_rdapu(ess, ess->pch.num << 1, APUREG_CURPTR);
   1454   1.1        rh 
   1455   1.1        rh 		DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
   1456   1.1        rh 		    wp_rdapu(ess, (ess->pch.num<<1)+1, APUREG_CURPTR)));
   1457   1.1        rh 
   1458  1.18  fredette 		pos -= ess->pch.apubase;
   1459   1.1        rh 		if (pos >= ess->pch.nextirq &&
   1460   1.1        rh 		    pos - ess->pch.nextirq < ess->pch.apubuf / 2) {
   1461   1.1        rh 			ess->pch.nextirq += ess->pch.apublk;
   1462   1.1        rh 
   1463   1.1        rh 			if (ess->pch.nextirq >= ess->pch.apubuf)
   1464   1.1        rh 				ess->pch.nextirq = 0;
   1465   1.1        rh 
   1466   1.1        rh 			if (ess->sc_pintr) {
   1467   1.1        rh 				DPRINTF(ESM_DEBUG_IRQ, ("P\n"));
   1468   1.1        rh 				ess->sc_pintr(ess->sc_parg);
   1469   1.1        rh 			}
   1470   1.1        rh 
   1471   1.1        rh 		}
   1472   1.1        rh 		ret++;
   1473   1.1        rh 	}
   1474   1.1        rh 
   1475   1.1        rh 	if (ess->ractive) {
   1476   1.1        rh 		pos = wp_rdapu(ess, ess->rch.num << 1, APUREG_CURPTR);
   1477   1.1        rh 
   1478   1.1        rh 		DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
   1479   1.1        rh 		    wp_rdapu(ess, (ess->rch.num<<1)+1, APUREG_CURPTR)));
   1480   1.1        rh 
   1481  1.18  fredette 		pos -= ess->rch.apubase;
   1482   1.1        rh 		if (pos >= ess->rch.nextirq &&
   1483   1.1        rh 		    pos - ess->rch.nextirq < ess->rch.apubuf / 2) {
   1484   1.1        rh 			ess->rch.nextirq += ess->rch.apublk;
   1485   1.1        rh 
   1486   1.1        rh 			if (ess->rch.nextirq >= ess->rch.apubuf)
   1487   1.1        rh 				ess->rch.nextirq = 0;
   1488   1.1        rh 
   1489   1.1        rh 			if (ess->sc_rintr) {
   1490   1.1        rh 				DPRINTF(ESM_DEBUG_IRQ, ("R\n"));
   1491  1.18  fredette 				switch(ess->rch.aputype) {
   1492  1.18  fredette 				case APUTYPE_16BITSTEREO:
   1493  1.18  fredette 					esmch_combine_input(ess, &ess->rch);
   1494  1.18  fredette 					break;
   1495  1.18  fredette 				}
   1496  1.18  fredette 				ess->sc_rintr(ess->sc_rarg);
   1497   1.1        rh 			}
   1498   1.1        rh 
   1499   1.1        rh 		}
   1500   1.1        rh 		ret++;
   1501   1.1        rh 	}
   1502   1.1        rh 
   1503   1.1        rh 	return ret;
   1504   1.1        rh }
   1505   1.1        rh 
   1506  1.45    dyoung static void
   1507  1.45    dyoung esm_freemem(struct esm_softc *sc, struct esm_dma *p)
   1508  1.45    dyoung {
   1509  1.45    dyoung 	if (p->size == 0)
   1510  1.45    dyoung 		return;
   1511  1.45    dyoung 
   1512  1.45    dyoung 	bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
   1513  1.45    dyoung 
   1514  1.45    dyoung 	bus_dmamem_unmap(sc->dmat, p->addr, p->size);
   1515  1.45    dyoung 
   1516  1.45    dyoung 	bus_dmamap_destroy(sc->dmat, p->map);
   1517  1.45    dyoung 
   1518  1.45    dyoung 	bus_dmamap_unload(sc->dmat, p->map);
   1519  1.45    dyoung 
   1520  1.45    dyoung 	p->size = 0;
   1521  1.45    dyoung }
   1522  1.45    dyoung 
   1523  1.45    dyoung static int
   1524   1.1        rh esm_allocmem(struct esm_softc *sc, size_t size, size_t align,
   1525   1.1        rh     struct esm_dma *p)
   1526   1.1        rh {
   1527   1.1        rh 	int error;
   1528   1.1        rh 
   1529   1.1        rh 	p->size = size;
   1530   1.1        rh 	error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
   1531  1.50    cegger 				 p->segs, __arraycount(p->segs),
   1532   1.1        rh 				 &p->nsegs, BUS_DMA_NOWAIT);
   1533   1.1        rh 	if (error)
   1534   1.1        rh 		return error;
   1535   1.1        rh 
   1536   1.1        rh 	error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
   1537   1.1        rh 			       &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
   1538   1.1        rh 	if (error)
   1539   1.1        rh 		goto free;
   1540   1.1        rh 
   1541   1.1        rh 	error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
   1542   1.1        rh 				  0, BUS_DMA_NOWAIT, &p->map);
   1543   1.1        rh 	if (error)
   1544   1.1        rh 		goto unmap;
   1545   1.1        rh 
   1546   1.1        rh 	error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
   1547   1.1        rh 				BUS_DMA_NOWAIT);
   1548   1.1        rh 	if (error)
   1549   1.1        rh 		goto destroy;
   1550   1.1        rh 
   1551   1.1        rh 	return 0;
   1552   1.1        rh 
   1553   1.1        rh  destroy:
   1554   1.1        rh 	bus_dmamap_destroy(sc->dmat, p->map);
   1555   1.1        rh  unmap:
   1556   1.1        rh 	bus_dmamem_unmap(sc->dmat, p->addr, p->size);
   1557   1.1        rh  free:
   1558   1.1        rh 	bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
   1559   1.1        rh 
   1560  1.45    dyoung 	p->size = 0;
   1561   1.1        rh 	return error;
   1562   1.1        rh }
   1563   1.1        rh 
   1564  1.45    dyoung static int
   1565  1.48    cegger esm_match(device_t dev, cfdata_t match, void *aux)
   1566   1.1        rh {
   1567  1.30      kent 	struct pci_attach_args *pa;
   1568   1.1        rh 
   1569  1.30      kent 	pa = (struct pci_attach_args *)aux;
   1570   1.1        rh 	switch (PCI_VENDOR(pa->pa_id)) {
   1571   1.1        rh 	case PCI_VENDOR_ESSTECH:
   1572   1.1        rh 		switch (PCI_PRODUCT(pa->pa_id)) {
   1573   1.1        rh 		case PCI_PRODUCT_ESSTECH_MAESTRO1:
   1574   1.1        rh 		case PCI_PRODUCT_ESSTECH_MAESTRO2:
   1575   1.1        rh 		case PCI_PRODUCT_ESSTECH_MAESTRO2E:
   1576   1.1        rh 			return 1;
   1577   1.1        rh 		}
   1578   1.1        rh 
   1579   1.1        rh 	case PCI_VENDOR_ESSTECH2:
   1580   1.1        rh 		switch (PCI_PRODUCT(pa->pa_id)) {
   1581   1.1        rh 		case PCI_PRODUCT_ESSTECH2_MAESTRO1:
   1582   1.1        rh 			return 1;
   1583   1.1        rh 		}
   1584   1.1        rh 	}
   1585   1.1        rh 	return 0;
   1586   1.1        rh }
   1587   1.1        rh 
   1588  1.45    dyoung static void
   1589  1.45    dyoung esm_attach(device_t parent, device_t self, void *aux)
   1590   1.1        rh {
   1591  1.30      kent 	char devinfo[256];
   1592  1.30      kent 	struct esm_softc *ess;
   1593  1.30      kent 	struct pci_attach_args *pa;
   1594  1.30      kent 	const char *intrstr;
   1595  1.30      kent 	pci_chipset_tag_t pc;
   1596  1.30      kent 	pcitag_t tag;
   1597   1.1        rh 	pci_intr_handle_t ih;
   1598   1.1        rh 	pcireg_t csr, data;
   1599   1.1        rh 	int revision;
   1600  1.30      kent 	uint16_t codec_data;
   1601  1.30      kent 	uint16_t pcmbar;
   1602  1.35  christos 	int error;
   1603   1.1        rh 
   1604  1.45    dyoung 	ess = device_private(self);
   1605  1.49    cegger 	ess->sc_dev = self;
   1606  1.30      kent 	pa = (struct pci_attach_args *)aux;
   1607  1.30      kent 	pc = pa->pa_pc;
   1608  1.30      kent 	tag = pa->pa_tag;
   1609  1.20   thorpej 	aprint_naive(": Audio controller\n");
   1610  1.20   thorpej 
   1611  1.24    itojun 	pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
   1612   1.1        rh 	revision = PCI_REVISION(pa->pa_class);
   1613  1.20   thorpej 	aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision);
   1614   1.1        rh 
   1615   1.1        rh 	/* Enable the device. */
   1616   1.1        rh 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
   1617   1.1        rh 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
   1618   1.1        rh 	    csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
   1619   1.1        rh 
   1620   1.1        rh 	/* Map I/O register */
   1621   1.1        rh 	if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
   1622  1.45    dyoung 	    &ess->st, &ess->sh, NULL, &ess->sz)) {
   1623  1.49    cegger 		aprint_error_dev(ess->sc_dev, "can't map i/o space\n");
   1624   1.1        rh 		return;
   1625   1.1        rh 	}
   1626   1.1        rh 
   1627   1.1        rh 	/* Initialize softc */
   1628   1.1        rh 	ess->pch.num = 0;
   1629  1.18  fredette 	ess->rch.num = 1;
   1630   1.1        rh 	ess->dmat = pa->pa_dmat;
   1631   1.1        rh 	ess->tag = tag;
   1632   1.1        rh 	ess->pc = pc;
   1633   1.1        rh 	ess->subid = pci_conf_read(pc, tag, PCI_SUBSYS_ID_REG);
   1634   1.1        rh 
   1635   1.3        rh 	DPRINTF(ESM_DEBUG_PCI,
   1636   1.3        rh 	    ("%s: sub-system vendor 0x%4.4x, product 0x%4.4x\n",
   1637  1.49    cegger 	    device_xname(ess->sc_dev),
   1638   1.3        rh 	    PCI_VENDOR(ess->subid), PCI_PRODUCT(ess->subid)));
   1639   1.3        rh 
   1640   1.1        rh 	/* Map and establish the interrupt. */
   1641   1.1        rh 	if (pci_intr_map(pa, &ih)) {
   1642  1.49    cegger 		aprint_error_dev(ess->sc_dev, "can't map interrupt\n");
   1643   1.1        rh 		return;
   1644   1.1        rh 	}
   1645   1.1        rh 	intrstr = pci_intr_string(pc, ih);
   1646   1.1        rh 	ess->ih = pci_intr_establish(pc, ih, IPL_AUDIO, esm_intr, self);
   1647   1.1        rh 	if (ess->ih == NULL) {
   1648  1.49    cegger 		aprint_error_dev(ess->sc_dev, "can't establish interrupt");
   1649   1.1        rh 		if (intrstr != NULL)
   1650  1.51     njoly 			aprint_error(" at %s", intrstr);
   1651  1.51     njoly 		aprint_error("\n");
   1652   1.1        rh 		return;
   1653   1.1        rh 	}
   1654  1.49    cegger 	aprint_normal_dev(ess->sc_dev, "interrupting at %s\n",
   1655  1.47    cegger 	    intrstr);
   1656   1.1        rh 
   1657   1.1        rh 	/*
   1658   1.1        rh 	 * Setup PCI config registers
   1659   1.1        rh 	 */
   1660   1.1        rh 
   1661  1.35  christos 	/* power up chip */
   1662  1.46    dyoung 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
   1663  1.35  christos 	    pci_activate_null)) && error != EOPNOTSUPP) {
   1664  1.49    cegger 		aprint_error_dev(ess->sc_dev, "cannot activate %d\n",
   1665  1.35  christos 		    error);
   1666  1.35  christos 		return;
   1667  1.35  christos 	}
   1668   1.1        rh 	delay(100000);
   1669   1.1        rh 
   1670   1.1        rh 	/* Disable all legacy emulations. */
   1671   1.1        rh 	data = pci_conf_read(pc, tag, CONF_LEGACY);
   1672   1.1        rh 	pci_conf_write(pc, tag, CONF_LEGACY, data | LEGACY_DISABLED);
   1673   1.1        rh 
   1674   1.1        rh 	/* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
   1675   1.1        rh 	 * Enable posted write.
   1676   1.1        rh 	 * Prefer PCI timing rather than that of ISA.
   1677   1.1        rh 	 * Don't swap L/R. */
   1678   1.1        rh 	data = pci_conf_read(pc, tag, CONF_MAESTRO);
   1679   1.1        rh 	data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
   1680   1.1        rh 	data &= ~MAESTRO_SWAP_LR;
   1681   1.1        rh 	pci_conf_write(pc, tag, CONF_MAESTRO, data);
   1682   1.1        rh 
   1683   1.1        rh 	/* initialize sound chip */
   1684   1.1        rh 	esm_init(ess);
   1685   1.1        rh 
   1686   1.1        rh 	esm_read_codec(ess, 0, &codec_data);
   1687   1.1        rh 	if (codec_data == 0x80) {
   1688  1.49    cegger 		aprint_error_dev(ess->sc_dev, "PT101 codec detected!\n");
   1689   1.1        rh 		return;
   1690   1.1        rh 	}
   1691   1.1        rh 
   1692   1.3        rh 	/*
   1693   1.3        rh 	 * Some cards and Notebooks appear to have left and right channels
   1694   1.3        rh 	 * reversed.  Check if there is a corresponding quirk entry for
   1695   1.3        rh 	 * the subsystem vendor and product and if so, set the appropriate
   1696   1.3        rh 	 * codec flag.
   1697   1.3        rh 	 */
   1698   1.3        rh 	if (esm_get_quirks(ess->subid) & ESM_QUIRKF_SWAPPEDCH) {
   1699   1.3        rh 		ess->codec_flags |= AC97_HOST_SWAPPED_CHANNELS;
   1700   1.3        rh 	}
   1701   1.5        rh 	ess->codec_flags |= AC97_HOST_DONT_READ;
   1702   1.3        rh 
   1703   1.1        rh 	/* initialize AC97 host interface */
   1704   1.1        rh 	ess->host_if.arg = self;
   1705   1.1        rh 	ess->host_if.attach = esm_attach_codec;
   1706   1.1        rh 	ess->host_if.read = esm_read_codec;
   1707   1.1        rh 	ess->host_if.write = esm_write_codec;
   1708   1.1        rh 	ess->host_if.reset = esm_reset_codec;
   1709   1.3        rh 	ess->host_if.flags = esm_flags_codec;
   1710   1.1        rh 
   1711  1.29      kent 	if (ac97_attach(&ess->host_if, self) != 0)
   1712   1.1        rh 		return;
   1713  1.18  fredette 
   1714  1.18  fredette 	/* allocate our DMA region */
   1715  1.18  fredette 	if (esm_allocmem(ess, MAESTRO_DMA_SZ, MAESTRO_DMA_ALIGN,
   1716  1.18  fredette 		&ess->sc_dma)) {
   1717  1.49    cegger 		aprint_error_dev(ess->sc_dev, "couldn't allocate memory!\n");
   1718  1.18  fredette 		return;
   1719  1.18  fredette 	}
   1720  1.18  fredette 	ess->rings_alloced = 0;
   1721  1.18  fredette 
   1722  1.18  fredette 	/* set DMA base address */
   1723  1.18  fredette 	for (pcmbar = WAVCACHE_PCMBAR; pcmbar < WAVCACHE_PCMBAR + 4; pcmbar++)
   1724  1.18  fredette 		wc_wrreg(ess, pcmbar,
   1725  1.18  fredette 		    DMAADDR(&ess->sc_dma) >> WAVCACHE_BASEADDR_SHIFT);
   1726   1.1        rh 
   1727  1.49    cegger 	audio_attach_mi(&esm_hw_if, self, ess->sc_dev);
   1728   1.7    ichiro 
   1729  1.44  jmcneill 	if (!pmf_device_register(self, esm_suspend, esm_resume))
   1730  1.44  jmcneill 		aprint_error_dev(self, "couldn't establish power handler\n");
   1731   1.7    ichiro }
   1732   1.7    ichiro 
   1733  1.45    dyoung static void
   1734  1.45    dyoung esm_childdet(device_t self, device_t child)
   1735  1.45    dyoung {
   1736  1.45    dyoung 	/* we hold no child references, so do nothing */
   1737  1.45    dyoung }
   1738  1.45    dyoung 
   1739  1.45    dyoung static int
   1740  1.45    dyoung esm_detach(device_t self, int flags)
   1741  1.45    dyoung {
   1742  1.45    dyoung 	int rc;
   1743  1.45    dyoung 	struct esm_softc *ess = device_private(self);
   1744  1.45    dyoung 
   1745  1.45    dyoung 	pmf_device_deregister(self);
   1746  1.45    dyoung 
   1747  1.45    dyoung 	if ((rc = config_detach_children(self, flags)) != 0)
   1748  1.45    dyoung 		return rc;
   1749  1.45    dyoung 
   1750  1.45    dyoung 	/* free our DMA region */
   1751  1.45    dyoung 	esm_freemem(ess, &ess->sc_dma);
   1752  1.45    dyoung 
   1753  1.45    dyoung 	if (ess->codec_if != NULL)
   1754  1.45    dyoung 		ess->codec_if->vtbl->detach(ess->codec_if);
   1755  1.45    dyoung 
   1756  1.45    dyoung 	/* XXX Restore CONF_MAESTRO? */
   1757  1.45    dyoung 	/* XXX Restore legacy emulations? */
   1758  1.45    dyoung 	/* XXX Restore PCI config registers? */
   1759  1.45    dyoung 
   1760  1.45    dyoung 	if (ess->ih != NULL)
   1761  1.45    dyoung 		pci_intr_disestablish(ess->pc, ess->ih);
   1762  1.45    dyoung 
   1763  1.45    dyoung 	bus_space_unmap(ess->st, ess->sh, ess->sz);
   1764  1.45    dyoung 
   1765  1.45    dyoung 	return 0;
   1766  1.45    dyoung }
   1767  1.45    dyoung 
   1768  1.44  jmcneill static bool
   1769  1.45    dyoung esm_suspend(device_t dv PMF_FN_ARGS)
   1770   1.1        rh {
   1771  1.44  jmcneill 	struct esm_softc *ess = device_private(dv);
   1772   1.8    ichiro 	int x;
   1773   1.1        rh 
   1774   1.1        rh 	x = splaudio();
   1775   1.1        rh 	wp_stoptimer(ess);
   1776   1.1        rh 	bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
   1777   1.1        rh 
   1778   1.1        rh 	esm_halt_output(ess);
   1779   1.1        rh 	esm_halt_input(ess);
   1780   1.1        rh 	splx(x);
   1781   1.1        rh 
   1782   1.1        rh 	/* Power down everything except clock. */
   1783   1.1        rh 	esm_write_codec(ess, AC97_REG_POWER, 0xdf00);
   1784   1.1        rh 	delay(20);
   1785   1.1        rh 	bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
   1786   1.1        rh 	delay(1);
   1787   1.1        rh 
   1788  1.44  jmcneill 	return true;
   1789   1.1        rh }
   1790   1.1        rh 
   1791  1.44  jmcneill static bool
   1792  1.45    dyoung esm_resume(device_t dv PMF_FN_ARGS)
   1793   1.1        rh {
   1794  1.44  jmcneill 	struct esm_softc *ess = device_private(dv);
   1795   1.8    ichiro 	int x;
   1796  1.38  jmcneill 	uint16_t pcmbar;
   1797   1.1        rh 
   1798   1.1        rh 	delay(100000);
   1799   1.1        rh 	esm_init(ess);
   1800   1.8    ichiro 
   1801  1.38  jmcneill 	/* set DMA base address */
   1802  1.38  jmcneill 	for (pcmbar = WAVCACHE_PCMBAR; pcmbar < WAVCACHE_PCMBAR + 4; pcmbar++)
   1803  1.38  jmcneill 		wc_wrreg(ess, pcmbar,
   1804  1.38  jmcneill 		    DMAADDR(&ess->sc_dma) >> WAVCACHE_BASEADDR_SHIFT);
   1805  1.38  jmcneill 
   1806  1.30      kent 	ess->codec_if->vtbl->restore_ports(ess->codec_if);
   1807   1.8    ichiro #if 0
   1808   1.1        rh 	if (mixer_reinit(dev)) {
   1809   1.1        rh 		printf("%s: unable to reinitialize the mixer\n",
   1810  1.49    cegger 		    device_xname(ess->sc_dev));
   1811   1.1        rh 		return ENXIO;
   1812   1.1        rh 	}
   1813   1.8    ichiro #endif
   1814   1.1        rh 
   1815   1.1        rh 	x = splaudio();
   1816   1.8    ichiro #if TODO
   1817   1.1        rh 	if (ess->pactive)
   1818   1.1        rh 		esm_start_output(ess);
   1819   1.1        rh 	if (ess->ractive)
   1820   1.1        rh 		esm_start_input(ess);
   1821  1.30      kent #endif
   1822   1.1        rh 	if (ess->pactive || ess->ractive) {
   1823   1.1        rh 		set_timer(ess);
   1824   1.1        rh 		wp_starttimer(ess);
   1825   1.1        rh 	}
   1826   1.1        rh 	splx(x);
   1827   1.1        rh 
   1828  1.44  jmcneill 	return true;
   1829   1.1        rh }
   1830