esm.c revision 1.54 1 1.54 jmcneill /* $NetBSD: esm.c,v 1.54 2011/11/23 23:07:35 jmcneill Exp $ */
2 1.1 rh
3 1.1 rh /*-
4 1.18 fredette * Copyright (c) 2002, 2003 Matt Fredette
5 1.18 fredette * All rights reserved.
6 1.18 fredette *
7 1.23 keihan * Copyright (c) 2000, 2001 Rene Hexel <rh (at) NetBSD.org>
8 1.1 rh * All rights reserved.
9 1.1 rh *
10 1.1 rh * Copyright (c) 2000 Taku YAMAMOTO <taku (at) cent.saitama-u.ac.jp>
11 1.1 rh * All rights reserved.
12 1.1 rh *
13 1.1 rh * Redistribution and use in source and binary forms, with or without
14 1.1 rh * modification, are permitted provided that the following conditions
15 1.1 rh * are met:
16 1.1 rh * 1. Redistributions of source code must retain the above copyright
17 1.1 rh * notice, this list of conditions and the following disclaimer.
18 1.1 rh * 2. Redistributions in binary form must reproduce the above copyright
19 1.1 rh * notice, this list of conditions and the following disclaimer in the
20 1.1 rh * documentation and/or other materials provided with the distribution.
21 1.1 rh *
22 1.1 rh * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 1.1 rh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 1.1 rh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 1.1 rh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 1.1 rh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 1.1 rh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 1.1 rh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 1.1 rh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 1.1 rh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 1.1 rh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 1.1 rh * SUCH DAMAGE.
33 1.1 rh *
34 1.1 rh * Taku Id: maestro.c,v 1.12 2000/09/06 03:32:34 taku Exp
35 1.1 rh * FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.4 2000/12/18 01:36:35 cg Exp
36 1.1 rh */
37 1.1 rh
38 1.1 rh /*
39 1.1 rh * TODO:
40 1.1 rh * - hardware volume support
41 1.18 fredette * - fix 16-bit stereo recording, add 8-bit recording
42 1.1 rh * - MIDI support
43 1.1 rh * - joystick support
44 1.1 rh *
45 1.1 rh *
46 1.1 rh * Credits:
47 1.1 rh *
48 1.1 rh * This code is based on the FreeBSD driver written by Taku YAMAMOTO
49 1.1 rh *
50 1.1 rh *
51 1.1 rh * Original credits from the FreeBSD driver:
52 1.1 rh *
53 1.1 rh * Part of this code (especially in many magic numbers) was heavily inspired
54 1.1 rh * by the Linux driver originally written by
55 1.1 rh * Alan Cox <alan.cox (at) linux.org>, modified heavily by
56 1.1 rh * Zach Brown <zab (at) zabbo.net>.
57 1.1 rh *
58 1.1 rh * busdma()-ize and buffer size reduction were suggested by
59 1.1 rh * Cameron Grant <gandalf (at) vilnya.demon.co.uk>.
60 1.1 rh * Also he showed me the way to use busdma() suite.
61 1.1 rh *
62 1.1 rh * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
63 1.1 rh * were looked at by
64 1.1 rh * Munehiro Matsuda <haro (at) tk.kubota.co.jp>,
65 1.1 rh * who brought patches based on the Linux driver with some simplification.
66 1.1 rh */
67 1.12 lukem
68 1.12 lukem #include <sys/cdefs.h>
69 1.54 jmcneill __KERNEL_RCSID(0, "$NetBSD: esm.c,v 1.54 2011/11/23 23:07:35 jmcneill Exp $");
70 1.1 rh
71 1.1 rh #include <sys/param.h>
72 1.1 rh #include <sys/systm.h>
73 1.1 rh #include <sys/kernel.h>
74 1.54 jmcneill #include <sys/kmem.h>
75 1.1 rh #include <sys/device.h>
76 1.43 ad #include <sys/bus.h>
77 1.54 jmcneill #include <sys/audioio.h>
78 1.1 rh
79 1.1 rh #include <dev/audio_if.h>
80 1.1 rh #include <dev/mulaw.h>
81 1.1 rh #include <dev/auconv.h>
82 1.54 jmcneill
83 1.1 rh #include <dev/ic/ac97var.h>
84 1.8 ichiro #include <dev/ic/ac97reg.h>
85 1.1 rh
86 1.1 rh #include <dev/pci/pcidevs.h>
87 1.1 rh #include <dev/pci/pcivar.h>
88 1.1 rh #include <dev/pci/esmreg.h>
89 1.1 rh #include <dev/pci/esmvar.h>
90 1.1 rh
91 1.1 rh #define PCI_CBIO 0x10 /* Configuration Base I/O Address */
92 1.1 rh
93 1.1 rh /* Debug */
94 1.1 rh #ifdef AUDIO_DEBUG
95 1.1 rh #define DPRINTF(l,x) do { if (esm_debug & (l)) printf x; } while(0)
96 1.1 rh #define DUMPREG(x) do { if (esm_debug & ESM_DEBUG_REG) \
97 1.1 rh esm_dump_regs(x); } while(0)
98 1.1 rh int esm_debug = 0xfffc;
99 1.1 rh #define ESM_DEBUG_CODECIO 0x0001
100 1.1 rh #define ESM_DEBUG_IRQ 0x0002
101 1.1 rh #define ESM_DEBUG_DMA 0x0004
102 1.1 rh #define ESM_DEBUG_TIMER 0x0008
103 1.1 rh #define ESM_DEBUG_REG 0x0010
104 1.1 rh #define ESM_DEBUG_PARAM 0x0020
105 1.1 rh #define ESM_DEBUG_APU 0x0040
106 1.1 rh #define ESM_DEBUG_CODEC 0x0080
107 1.3 rh #define ESM_DEBUG_PCI 0x0100
108 1.8 ichiro #define ESM_DEBUG_RESUME 0x0200
109 1.1 rh #else
110 1.1 rh #define DPRINTF(x,y) /* nothing */
111 1.1 rh #define DUMPREG(x) /* nothing */
112 1.1 rh #endif
113 1.1 rh
114 1.1 rh #ifdef DIAGNOSTIC
115 1.1 rh #define RANGE(n, l, h) if ((n) < (l) || (n) >= (h)) \
116 1.1 rh printf (#n "=%d out of range (%d, %d) in " \
117 1.1 rh __FILE__ ", line %d\n", (n), (l), (h), __LINE__)
118 1.1 rh #else
119 1.1 rh #define RANGE(x,y,z) /* nothing */
120 1.1 rh #endif
121 1.1 rh
122 1.32 perry #define inline inline
123 1.1 rh
124 1.30 kent static inline void ringbus_setdest(struct esm_softc *, int, int);
125 1.1 rh
126 1.30 kent static inline uint16_t wp_rdreg(struct esm_softc *, uint16_t);
127 1.30 kent static inline void wp_wrreg(struct esm_softc *, uint16_t, uint16_t);
128 1.30 kent static inline uint16_t wp_rdapu(struct esm_softc *, int, uint16_t);
129 1.30 kent static inline void wp_wrapu(struct esm_softc *, int, uint16_t,
130 1.30 kent uint16_t);
131 1.1 rh static inline void wp_settimer(struct esm_softc *, u_int);
132 1.1 rh static inline void wp_starttimer(struct esm_softc *);
133 1.1 rh static inline void wp_stoptimer(struct esm_softc *);
134 1.1 rh
135 1.30 kent static inline uint16_t wc_rdreg(struct esm_softc *, uint16_t);
136 1.30 kent static inline void wc_wrreg(struct esm_softc *, uint16_t, uint16_t);
137 1.30 kent static inline uint16_t wc_rdchctl(struct esm_softc *, int);
138 1.30 kent static inline void wc_wrchctl(struct esm_softc *, int, uint16_t);
139 1.1 rh
140 1.1 rh static inline u_int calc_timer_freq(struct esm_chinfo*);
141 1.1 rh static void set_timer(struct esm_softc *);
142 1.1 rh
143 1.1 rh static void esmch_set_format(struct esm_chinfo *,
144 1.29 kent const audio_params_t *);
145 1.18 fredette static void esmch_combine_input(struct esm_softc *,
146 1.29 kent struct esm_chinfo *);
147 1.1 rh
148 1.53 dyoung static bool esm_suspend(device_t, const pmf_qual_t *);
149 1.53 dyoung static bool esm_resume(device_t, const pmf_qual_t *);
150 1.45 dyoung static void esm_childdet(device_t, device_t);
151 1.48 cegger static int esm_match(device_t, cfdata_t, void *);
152 1.45 dyoung static void esm_attach(device_t, device_t, void *);
153 1.45 dyoung static int esm_detach(device_t, int);
154 1.45 dyoung static int esm_intr(void *);
155 1.45 dyoung
156 1.45 dyoung static void esm_freemem(struct esm_softc *, struct esm_dma *);
157 1.45 dyoung static int esm_allocmem(struct esm_softc *, size_t, size_t,
158 1.45 dyoung struct esm_dma *);
159 1.7 ichiro
160 1.45 dyoung
161 1.49 cegger CFATTACH_DECL2_NEW(esm, sizeof(struct esm_softc),
162 1.45 dyoung esm_match, esm_attach, esm_detach, NULL, NULL, esm_childdet);
163 1.1 rh
164 1.28 yamt const struct audio_hw_if esm_hw_if = {
165 1.29 kent NULL, /* open */
166 1.29 kent NULL, /* close */
167 1.1 rh NULL, /* drain */
168 1.1 rh esm_query_encoding,
169 1.1 rh esm_set_params,
170 1.1 rh esm_round_blocksize,
171 1.1 rh NULL, /* commit_settings */
172 1.1 rh esm_init_output,
173 1.18 fredette esm_init_input,
174 1.1 rh NULL, /* start_output */
175 1.1 rh NULL, /* start_input */
176 1.1 rh esm_halt_output,
177 1.1 rh esm_halt_input,
178 1.1 rh NULL, /* speaker_ctl */
179 1.1 rh esm_getdev,
180 1.1 rh NULL, /* getfd */
181 1.1 rh esm_set_port,
182 1.1 rh esm_get_port,
183 1.1 rh esm_query_devinfo,
184 1.1 rh esm_malloc,
185 1.1 rh esm_free,
186 1.1 rh esm_round_buffersize,
187 1.1 rh esm_mappage,
188 1.1 rh esm_get_props,
189 1.1 rh esm_trigger_output,
190 1.11 augustss esm_trigger_input,
191 1.11 augustss NULL,
192 1.54 jmcneill esm_get_locks,
193 1.1 rh };
194 1.1 rh
195 1.1 rh struct audio_device esm_device = {
196 1.1 rh "ESS Maestro",
197 1.1 rh "",
198 1.1 rh "esm"
199 1.1 rh };
200 1.1 rh
201 1.30 kent #define MAESTRO_NENCODINGS 8
202 1.30 kent static audio_encoding_t esm_encoding[MAESTRO_NENCODINGS] = {
203 1.30 kent { 0, AudioEulinear, AUDIO_ENCODING_ULINEAR, 8, 0 },
204 1.1 rh { 1, AudioEmulaw, AUDIO_ENCODING_ULAW, 8,
205 1.30 kent AUDIO_ENCODINGFLAG_EMULATED },
206 1.30 kent { 2, AudioEalaw, AUDIO_ENCODING_ALAW, 8, AUDIO_ENCODINGFLAG_EMULATED },
207 1.30 kent { 3, AudioEslinear, AUDIO_ENCODING_SLINEAR, 8, 0 },
208 1.30 kent { 4, AudioEslinear_le, AUDIO_ENCODING_SLINEAR_LE, 16, 0 },
209 1.1 rh { 5, AudioEulinear_le, AUDIO_ENCODING_ULINEAR_LE, 16,
210 1.30 kent AUDIO_ENCODINGFLAG_EMULATED },
211 1.1 rh { 6, AudioEslinear_be, AUDIO_ENCODING_SLINEAR_BE, 16,
212 1.30 kent AUDIO_ENCODINGFLAG_EMULATED },
213 1.1 rh { 7, AudioEulinear_be, AUDIO_ENCODING_ULINEAR_BE, 16,
214 1.30 kent AUDIO_ENCODINGFLAG_EMULATED },
215 1.1 rh };
216 1.1 rh
217 1.29 kent #define ESM_NFORMATS 4
218 1.29 kent static const struct audio_format esm_formats[ESM_NFORMATS] = {
219 1.29 kent {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
220 1.29 kent 2, AUFMT_STEREO, 0, {4000, 48000}},
221 1.29 kent {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
222 1.29 kent 1, AUFMT_MONAURAL, 0, {4000, 48000}},
223 1.29 kent {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR_LE, 8, 8,
224 1.29 kent 2, AUFMT_STEREO, 0, {4000, 48000}},
225 1.29 kent {NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_ULINEAR_LE, 8, 8,
226 1.29 kent 1, AUFMT_MONAURAL, 0, {4000, 48000}},
227 1.29 kent };
228 1.3 rh
229 1.3 rh static const struct esm_quirks esm_quirks[] = {
230 1.3 rh /* COMPAL 38W2 OEM Notebook, e.g. Dell INSPIRON 5000e */
231 1.3 rh { PCI_VENDOR_COMPAL, PCI_PRODUCT_COMPAL_38W2, ESM_QUIRKF_SWAPPEDCH },
232 1.3 rh
233 1.5 rh /* COMPAQ Armada M700 Notebook */
234 1.5 rh { PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_M700, ESM_QUIRKF_SWAPPEDCH },
235 1.5 rh
236 1.3 rh /* NEC Versa Pro LX VA26D */
237 1.3 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VA26D, ESM_QUIRKF_GPIO },
238 1.3 rh
239 1.3 rh /* NEC Versa LX */
240 1.6 rh { PCI_VENDOR_NEC, PCI_PRODUCT_NEC_VERSALX, ESM_QUIRKF_GPIO },
241 1.6 rh
242 1.10 simonb /* Toshiba Portege */
243 1.10 simonb { PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_PORTEGE, ESM_QUIRKF_SWAPPEDCH }
244 1.3 rh };
245 1.3 rh
246 1.3 rh enum esm_quirk_flags
247 1.3 rh esm_get_quirks(pcireg_t subid)
248 1.3 rh {
249 1.3 rh int i;
250 1.3 rh
251 1.50 cegger for (i = 0; i < __arraycount(esm_quirks); i++) {
252 1.3 rh if (PCI_VENDOR(subid) == esm_quirks[i].eq_vendor &&
253 1.3 rh PCI_PRODUCT(subid) == esm_quirks[i].eq_product) {
254 1.3 rh return esm_quirks[i].eq_quirks;
255 1.3 rh }
256 1.3 rh }
257 1.3 rh
258 1.3 rh return 0;
259 1.3 rh }
260 1.3 rh
261 1.3 rh
262 1.1 rh #ifdef AUDIO_DEBUG
263 1.1 rh struct esm_reg_info {
264 1.1 rh int offset; /* register offset */
265 1.1 rh int width; /* 1/2/4 bytes */
266 1.1 rh } dump_regs[] = {
267 1.1 rh { PORT_WAVCACHE_CTRL, 2 },
268 1.1 rh { PORT_HOSTINT_CTRL, 2 },
269 1.1 rh { PORT_HOSTINT_STAT, 2 },
270 1.1 rh { PORT_HWVOL_VOICE_SHADOW, 1 },
271 1.1 rh { PORT_HWVOL_VOICE, 1 },
272 1.1 rh { PORT_HWVOL_MASTER_SHADOW, 1 },
273 1.1 rh { PORT_HWVOL_MASTER, 1 },
274 1.1 rh { PORT_RINGBUS_CTRL, 4 },
275 1.1 rh { PORT_GPIO_DATA, 2 },
276 1.1 rh { PORT_GPIO_MASK, 2 },
277 1.1 rh { PORT_GPIO_DIR, 2 },
278 1.1 rh { PORT_ASSP_CTRL_A, 1 },
279 1.1 rh { PORT_ASSP_CTRL_B, 1 },
280 1.1 rh { PORT_ASSP_CTRL_C, 1 },
281 1.3 rh { PORT_ASSP_INT_STAT, 1 }
282 1.1 rh };
283 1.1 rh
284 1.2 lukem static void
285 1.2 lukem esm_dump_regs(struct esm_softc *ess)
286 1.1 rh {
287 1.3 rh int i;
288 1.1 rh
289 1.49 cegger printf("%s registers:", device_xname(ess->sc_dev));
290 1.50 cegger for (i = 0; i < __arraycount(dump_regs); i++) {
291 1.1 rh if (i % 5 == 0)
292 1.1 rh printf("\n");
293 1.1 rh printf("0x%2.2x: ", dump_regs[i].offset);
294 1.1 rh switch(dump_regs[i].width) {
295 1.1 rh case 4:
296 1.1 rh printf("%8.8x, ", bus_space_read_4(ess->st, ess->sh,
297 1.1 rh dump_regs[i].offset));
298 1.1 rh break;
299 1.1 rh case 2:
300 1.1 rh printf("%4.4x, ", bus_space_read_2(ess->st, ess->sh,
301 1.1 rh dump_regs[i].offset));
302 1.1 rh break;
303 1.1 rh default:
304 1.1 rh printf("%2.2x, ",
305 1.1 rh bus_space_read_1(ess->st, ess->sh,
306 1.1 rh dump_regs[i].offset));
307 1.1 rh }
308 1.1 rh }
309 1.1 rh printf("\n");
310 1.1 rh }
311 1.1 rh #endif
312 1.1 rh
313 1.3 rh
314 1.1 rh /* -----------------------------
315 1.1 rh * Subsystems.
316 1.1 rh */
317 1.1 rh
318 1.1 rh /* Codec/Ringbus */
319 1.1 rh
320 1.1 rh /* -------------------------------------------------------------------- */
321 1.1 rh
322 1.1 rh int
323 1.30 kent esm_read_codec(void *sc, uint8_t regno, uint16_t *result)
324 1.1 rh {
325 1.30 kent struct esm_softc *ess;
326 1.1 rh unsigned t;
327 1.1 rh
328 1.30 kent ess = sc;
329 1.1 rh /* We have to wait for a SAFE time to write addr/data */
330 1.1 rh for (t = 0; t < 20; t++) {
331 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
332 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
333 1.1 rh break;
334 1.1 rh delay(2); /* 20.8us / 13 */
335 1.1 rh }
336 1.1 rh if (t == 20)
337 1.1 rh printf("%s: esm_read_codec() PROGLESS timed out.\n",
338 1.49 cegger device_xname(ess->sc_dev));
339 1.1 rh
340 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
341 1.1 rh CODEC_CMD_READ | regno);
342 1.1 rh delay(21); /* AC97 cycle = 20.8usec */
343 1.1 rh
344 1.1 rh /* Wait for data retrieve */
345 1.1 rh for (t = 0; t < 20; t++) {
346 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
347 1.1 rh & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE)
348 1.1 rh break;
349 1.1 rh delay(2); /* 20.8us / 13 */
350 1.1 rh }
351 1.1 rh if (t == 20)
352 1.1 rh /* Timed out, but perform dummy read. */
353 1.1 rh printf("%s: esm_read_codec() RW_DONE timed out.\n",
354 1.49 cegger device_xname(ess->sc_dev));
355 1.1 rh
356 1.1 rh *result = bus_space_read_2(ess->st, ess->sh, PORT_CODEC_REG);
357 1.1 rh
358 1.1 rh return 0;
359 1.1 rh }
360 1.1 rh
361 1.1 rh int
362 1.30 kent esm_write_codec(void *sc, uint8_t regno, uint16_t data)
363 1.1 rh {
364 1.30 kent struct esm_softc *ess;
365 1.1 rh unsigned t;
366 1.1 rh
367 1.30 kent ess = sc;
368 1.1 rh /* We have to wait for a SAFE time to write addr/data */
369 1.1 rh for (t = 0; t < 20; t++) {
370 1.1 rh if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
371 1.1 rh & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
372 1.1 rh break;
373 1.1 rh delay(2); /* 20.8us / 13 */
374 1.1 rh }
375 1.1 rh if (t == 20) {
376 1.1 rh /* Timed out. Abort writing. */
377 1.1 rh printf("%s: esm_write_codec() PROGLESS timed out.\n",
378 1.49 cegger device_xname(ess->sc_dev));
379 1.1 rh return -1;
380 1.1 rh }
381 1.1 rh
382 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_CODEC_REG, data);
383 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
384 1.1 rh CODEC_CMD_WRITE | regno);
385 1.1 rh
386 1.1 rh return 0;
387 1.1 rh }
388 1.1 rh
389 1.1 rh /* -------------------------------------------------------------------- */
390 1.1 rh
391 1.1 rh static inline void
392 1.1 rh ringbus_setdest(struct esm_softc *ess, int src, int dest)
393 1.1 rh {
394 1.30 kent uint32_t data;
395 1.1 rh
396 1.1 rh data = bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL);
397 1.1 rh data &= ~(0xfU << src);
398 1.1 rh data |= (0xfU & dest) << src;
399 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, data);
400 1.1 rh }
401 1.1 rh
402 1.1 rh /* Wave Processor */
403 1.1 rh
404 1.30 kent static inline uint16_t
405 1.30 kent wp_rdreg(struct esm_softc *ess, uint16_t reg)
406 1.1 rh {
407 1.30 kent
408 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
409 1.1 rh return bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA);
410 1.1 rh }
411 1.1 rh
412 1.1 rh static inline void
413 1.30 kent wp_wrreg(struct esm_softc *ess, uint16_t reg, uint16_t data)
414 1.1 rh {
415 1.30 kent
416 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
417 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
418 1.1 rh }
419 1.1 rh
420 1.1 rh static inline void
421 1.30 kent apu_setindex(struct esm_softc *ess, uint16_t reg)
422 1.1 rh {
423 1.1 rh int t;
424 1.1 rh
425 1.1 rh wp_wrreg(ess, WPREG_CRAM_PTR, reg);
426 1.1 rh /* Sometimes WP fails to set apu register index. */
427 1.1 rh for (t = 0; t < 1000; t++) {
428 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == reg)
429 1.1 rh break;
430 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, reg);
431 1.1 rh }
432 1.1 rh if (t == 1000)
433 1.49 cegger printf("%s: apu_setindex() timed out.\n", device_xname(ess->sc_dev));
434 1.1 rh }
435 1.1 rh
436 1.30 kent static inline uint16_t
437 1.30 kent wp_rdapu(struct esm_softc *ess, int ch, uint16_t reg)
438 1.1 rh {
439 1.30 kent uint16_t ret;
440 1.1 rh
441 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg);
442 1.1 rh ret = wp_rdreg(ess, WPREG_DATA_PORT);
443 1.1 rh return ret;
444 1.1 rh }
445 1.1 rh
446 1.1 rh static inline void
447 1.30 kent wp_wrapu(struct esm_softc *ess, int ch, uint16_t reg, uint16_t data)
448 1.1 rh {
449 1.1 rh int t;
450 1.1 rh
451 1.1 rh DPRINTF(ESM_DEBUG_APU,
452 1.1 rh ("wp_wrapu(%p, ch=%d, reg=0x%x, data=0x%04x)\n",
453 1.1 rh ess, ch, reg, data));
454 1.1 rh
455 1.1 rh apu_setindex(ess, ((unsigned)ch << 4) + reg);
456 1.1 rh wp_wrreg(ess, WPREG_DATA_PORT, data);
457 1.1 rh for (t = 0; t < 1000; t++) {
458 1.1 rh if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == data)
459 1.1 rh break;
460 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
461 1.1 rh }
462 1.1 rh if (t == 1000)
463 1.49 cegger printf("%s: wp_wrapu() timed out.\n", device_xname(ess->sc_dev));
464 1.1 rh }
465 1.1 rh
466 1.1 rh static inline void
467 1.1 rh wp_settimer(struct esm_softc *ess, u_int freq)
468 1.1 rh {
469 1.30 kent u_int clock;
470 1.30 kent u_int prescale, divide;
471 1.1 rh
472 1.30 kent clock = 48000 << 2;
473 1.30 kent prescale = 0;
474 1.30 kent divide = (freq != 0) ? (clock / freq) : ~0;
475 1.1 rh RANGE(divide, WPTIMER_MINDIV, WPTIMER_MAXDIV);
476 1.1 rh
477 1.1 rh for (; divide > 32 << 1; divide >>= 1)
478 1.1 rh prescale++;
479 1.1 rh divide = (divide + 1) >> 1;
480 1.1 rh
481 1.1 rh for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
482 1.1 rh prescale++;
483 1.1 rh
484 1.1 rh DPRINTF(ESM_DEBUG_TIMER,
485 1.1 rh ("wp_settimer(%p, %u): clock = %u, prescale = %u, divide = %u\n",
486 1.1 rh ess, freq, clock, prescale, divide));
487 1.1 rh
488 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
489 1.1 rh wp_wrreg(ess, WPREG_TIMER_FREQ,
490 1.1 rh (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
491 1.1 rh wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
492 1.1 rh }
493 1.1 rh
494 1.1 rh static inline void
495 1.1 rh wp_starttimer(struct esm_softc *ess)
496 1.1 rh {
497 1.30 kent
498 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 1);
499 1.1 rh }
500 1.1 rh
501 1.1 rh static inline void
502 1.1 rh wp_stoptimer(struct esm_softc *ess)
503 1.1 rh {
504 1.30 kent
505 1.1 rh wp_wrreg(ess, WPREG_TIMER_START, 0);
506 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
507 1.1 rh }
508 1.1 rh
509 1.1 rh /* WaveCache */
510 1.1 rh
511 1.30 kent static inline uint16_t
512 1.30 kent wc_rdreg(struct esm_softc *ess, uint16_t reg)
513 1.1 rh {
514 1.30 kent
515 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
516 1.1 rh return bus_space_read_2(ess->st, ess->sh, PORT_WAVCACHE_DATA);
517 1.1 rh }
518 1.1 rh
519 1.1 rh static inline void
520 1.30 kent wc_wrreg(struct esm_softc *ess, uint16_t reg, uint16_t data)
521 1.1 rh {
522 1.30 kent
523 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
524 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_DATA, data);
525 1.1 rh }
526 1.1 rh
527 1.30 kent static inline uint16_t
528 1.1 rh wc_rdchctl(struct esm_softc *ess, int ch)
529 1.1 rh {
530 1.30 kent
531 1.1 rh return wc_rdreg(ess, ch << 3);
532 1.1 rh }
533 1.1 rh
534 1.1 rh static inline void
535 1.30 kent wc_wrchctl(struct esm_softc *ess, int ch, uint16_t data)
536 1.1 rh {
537 1.30 kent
538 1.1 rh wc_wrreg(ess, ch << 3, data);
539 1.1 rh }
540 1.1 rh
541 1.1 rh /* -----------------------------
542 1.1 rh * Controller.
543 1.1 rh */
544 1.1 rh
545 1.1 rh int
546 1.1 rh esm_attach_codec(void *sc, struct ac97_codec_if *codec_if)
547 1.1 rh {
548 1.30 kent struct esm_softc *ess;
549 1.1 rh
550 1.30 kent ess = sc;
551 1.1 rh ess->codec_if = codec_if;
552 1.1 rh
553 1.1 rh return 0;
554 1.1 rh }
555 1.1 rh
556 1.27 kent int
557 1.41 christos esm_reset_codec(void *sc)
558 1.1 rh {
559 1.30 kent
560 1.27 kent return 0;
561 1.1 rh }
562 1.1 rh
563 1.1 rh
564 1.3 rh enum ac97_host_flags
565 1.3 rh esm_flags_codec(void *sc)
566 1.3 rh {
567 1.30 kent struct esm_softc *ess;
568 1.3 rh
569 1.30 kent ess = sc;
570 1.3 rh return ess->codec_flags;
571 1.3 rh }
572 1.3 rh
573 1.3 rh
574 1.1 rh void
575 1.1 rh esm_initcodec(struct esm_softc *ess)
576 1.1 rh {
577 1.30 kent uint16_t data;
578 1.1 rh
579 1.1 rh DPRINTF(ESM_DEBUG_CODEC, ("esm_initcodec(%p)\n", ess));
580 1.1 rh
581 1.1 rh if (bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL)
582 1.1 rh & RINGBUS_CTRL_ACLINK_ENABLED) {
583 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
584 1.1 rh delay(104); /* 20.8us * (4 + 1) */
585 1.1 rh }
586 1.1 rh /* XXX - 2nd codec should be looked at. */
587 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
588 1.1 rh RINGBUS_CTRL_AC97_SWRESET);
589 1.1 rh delay(2);
590 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
591 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED);
592 1.1 rh delay(21);
593 1.1 rh
594 1.1 rh esm_read_codec(ess, 0, &data);
595 1.1 rh if (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
596 1.1 rh & CODEC_STAT_MASK) {
597 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
598 1.1 rh delay(21);
599 1.1 rh
600 1.1 rh /* Try cold reset. */
601 1.49 cegger printf("%s: will perform cold reset.\n", device_xname(ess->sc_dev));
602 1.1 rh data = bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR);
603 1.1 rh if (pci_conf_read(ess->pc, ess->tag, 0x58) & 1)
604 1.1 rh data |= 0x10;
605 1.1 rh data |= 0x009 &
606 1.1 rh ~bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DATA);
607 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0xff6);
608 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
609 1.1 rh data | 0x009);
610 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x000);
611 1.1 rh delay(2);
612 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x001);
613 1.1 rh delay(1);
614 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x009);
615 1.1 rh delay(500000);
616 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, data);
617 1.1 rh delay(84); /* 20.8us * 4 */
618 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
619 1.1 rh RINGBUS_CTRL_ACLINK_ENABLED);
620 1.1 rh delay(21);
621 1.1 rh }
622 1.1 rh }
623 1.1 rh
624 1.1 rh void
625 1.1 rh esm_init(struct esm_softc *ess)
626 1.1 rh {
627 1.30 kent
628 1.1 rh /* Reset direct sound. */
629 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
630 1.1 rh HOSTINT_CTRL_DSOUND_RESET);
631 1.1 rh delay(10000);
632 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
633 1.1 rh delay(10000);
634 1.1 rh
635 1.1 rh /* Enable direct sound interruption. */
636 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
637 1.1 rh HOSTINT_CTRL_DSOUND_INT_ENABLED);
638 1.1 rh
639 1.1 rh /* Setup Wave Processor. */
640 1.1 rh
641 1.1 rh /* Enable WaveCache */
642 1.1 rh wp_wrreg(ess, WPREG_WAVE_ROMRAM,
643 1.1 rh WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
644 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_CTRL,
645 1.1 rh WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB);
646 1.1 rh
647 1.1 rh /* Setup Codec/Ringbus. */
648 1.1 rh esm_initcodec(ess);
649 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
650 1.1 rh RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED);
651 1.1 rh
652 1.18 fredette /* Undocumented registers from the Linux driver. */
653 1.18 fredette wp_wrreg(ess, 0x8, 0xB004);
654 1.18 fredette wp_wrreg(ess, 0x9, 0x001B);
655 1.18 fredette wp_wrreg(ess, 0xA, 0x8000);
656 1.18 fredette wp_wrreg(ess, 0xB, 0x3F37);
657 1.18 fredette wp_wrreg(ess, 0xD, 0x7632);
658 1.18 fredette
659 1.18 fredette wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
660 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_ADC,
661 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
662 1.1 rh ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
663 1.1 rh RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
664 1.1 rh
665 1.1 rh /* Setup ASSP. Needed for Dell Inspiron 7500? */
666 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_B, 0x00);
667 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_A, 0x03);
668 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_C, 0x00);
669 1.1 rh
670 1.1 rh /*
671 1.1 rh * Setup GPIO.
672 1.1 rh * There seems to be speciality with NEC systems.
673 1.1 rh */
674 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_GPIO) {
675 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK,
676 1.3 rh 0x9ff);
677 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
678 1.3 rh bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR) |
679 1.3 rh 0x600);
680 1.3 rh bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA,
681 1.3 rh 0x200);
682 1.1 rh }
683 1.1 rh
684 1.1 rh DUMPREG(ess);
685 1.1 rh }
686 1.1 rh
687 1.1 rh /* Channel controller. */
688 1.1 rh
689 1.1 rh int
690 1.41 christos esm_init_output (void *sc, void *start, int size)
691 1.1 rh {
692 1.30 kent struct esm_softc *ess;
693 1.1 rh struct esm_dma *p;
694 1.1 rh
695 1.30 kent ess = sc;
696 1.18 fredette p = &ess->sc_dma;
697 1.42 christos if ((char *)start != (char *)p->addr + MAESTRO_PLAYBUF_OFF) {
698 1.1 rh printf("%s: esm_init_output: bad addr %p\n",
699 1.49 cegger device_xname(ess->sc_dev), start);
700 1.1 rh return EINVAL;
701 1.1 rh }
702 1.1 rh
703 1.18 fredette ess->pch.base = DMAADDR(p) + MAESTRO_PLAYBUF_OFF;
704 1.1 rh
705 1.1 rh DPRINTF(ESM_DEBUG_DMA, ("%s: pch.base = 0x%x\n",
706 1.49 cegger device_xname(ess->sc_dev), ess->pch.base));
707 1.1 rh
708 1.18 fredette return 0;
709 1.18 fredette }
710 1.18 fredette
711 1.18 fredette int
712 1.41 christos esm_init_input (void *sc, void *start, int size)
713 1.18 fredette {
714 1.30 kent struct esm_softc *ess;
715 1.18 fredette struct esm_dma *p;
716 1.18 fredette
717 1.30 kent ess = sc;
718 1.18 fredette p = &ess->sc_dma;
719 1.42 christos if ((char *)start != (char *)p->addr + MAESTRO_RECBUF_OFF) {
720 1.18 fredette printf("%s: esm_init_input: bad addr %p\n",
721 1.49 cegger device_xname(ess->sc_dev), start);
722 1.18 fredette return EINVAL;
723 1.18 fredette }
724 1.18 fredette
725 1.18 fredette switch (ess->rch.aputype) {
726 1.18 fredette case APUTYPE_16BITSTEREO:
727 1.18 fredette ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_L_OFF;
728 1.18 fredette break;
729 1.18 fredette default:
730 1.18 fredette ess->rch.base = DMAADDR(p) + MAESTRO_RECBUF_OFF;
731 1.18 fredette break;
732 1.18 fredette }
733 1.18 fredette
734 1.18 fredette DPRINTF(ESM_DEBUG_DMA, ("%s: rch.base = 0x%x\n",
735 1.49 cegger device_xname(ess->sc_dev), ess->rch.base));
736 1.1 rh
737 1.1 rh return 0;
738 1.1 rh }
739 1.1 rh
740 1.1 rh int
741 1.1 rh esm_trigger_output(void *sc, void *start, void *end, int blksize,
742 1.41 christos void (*intr)(void *), void *arg, const audio_params_t *param)
743 1.1 rh {
744 1.30 kent size_t size;
745 1.30 kent struct esm_softc *ess;
746 1.30 kent struct esm_chinfo *ch;
747 1.1 rh struct esm_dma *p;
748 1.30 kent int pan, choffset;
749 1.30 kent int i, nch;
750 1.30 kent unsigned speed, offset, wpwa, dv;
751 1.30 kent uint16_t apuch;
752 1.1 rh
753 1.1 rh DPRINTF(ESM_DEBUG_DMA,
754 1.1 rh ("esm_trigger_output(%p, %p, %p, 0x%x, %p, %p, %p)\n",
755 1.1 rh sc, start, end, blksize, intr, arg, param));
756 1.30 kent ess = sc;
757 1.30 kent ch = &ess->pch;
758 1.30 kent pan = 0;
759 1.30 kent nch = 1;
760 1.30 kent speed = ch->sample_rate;
761 1.30 kent apuch = ch->num << 1;
762 1.1 rh
763 1.1 rh #ifdef DIAGNOSTIC
764 1.1 rh if (ess->pactive) {
765 1.1 rh printf("%s: esm_trigger_output: already running",
766 1.49 cegger device_xname(ess->sc_dev));
767 1.1 rh return EINVAL;
768 1.1 rh }
769 1.1 rh #endif
770 1.1 rh
771 1.1 rh ess->sc_pintr = intr;
772 1.1 rh ess->sc_parg = arg;
773 1.18 fredette p = &ess->sc_dma;
774 1.42 christos if ((char *)start != (char *)p->addr + MAESTRO_PLAYBUF_OFF) {
775 1.1 rh printf("%s: esm_trigger_output: bad addr %p\n",
776 1.49 cegger device_xname(ess->sc_dev), start);
777 1.1 rh return EINVAL;
778 1.1 rh }
779 1.1 rh
780 1.1 rh ess->pch.blocksize = blksize;
781 1.1 rh ess->pch.apublk = blksize >> 1;
782 1.1 rh ess->pactive = 1;
783 1.1 rh
784 1.42 christos size = (size_t)(((char *)end - (char *)start) >> 1);
785 1.18 fredette choffset = MAESTRO_PLAYBUF_OFF;
786 1.1 rh offset = choffset >> 1;
787 1.18 fredette wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK);
788 1.1 rh
789 1.1 rh DPRINTF(ESM_DEBUG_DMA,
790 1.26 kleink ("choffs=0x%x, wpwa=0x%x, size=0x%lx words\n",
791 1.26 kleink choffset, wpwa, (unsigned long int)size));
792 1.1 rh
793 1.1 rh switch (ch->aputype) {
794 1.1 rh case APUTYPE_16BITSTEREO:
795 1.1 rh ess->pch.apublk >>= 1;
796 1.1 rh wpwa >>= 1;
797 1.1 rh size >>= 1;
798 1.1 rh offset >>= 1;
799 1.1 rh /* FALLTHROUGH */
800 1.1 rh case APUTYPE_8BITSTEREO:
801 1.3 rh if (ess->codec_flags & AC97_HOST_SWAPPED_CHANNELS)
802 1.3 rh pan = 8;
803 1.3 rh else
804 1.3 rh pan = -8;
805 1.3 rh nch++;
806 1.1 rh break;
807 1.1 rh case APUTYPE_8BITLINEAR:
808 1.1 rh ess->pch.apublk <<= 1;
809 1.1 rh speed >>= 1;
810 1.1 rh break;
811 1.1 rh }
812 1.1 rh
813 1.18 fredette ess->pch.apubase = offset;
814 1.1 rh ess->pch.apubuf = size;
815 1.1 rh ess->pch.nextirq = ess->pch.apublk;
816 1.1 rh
817 1.1 rh set_timer(ess);
818 1.1 rh wp_starttimer(ess);
819 1.1 rh
820 1.1 rh dv = (((speed % 48000) << 16) + 24000) / 48000
821 1.1 rh + ((speed / 48000) << 16);
822 1.1 rh
823 1.3 rh for (i = nch-1; i >= 0; i--) {
824 1.3 rh wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa & 0xff00);
825 1.3 rh wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset);
826 1.3 rh wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size);
827 1.3 rh wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1);
828 1.3 rh wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800);
829 1.3 rh wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00
830 1.1 rh | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
831 1.1 rh | ((PAN_FRONT + pan) << APU_PAN_SHIFT));
832 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB
833 1.1 rh | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
834 1.3 rh wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8);
835 1.1 rh
836 1.1 rh if (ch->aputype == APUTYPE_16BITSTEREO)
837 1.1 rh wpwa |= APU_STEREO >> 1;
838 1.1 rh pan = -pan;
839 1.3 rh }
840 1.1 rh
841 1.1 rh wc_wrchctl(ess, apuch, ch->wcreg_tpl);
842 1.3 rh if (nch > 1)
843 1.3 rh wc_wrchctl(ess, apuch + 1, ch->wcreg_tpl);
844 1.1 rh
845 1.1 rh wp_wrapu(ess, apuch, APUREG_APUTYPE,
846 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
847 1.1 rh if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO)
848 1.1 rh wp_wrapu(ess, apuch + 1, APUREG_APUTYPE,
849 1.1 rh (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
850 1.1 rh
851 1.1 rh return 0;
852 1.1 rh }
853 1.1 rh
854 1.1 rh int
855 1.1 rh esm_trigger_input(void *sc, void *start, void *end, int blksize,
856 1.41 christos void (*intr)(void *), void *arg, const audio_params_t *param)
857 1.1 rh {
858 1.18 fredette size_t size;
859 1.18 fredette size_t mixsize;
860 1.30 kent struct esm_softc *ess;
861 1.30 kent struct esm_chinfo *ch;
862 1.30 kent struct esm_dma *p;
863 1.30 kent uint32_t chctl, choffset;
864 1.30 kent uint32_t speed, offset, wpwa, dv;
865 1.30 kent uint32_t mixoffset, mixdv;
866 1.30 kent int i, nch;
867 1.30 kent uint16_t apuch;
868 1.30 kent uint16_t reg;
869 1.18 fredette
870 1.18 fredette DPRINTF(ESM_DEBUG_DMA,
871 1.18 fredette ("esm_trigger_input(%p, %p, %p, 0x%x, %p, %p, %p)\n",
872 1.18 fredette sc, start, end, blksize, intr, arg, param));
873 1.30 kent ess = sc;
874 1.30 kent ch = &ess->rch;
875 1.30 kent nch = 1;
876 1.30 kent speed = ch->sample_rate;
877 1.30 kent apuch = ch->num << 1;
878 1.18 fredette
879 1.18 fredette #ifdef DIAGNOSTIC
880 1.18 fredette if (ess->ractive) {
881 1.18 fredette printf("%s: esm_trigger_input: already running",
882 1.49 cegger device_xname(ess->sc_dev));
883 1.18 fredette return EINVAL;
884 1.18 fredette }
885 1.18 fredette #endif
886 1.18 fredette
887 1.18 fredette ess->sc_rintr = intr;
888 1.18 fredette ess->sc_rarg = arg;
889 1.18 fredette p = &ess->sc_dma;
890 1.42 christos if ((char *)start != (char *)p->addr + MAESTRO_RECBUF_OFF) {
891 1.18 fredette printf("%s: esm_trigger_input: bad addr %p\n",
892 1.49 cegger device_xname(ess->sc_dev), start);
893 1.18 fredette return EINVAL;
894 1.18 fredette }
895 1.18 fredette
896 1.42 christos ess->rch.buffer = (void *)start;
897 1.18 fredette ess->rch.offset = 0;
898 1.18 fredette ess->rch.blocksize = blksize;
899 1.42 christos ess->rch.bufsize = ((char *)end - (char *)start);
900 1.18 fredette ess->rch.apublk = blksize >> 1;
901 1.18 fredette ess->ractive = 1;
902 1.18 fredette
903 1.42 christos size = (size_t)(((char *)end - (char *)start) >> 1);
904 1.18 fredette choffset = MAESTRO_RECBUF_OFF;
905 1.18 fredette switch (ch->aputype) {
906 1.18 fredette case APUTYPE_16BITSTEREO:
907 1.18 fredette size >>= 1;
908 1.18 fredette choffset = MAESTRO_RECBUF_L_OFF;
909 1.18 fredette ess->rch.apublk >>= 1;
910 1.18 fredette nch++;
911 1.18 fredette break;
912 1.18 fredette case APUTYPE_16BITLINEAR:
913 1.18 fredette break;
914 1.18 fredette default:
915 1.18 fredette ess->ractive = 0;
916 1.18 fredette return EINVAL;
917 1.18 fredette }
918 1.18 fredette
919 1.18 fredette mixsize = (MAESTRO_MIXBUF_SZ >> 1) >> 1;
920 1.18 fredette mixoffset = MAESTRO_MIXBUF_OFF;
921 1.18 fredette
922 1.18 fredette ess->rch.apubase = (choffset >> 1);
923 1.18 fredette ess->rch.apubuf = size;
924 1.18 fredette ess->rch.nextirq = ess->rch.apublk;
925 1.18 fredette
926 1.18 fredette set_timer(ess);
927 1.18 fredette wp_starttimer(ess);
928 1.18 fredette
929 1.18 fredette if (speed > 47999) speed = 47999;
930 1.18 fredette if (speed < 4000) speed = 4000;
931 1.18 fredette dv = (((speed % 48000) << 16) + 24000) / 48000
932 1.18 fredette + ((speed / 48000) << 16);
933 1.33 lukem mixdv = 65536; /* 48 kHz */
934 1.18 fredette
935 1.18 fredette for (i = 0; i < nch; i++) {
936 1.18 fredette
937 1.18 fredette /* Clear all rate conversion WP channel registers first. */
938 1.18 fredette for (reg = 0; reg < 15; reg++)
939 1.18 fredette wp_wrapu(ess, apuch + i, reg, 0);
940 1.18 fredette
941 1.18 fredette /* Program the WaveCache for the rate conversion WP channel. */
942 1.18 fredette chctl = (DMAADDR(p) + choffset - 0x10) &
943 1.18 fredette WAVCACHE_CHCTL_ADDRTAG_MASK;
944 1.18 fredette wc_wrchctl(ess, apuch + i, chctl);
945 1.18 fredette
946 1.18 fredette /* Program the rate conversion WP channel. */
947 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_FREQ_LOBYTE, APU_plus6dB
948 1.18 fredette | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT) | 0x08);
949 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_FREQ_HIWORD, dv >> 8);
950 1.18 fredette offset = choffset >> 1;
951 1.18 fredette wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK);
952 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_WAVESPACE, wpwa);
953 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_CURPTR, offset);
954 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_ENDPTR, offset + size);
955 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_LOOPLEN, size - 1);
956 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_EFFECTS_ENV, 0x00f0);
957 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_AMPLITUDE, 0xe800);
958 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_POSITION, 0x8f00
959 1.18 fredette | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
960 1.18 fredette | (PAN_FRONT << APU_PAN_SHIFT));
961 1.18 fredette wp_wrapu(ess, apuch + i, APUREG_ROUTE, apuch + 2 + i);
962 1.18 fredette
963 1.18 fredette DPRINTF(ESM_DEBUG_DMA,
964 1.26 kleink ("choffs=0x%x, wpwa=0x%x, offset=0x%x words, size=0x%lx words\n",
965 1.26 kleink choffset, wpwa, offset, (unsigned long int)size));
966 1.18 fredette
967 1.18 fredette /* Clear all mixer WP channel registers first. */
968 1.18 fredette for (reg = 0; reg < 15; reg++)
969 1.18 fredette wp_wrapu(ess, apuch + 2 + i, reg, 0);
970 1.18 fredette
971 1.18 fredette /* Program the WaveCache for the mixer WP channel. */
972 1.18 fredette chctl = (ess->rch.base + mixoffset - 0x10) &
973 1.18 fredette WAVCACHE_CHCTL_ADDRTAG_MASK;
974 1.18 fredette wc_wrchctl(ess, apuch + 2 + i, chctl);
975 1.18 fredette
976 1.18 fredette /* Program the mixer WP channel. */
977 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_FREQ_LOBYTE, APU_plus6dB
978 1.18 fredette | ((mixdv & 0xff) << APU_FREQ_LOBYTE_SHIFT) | 0x08);
979 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_FREQ_HIWORD, mixdv >> 8);
980 1.18 fredette offset = mixoffset >> 1;
981 1.18 fredette wpwa = APU_USE_SYSMEM | ((offset >> 8) & APU_64KPAGE_MASK);
982 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_WAVESPACE, wpwa);
983 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_CURPTR, offset);
984 1.30 kent wp_wrapu(ess, apuch + 2 + i, APUREG_ENDPTR,
985 1.18 fredette offset + mixsize);
986 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_LOOPLEN, mixsize);
987 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_EFFECTS_ENV, 0x00f0);
988 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_AMPLITUDE, 0xe800);
989 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_POSITION, 0x8f00
990 1.18 fredette | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
991 1.18 fredette | (PAN_FRONT << APU_PAN_SHIFT));
992 1.18 fredette wp_wrapu(ess, apuch + 2 + i, APUREG_ROUTE,
993 1.18 fredette ROUTE_PARALLEL + i);
994 1.18 fredette
995 1.18 fredette DPRINTF(ESM_DEBUG_DMA,
996 1.26 kleink ("mixoffs=0x%x, wpwa=0x%x, offset=0x%x words, size=0x%lx words\n",
997 1.26 kleink mixoffset, wpwa, offset, (unsigned long int)mixsize));
998 1.18 fredette
999 1.18 fredette /* Assume we're going to loop to do the right channel. */
1000 1.18 fredette choffset += MAESTRO_RECBUF_L_SZ;
1001 1.18 fredette mixoffset += MAESTRO_MIXBUF_SZ >> 1;
1002 1.18 fredette }
1003 1.18 fredette
1004 1.18 fredette wp_wrapu(ess, apuch, APUREG_APUTYPE,
1005 1.18 fredette (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) |
1006 1.18 fredette APU_DMA_ENABLED | 0xf);
1007 1.18 fredette if (nch > 1)
1008 1.18 fredette wp_wrapu(ess, apuch + 1, APUREG_APUTYPE,
1009 1.18 fredette (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) |
1010 1.18 fredette APU_DMA_ENABLED | 0xf);
1011 1.18 fredette wp_wrapu(ess, apuch + 2, APUREG_APUTYPE,
1012 1.18 fredette (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) |
1013 1.18 fredette APU_DMA_ENABLED | 0xf);
1014 1.18 fredette if (nch > 1)
1015 1.18 fredette wp_wrapu(ess, apuch + 3, APUREG_APUTYPE,
1016 1.18 fredette (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) |
1017 1.18 fredette APU_DMA_ENABLED | 0xf);
1018 1.18 fredette
1019 1.1 rh return 0;
1020 1.1 rh }
1021 1.1 rh
1022 1.1 rh int
1023 1.1 rh esm_halt_output(void *sc)
1024 1.1 rh {
1025 1.30 kent struct esm_softc *ess;
1026 1.30 kent struct esm_chinfo *ch;
1027 1.1 rh
1028 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_output(%p)\n", sc));
1029 1.30 kent ess = sc;
1030 1.30 kent ch = &ess->pch;
1031 1.1 rh
1032 1.1 rh wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE,
1033 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1034 1.1 rh wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE,
1035 1.1 rh APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1036 1.1 rh
1037 1.1 rh ess->pactive = 0;
1038 1.1 rh if (!ess->ractive)
1039 1.1 rh wp_stoptimer(ess);
1040 1.1 rh
1041 1.1 rh return 0;
1042 1.1 rh }
1043 1.1 rh
1044 1.1 rh int
1045 1.1 rh esm_halt_input(void *sc)
1046 1.1 rh {
1047 1.30 kent struct esm_softc *ess;
1048 1.30 kent struct esm_chinfo *ch;
1049 1.18 fredette
1050 1.18 fredette DPRINTF(ESM_DEBUG_PARAM, ("esm_halt_input(%p)\n", sc));
1051 1.30 kent ess = sc;
1052 1.30 kent ch = &ess->rch;
1053 1.18 fredette
1054 1.18 fredette wp_wrapu(ess, (ch->num << 1), APUREG_APUTYPE,
1055 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1056 1.18 fredette wp_wrapu(ess, (ch->num << 1) + 1, APUREG_APUTYPE,
1057 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1058 1.18 fredette wp_wrapu(ess, (ch->num << 1) + 2, APUREG_APUTYPE,
1059 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1060 1.18 fredette wp_wrapu(ess, (ch->num << 1) + 3, APUREG_APUTYPE,
1061 1.18 fredette APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1062 1.18 fredette
1063 1.18 fredette ess->ractive = 0;
1064 1.18 fredette if (!ess->pactive)
1065 1.18 fredette wp_stoptimer(ess);
1066 1.18 fredette
1067 1.1 rh return 0;
1068 1.1 rh }
1069 1.1 rh
1070 1.1 rh static inline u_int
1071 1.1 rh calc_timer_freq(struct esm_chinfo *ch)
1072 1.1 rh {
1073 1.1 rh u_int freq;
1074 1.1 rh
1075 1.1 rh freq = (ch->sample_rate + ch->apublk - 1) / ch->apublk;
1076 1.1 rh
1077 1.1 rh DPRINTF(ESM_DEBUG_TIMER,
1078 1.1 rh ("calc_timer_freq(%p): rate = %u, blk = 0x%x (0x%x): freq = %u\n",
1079 1.1 rh ch, ch->sample_rate, ch->apublk, ch->blocksize, freq));
1080 1.1 rh
1081 1.1 rh return freq;
1082 1.1 rh }
1083 1.1 rh
1084 1.1 rh static void
1085 1.1 rh set_timer(struct esm_softc *ess)
1086 1.1 rh {
1087 1.30 kent unsigned freq, freq2;
1088 1.1 rh
1089 1.30 kent freq = 0;
1090 1.1 rh if (ess->pactive)
1091 1.1 rh freq = calc_timer_freq(&ess->pch);
1092 1.1 rh
1093 1.1 rh if (ess->ractive) {
1094 1.1 rh freq2 = calc_timer_freq(&ess->rch);
1095 1.18 fredette if (freq2 > freq)
1096 1.1 rh freq = freq2;
1097 1.1 rh }
1098 1.1 rh
1099 1.18 fredette KASSERT(freq != 0);
1100 1.18 fredette
1101 1.1 rh for (; freq < MAESTRO_MINFREQ; freq <<= 1)
1102 1.30 kent continue;
1103 1.1 rh
1104 1.1 rh if (freq > 0)
1105 1.1 rh wp_settimer(ess, freq);
1106 1.1 rh }
1107 1.1 rh
1108 1.1 rh static void
1109 1.29 kent esmch_set_format(struct esm_chinfo *ch, const audio_params_t *p)
1110 1.1 rh {
1111 1.30 kent uint16_t wcreg_tpl;
1112 1.30 kent uint16_t aputype;
1113 1.1 rh
1114 1.30 kent wcreg_tpl = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
1115 1.30 kent aputype = APUTYPE_16BITLINEAR;
1116 1.1 rh if (p->channels == 2) {
1117 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_STEREO;
1118 1.1 rh aputype++;
1119 1.1 rh }
1120 1.29 kent if (p->precision == 8) {
1121 1.1 rh aputype += 2;
1122 1.25 simonb switch (p->encoding) {
1123 1.25 simonb case AUDIO_ENCODING_ULINEAR:
1124 1.25 simonb case AUDIO_ENCODING_ULINEAR_BE:
1125 1.25 simonb case AUDIO_ENCODING_ULINEAR_LE:
1126 1.1 rh wcreg_tpl |= WAVCACHE_CHCTL_U8;
1127 1.25 simonb break;
1128 1.25 simonb }
1129 1.1 rh }
1130 1.1 rh ch->wcreg_tpl = wcreg_tpl;
1131 1.1 rh ch->aputype = aputype;
1132 1.1 rh ch->sample_rate = p->sample_rate;
1133 1.1 rh
1134 1.1 rh DPRINTF(ESM_DEBUG_PARAM, ("esmch_set_format: "
1135 1.29 kent "numch=%u, prec=%u, tpl=0x%x, aputype=%d, rate=%u\n",
1136 1.29 kent p->channels, p->precision, wcreg_tpl, aputype, p->sample_rate));
1137 1.1 rh }
1138 1.1 rh
1139 1.18 fredette /*
1140 1.18 fredette * Since we can't record in true stereo, this function combines
1141 1.30 kent * the separately recorded left and right channels into the final
1142 1.18 fredette * buffer for the upper layer.
1143 1.18 fredette */
1144 1.18 fredette static void
1145 1.18 fredette esmch_combine_input(struct esm_softc *ess, struct esm_chinfo *ch)
1146 1.18 fredette {
1147 1.18 fredette size_t offset, resid, count;
1148 1.30 kent uint32_t *dst32s;
1149 1.30 kent const uint32_t *left32s, *right32s;
1150 1.30 kent uint32_t left32, right32;
1151 1.18 fredette
1152 1.18 fredette /* The current offset into the upper layer buffer. */
1153 1.18 fredette offset = ch->offset;
1154 1.18 fredette
1155 1.18 fredette /* The number of bytes left to combine. */
1156 1.18 fredette resid = ch->blocksize;
1157 1.18 fredette
1158 1.18 fredette while (resid > 0) {
1159 1.18 fredette
1160 1.18 fredette /* The 32-bit words for the left channel. */
1161 1.42 christos left32s = (const uint32_t *)((char *)ess->sc_dma.addr +
1162 1.18 fredette MAESTRO_RECBUF_L_OFF + offset / 2);
1163 1.18 fredette
1164 1.18 fredette /* The 32-bit words for the right channel. */
1165 1.42 christos right32s = (const uint32_t *)((char *)ess->sc_dma.addr +
1166 1.18 fredette MAESTRO_RECBUF_R_OFF + offset / 2);
1167 1.18 fredette
1168 1.18 fredette /* The pointer to the 32-bit words we will write. */
1169 1.42 christos dst32s = (uint32_t *)((char *)ch->buffer + offset);
1170 1.18 fredette
1171 1.18 fredette /* Get the number of bytes we will combine now. */
1172 1.18 fredette count = ch->bufsize - offset;
1173 1.18 fredette if (count > resid)
1174 1.18 fredette count = resid;
1175 1.18 fredette resid -= count;
1176 1.18 fredette offset += count;
1177 1.18 fredette if (offset == ch->bufsize)
1178 1.18 fredette offset = 0;
1179 1.18 fredette
1180 1.18 fredette /* Combine, writing two 32-bit words at a time. */
1181 1.18 fredette KASSERT((count & (sizeof(uint32_t) * 2 - 1)) == 0);
1182 1.30 kent count /= (sizeof(uint32_t) * 2);
1183 1.18 fredette while (count > 0) {
1184 1.18 fredette left32 = *(left32s++);
1185 1.18 fredette right32 = *(right32s++);
1186 1.18 fredette /* XXX this endian handling is half-baked at best */
1187 1.18 fredette #if BYTE_ORDER == LITTLE_ENDIAN
1188 1.18 fredette *(dst32s++) = (left32 & 0xFFFF) | (right32 << 16);
1189 1.18 fredette *(dst32s++) = (left32 >> 16) | (right32 & 0xFFFF0000);
1190 1.18 fredette #else /* BYTE_ORDER == BIG_ENDIAN */
1191 1.18 fredette *(dst32s++) = (left32 & 0xFFFF0000) | (right32 >> 16);
1192 1.18 fredette *(dst32s++) = (left32 << 16) | (right32 & 0xFFFF);
1193 1.18 fredette #endif /* BYTE_ORDER == BIG_ENDIAN */
1194 1.18 fredette count--;
1195 1.18 fredette }
1196 1.18 fredette }
1197 1.18 fredette
1198 1.18 fredette /* Update the offset. */
1199 1.18 fredette ch->offset = offset;
1200 1.18 fredette }
1201 1.1 rh
1202 1.1 rh /*
1203 1.1 rh * Audio interface glue functions
1204 1.1 rh */
1205 1.1 rh
1206 1.1 rh int
1207 1.41 christos esm_getdev (void *sc, struct audio_device *adp)
1208 1.1 rh {
1209 1.30 kent
1210 1.1 rh *adp = esm_device;
1211 1.1 rh return 0;
1212 1.1 rh }
1213 1.1 rh
1214 1.1 rh int
1215 1.41 christos esm_round_blocksize(void *sc, int blk, int mode,
1216 1.41 christos const audio_params_t *param)
1217 1.1 rh {
1218 1.30 kent
1219 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
1220 1.1 rh ("esm_round_blocksize(%p, 0x%x)", sc, blk));
1221 1.1 rh
1222 1.1 rh blk &= ~0x3f; /* keep good alignment */
1223 1.1 rh
1224 1.1 rh DPRINTF(ESM_DEBUG_PARAM, (" = 0x%x\n", blk));
1225 1.1 rh
1226 1.1 rh return blk;
1227 1.1 rh }
1228 1.1 rh
1229 1.1 rh int
1230 1.41 christos esm_query_encoding(void *sc, struct audio_encoding *fp)
1231 1.1 rh {
1232 1.30 kent
1233 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
1234 1.1 rh ("esm_query_encoding(%p, %d)\n", sc, fp->index));
1235 1.1 rh
1236 1.1 rh if (fp->index < 0 || fp->index >= MAESTRO_NENCODINGS)
1237 1.1 rh return EINVAL;
1238 1.1 rh
1239 1.1 rh *fp = esm_encoding[fp->index];
1240 1.1 rh return 0;
1241 1.1 rh }
1242 1.1 rh
1243 1.1 rh int
1244 1.41 christos esm_set_params(void *sc, int setmode, int usemode,
1245 1.29 kent audio_params_t *play, audio_params_t *rec,
1246 1.29 kent stream_filter_list_t *pfil, stream_filter_list_t *rfil)
1247 1.1 rh {
1248 1.30 kent struct esm_softc *ess;
1249 1.29 kent audio_params_t *p;
1250 1.29 kent const audio_params_t *hw_play, *hw_rec;
1251 1.29 kent stream_filter_list_t *fil;
1252 1.29 kent int mode, i;
1253 1.1 rh
1254 1.1 rh DPRINTF(ESM_DEBUG_PARAM,
1255 1.1 rh ("esm_set_params(%p, 0x%x, 0x%x, %p, %p)\n",
1256 1.1 rh sc, setmode, usemode, play, rec));
1257 1.30 kent ess = sc;
1258 1.29 kent hw_play = NULL;
1259 1.29 kent hw_rec = NULL;
1260 1.30 kent for (mode = AUMODE_RECORD; mode != -1;
1261 1.1 rh mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
1262 1.1 rh if ((setmode & mode) == 0)
1263 1.1 rh continue;
1264 1.1 rh
1265 1.1 rh p = mode == AUMODE_PLAY ? play : rec;
1266 1.1 rh
1267 1.1 rh if (p->sample_rate < 4000 || p->sample_rate > 48000 ||
1268 1.1 rh (p->precision != 8 && p->precision != 16) ||
1269 1.1 rh (p->channels != 1 && p->channels != 2))
1270 1.1 rh return EINVAL;
1271 1.1 rh
1272 1.29 kent fil = mode == AUMODE_PLAY ? pfil : rfil;
1273 1.29 kent i = auconv_set_converter(esm_formats, ESM_NFORMATS,
1274 1.29 kent mode, p, FALSE, fil);
1275 1.29 kent if (i < 0)
1276 1.1 rh return EINVAL;
1277 1.29 kent if (fil->req_size > 0)
1278 1.29 kent p = &fil->filters[0].param;
1279 1.29 kent if (mode == AUMODE_PLAY)
1280 1.29 kent hw_play = p;
1281 1.29 kent else
1282 1.29 kent hw_rec = p;
1283 1.1 rh }
1284 1.1 rh
1285 1.34 christos if (hw_play)
1286 1.29 kent esmch_set_format(&ess->pch, hw_play);
1287 1.1 rh
1288 1.34 christos if (hw_rec)
1289 1.29 kent esmch_set_format(&ess->rch, hw_rec);
1290 1.1 rh
1291 1.1 rh return 0;
1292 1.1 rh }
1293 1.1 rh
1294 1.1 rh int
1295 1.1 rh esm_set_port(void *sc, mixer_ctrl_t *cp)
1296 1.1 rh {
1297 1.30 kent struct esm_softc *ess;
1298 1.1 rh
1299 1.30 kent ess = sc;
1300 1.30 kent return ess->codec_if->vtbl->mixer_set_port(ess->codec_if, cp);
1301 1.1 rh }
1302 1.1 rh
1303 1.1 rh int
1304 1.1 rh esm_get_port(void *sc, mixer_ctrl_t *cp)
1305 1.1 rh {
1306 1.30 kent struct esm_softc *ess;
1307 1.1 rh
1308 1.30 kent ess = sc;
1309 1.30 kent return ess->codec_if->vtbl->mixer_get_port(ess->codec_if, cp);
1310 1.1 rh }
1311 1.1 rh
1312 1.1 rh int
1313 1.1 rh esm_query_devinfo(void *sc, mixer_devinfo_t *dip)
1314 1.1 rh {
1315 1.30 kent struct esm_softc *ess;
1316 1.1 rh
1317 1.30 kent ess = sc;
1318 1.30 kent return ess->codec_if->vtbl->query_devinfo(ess->codec_if, dip);
1319 1.1 rh }
1320 1.1 rh
1321 1.1 rh void *
1322 1.54 jmcneill esm_malloc(void *sc, int direction, size_t size)
1323 1.1 rh {
1324 1.30 kent struct esm_softc *ess;
1325 1.18 fredette int off;
1326 1.1 rh
1327 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1328 1.54 jmcneill ("esm_malloc(%p, %d, 0x%zd)", sc, direction, size));
1329 1.30 kent ess = sc;
1330 1.18 fredette /*
1331 1.18 fredette * Each buffer can only be allocated once.
1332 1.18 fredette */
1333 1.18 fredette if (ess->rings_alloced & direction) {
1334 1.1 rh DPRINTF(ESM_DEBUG_DMA, (" = 0 (ENOMEM)\n"));
1335 1.1 rh return 0;
1336 1.1 rh }
1337 1.1 rh
1338 1.18 fredette /*
1339 1.18 fredette * Mark this buffer as allocated and return its
1340 1.18 fredette * kernel virtual address.
1341 1.18 fredette */
1342 1.18 fredette ess->rings_alloced |= direction;
1343 1.18 fredette off = (direction == AUMODE_PLAY ?
1344 1.18 fredette MAESTRO_PLAYBUF_OFF : MAESTRO_RECBUF_OFF);
1345 1.18 fredette DPRINTF(ESM_DEBUG_DMA, (" = %p (DMAADDR 0x%x)\n",
1346 1.42 christos (char *)ess->sc_dma.addr + off,
1347 1.18 fredette (int)DMAADDR(&ess->sc_dma) + off));
1348 1.42 christos return (char *)ess->sc_dma.addr + off;
1349 1.1 rh }
1350 1.1 rh
1351 1.1 rh void
1352 1.54 jmcneill esm_free(void *sc, void *ptr, size_t size)
1353 1.1 rh {
1354 1.30 kent struct esm_softc *ess;
1355 1.1 rh
1356 1.54 jmcneill DPRINTF(ESM_DEBUG_DMA, ("esm_free(%p, %p, %zd)\n", sc, ptr, size));
1357 1.30 kent ess = sc;
1358 1.42 christos if ((char *)ptr == (char *)ess->sc_dma.addr + MAESTRO_PLAYBUF_OFF)
1359 1.18 fredette ess->rings_alloced &= ~AUMODE_PLAY;
1360 1.42 christos else if ((char *)ptr == (char *)ess->sc_dma.addr + MAESTRO_RECBUF_OFF)
1361 1.18 fredette ess->rings_alloced &= ~AUMODE_RECORD;
1362 1.1 rh }
1363 1.1 rh
1364 1.1 rh size_t
1365 1.41 christos esm_round_buffersize(void *sc, int direction, size_t size)
1366 1.1 rh {
1367 1.30 kent
1368 1.18 fredette if (size > MAESTRO_PLAYBUF_SZ)
1369 1.18 fredette size = MAESTRO_PLAYBUF_SZ;
1370 1.18 fredette if (size > MAESTRO_RECBUF_SZ)
1371 1.18 fredette size = MAESTRO_RECBUF_SZ;
1372 1.1 rh return size;
1373 1.1 rh }
1374 1.1 rh
1375 1.1 rh paddr_t
1376 1.1 rh esm_mappage(void *sc, void *mem, off_t off, int prot)
1377 1.1 rh {
1378 1.30 kent struct esm_softc *ess;
1379 1.1 rh
1380 1.1 rh DPRINTF(ESM_DEBUG_DMA,
1381 1.1 rh ("esm_mappage(%p, %p, 0x%lx, 0x%x)\n",
1382 1.1 rh sc, mem, (unsigned long)off, prot));
1383 1.30 kent ess = sc;
1384 1.1 rh if (off < 0)
1385 1.30 kent return -1;
1386 1.1 rh
1387 1.42 christos if ((char *)mem == (char *)ess->sc_dma.addr + MAESTRO_PLAYBUF_OFF)
1388 1.18 fredette off += MAESTRO_PLAYBUF_OFF;
1389 1.42 christos else if ((char *)mem == (char *)ess->sc_dma.addr + MAESTRO_RECBUF_OFF)
1390 1.18 fredette off += MAESTRO_RECBUF_OFF;
1391 1.18 fredette else
1392 1.18 fredette return -1;
1393 1.18 fredette return bus_dmamem_mmap(ess->dmat, ess->sc_dma.segs, ess->sc_dma.nsegs,
1394 1.18 fredette off, prot, BUS_DMA_WAITOK);
1395 1.1 rh }
1396 1.1 rh
1397 1.1 rh int
1398 1.41 christos esm_get_props(void *sc)
1399 1.1 rh {
1400 1.30 kent
1401 1.1 rh return AUDIO_PROP_MMAP | AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
1402 1.1 rh }
1403 1.1 rh
1404 1.1 rh
1405 1.1 rh /* -----------------------------
1406 1.1 rh * Bus space.
1407 1.1 rh */
1408 1.1 rh
1409 1.45 dyoung static int
1410 1.1 rh esm_intr(void *sc)
1411 1.1 rh {
1412 1.30 kent struct esm_softc *ess;
1413 1.30 kent uint16_t status;
1414 1.30 kent uint16_t pos;
1415 1.30 kent int ret;
1416 1.1 rh
1417 1.30 kent ess = sc;
1418 1.30 kent ret = 0;
1419 1.54 jmcneill
1420 1.54 jmcneill mutex_spin_enter(&ess->sc_intr_lock);
1421 1.1 rh status = bus_space_read_1(ess->st, ess->sh, PORT_HOSTINT_STAT);
1422 1.54 jmcneill if (!status) {
1423 1.54 jmcneill mutex_spin_exit(&ess->sc_intr_lock);
1424 1.1 rh return 0;
1425 1.54 jmcneill }
1426 1.1 rh
1427 1.1 rh /* Acknowledge all. */
1428 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
1429 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HOSTINT_STAT, 0);
1430 1.1 rh #if 0 /* XXX - HWVOL */
1431 1.1 rh if (status & HOSTINT_STAT_HWVOL) {
1432 1.1 rh u_int delta;
1433 1.1 rh delta = bus_space_read_1(ess->st, ess->sh, PORT_HWVOL_MASTER)
1434 1.1 rh - 0x88;
1435 1.1 rh if (delta & 0x11)
1436 1.1 rh mixer_set(device_get_softc(ess->dev),
1437 1.1 rh SOUND_MIXER_VOLUME, 0);
1438 1.1 rh else {
1439 1.1 rh mixer_set(device_get_softc(ess->dev),
1440 1.1 rh SOUND_MIXER_VOLUME,
1441 1.1 rh mixer_get(device_get_softc(ess->dev),
1442 1.1 rh SOUND_MIXER_VOLUME)
1443 1.1 rh + ((delta >> 5) & 0x7) - 4
1444 1.1 rh + ((delta << 7) & 0x700) - 0x400);
1445 1.1 rh }
1446 1.1 rh bus_space_write_1(ess->st, ess->sh, PORT_HWVOL_MASTER, 0x88);
1447 1.1 rh ret++;
1448 1.1 rh }
1449 1.1 rh #endif /* XXX - HWVOL */
1450 1.1 rh
1451 1.1 rh if (ess->pactive) {
1452 1.1 rh pos = wp_rdapu(ess, ess->pch.num << 1, APUREG_CURPTR);
1453 1.1 rh
1454 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
1455 1.1 rh wp_rdapu(ess, (ess->pch.num<<1)+1, APUREG_CURPTR)));
1456 1.1 rh
1457 1.18 fredette pos -= ess->pch.apubase;
1458 1.1 rh if (pos >= ess->pch.nextirq &&
1459 1.1 rh pos - ess->pch.nextirq < ess->pch.apubuf / 2) {
1460 1.1 rh ess->pch.nextirq += ess->pch.apublk;
1461 1.1 rh
1462 1.1 rh if (ess->pch.nextirq >= ess->pch.apubuf)
1463 1.1 rh ess->pch.nextirq = 0;
1464 1.1 rh
1465 1.1 rh if (ess->sc_pintr) {
1466 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("P\n"));
1467 1.1 rh ess->sc_pintr(ess->sc_parg);
1468 1.1 rh }
1469 1.1 rh
1470 1.1 rh }
1471 1.1 rh ret++;
1472 1.1 rh }
1473 1.1 rh
1474 1.1 rh if (ess->ractive) {
1475 1.1 rh pos = wp_rdapu(ess, ess->rch.num << 1, APUREG_CURPTR);
1476 1.1 rh
1477 1.1 rh DPRINTF(ESM_DEBUG_IRQ, (" %4.4x/%4.4x ", pos,
1478 1.1 rh wp_rdapu(ess, (ess->rch.num<<1)+1, APUREG_CURPTR)));
1479 1.1 rh
1480 1.18 fredette pos -= ess->rch.apubase;
1481 1.1 rh if (pos >= ess->rch.nextirq &&
1482 1.1 rh pos - ess->rch.nextirq < ess->rch.apubuf / 2) {
1483 1.1 rh ess->rch.nextirq += ess->rch.apublk;
1484 1.1 rh
1485 1.1 rh if (ess->rch.nextirq >= ess->rch.apubuf)
1486 1.1 rh ess->rch.nextirq = 0;
1487 1.1 rh
1488 1.1 rh if (ess->sc_rintr) {
1489 1.1 rh DPRINTF(ESM_DEBUG_IRQ, ("R\n"));
1490 1.18 fredette switch(ess->rch.aputype) {
1491 1.18 fredette case APUTYPE_16BITSTEREO:
1492 1.18 fredette esmch_combine_input(ess, &ess->rch);
1493 1.18 fredette break;
1494 1.18 fredette }
1495 1.18 fredette ess->sc_rintr(ess->sc_rarg);
1496 1.1 rh }
1497 1.1 rh
1498 1.1 rh }
1499 1.1 rh ret++;
1500 1.1 rh }
1501 1.54 jmcneill mutex_spin_exit(&ess->sc_intr_lock);
1502 1.1 rh
1503 1.1 rh return ret;
1504 1.1 rh }
1505 1.1 rh
1506 1.45 dyoung static void
1507 1.45 dyoung esm_freemem(struct esm_softc *sc, struct esm_dma *p)
1508 1.45 dyoung {
1509 1.45 dyoung if (p->size == 0)
1510 1.45 dyoung return;
1511 1.45 dyoung
1512 1.45 dyoung bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1513 1.45 dyoung
1514 1.45 dyoung bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1515 1.45 dyoung
1516 1.45 dyoung bus_dmamap_destroy(sc->dmat, p->map);
1517 1.45 dyoung
1518 1.45 dyoung bus_dmamap_unload(sc->dmat, p->map);
1519 1.45 dyoung
1520 1.45 dyoung p->size = 0;
1521 1.45 dyoung }
1522 1.45 dyoung
1523 1.45 dyoung static int
1524 1.1 rh esm_allocmem(struct esm_softc *sc, size_t size, size_t align,
1525 1.1 rh struct esm_dma *p)
1526 1.1 rh {
1527 1.1 rh int error;
1528 1.1 rh
1529 1.1 rh p->size = size;
1530 1.1 rh error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
1531 1.50 cegger p->segs, __arraycount(p->segs),
1532 1.54 jmcneill &p->nsegs, BUS_DMA_WAITOK);
1533 1.1 rh if (error)
1534 1.1 rh return error;
1535 1.1 rh
1536 1.1 rh error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
1537 1.54 jmcneill &p->addr, BUS_DMA_WAITOK|BUS_DMA_COHERENT);
1538 1.1 rh if (error)
1539 1.1 rh goto free;
1540 1.1 rh
1541 1.1 rh error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
1542 1.54 jmcneill 0, BUS_DMA_WAITOK, &p->map);
1543 1.1 rh if (error)
1544 1.1 rh goto unmap;
1545 1.1 rh
1546 1.1 rh error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
1547 1.54 jmcneill BUS_DMA_WAITOK);
1548 1.1 rh if (error)
1549 1.1 rh goto destroy;
1550 1.1 rh
1551 1.1 rh return 0;
1552 1.1 rh
1553 1.1 rh destroy:
1554 1.1 rh bus_dmamap_destroy(sc->dmat, p->map);
1555 1.1 rh unmap:
1556 1.1 rh bus_dmamem_unmap(sc->dmat, p->addr, p->size);
1557 1.1 rh free:
1558 1.1 rh bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
1559 1.1 rh
1560 1.45 dyoung p->size = 0;
1561 1.1 rh return error;
1562 1.1 rh }
1563 1.1 rh
1564 1.45 dyoung static int
1565 1.48 cegger esm_match(device_t dev, cfdata_t match, void *aux)
1566 1.1 rh {
1567 1.30 kent struct pci_attach_args *pa;
1568 1.1 rh
1569 1.30 kent pa = (struct pci_attach_args *)aux;
1570 1.1 rh switch (PCI_VENDOR(pa->pa_id)) {
1571 1.1 rh case PCI_VENDOR_ESSTECH:
1572 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) {
1573 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO1:
1574 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2:
1575 1.1 rh case PCI_PRODUCT_ESSTECH_MAESTRO2E:
1576 1.1 rh return 1;
1577 1.1 rh }
1578 1.1 rh
1579 1.1 rh case PCI_VENDOR_ESSTECH2:
1580 1.1 rh switch (PCI_PRODUCT(pa->pa_id)) {
1581 1.1 rh case PCI_PRODUCT_ESSTECH2_MAESTRO1:
1582 1.1 rh return 1;
1583 1.1 rh }
1584 1.1 rh }
1585 1.1 rh return 0;
1586 1.1 rh }
1587 1.1 rh
1588 1.45 dyoung static void
1589 1.45 dyoung esm_attach(device_t parent, device_t self, void *aux)
1590 1.1 rh {
1591 1.30 kent char devinfo[256];
1592 1.30 kent struct esm_softc *ess;
1593 1.30 kent struct pci_attach_args *pa;
1594 1.30 kent const char *intrstr;
1595 1.30 kent pci_chipset_tag_t pc;
1596 1.30 kent pcitag_t tag;
1597 1.1 rh pci_intr_handle_t ih;
1598 1.1 rh pcireg_t csr, data;
1599 1.1 rh int revision;
1600 1.30 kent uint16_t codec_data;
1601 1.30 kent uint16_t pcmbar;
1602 1.35 christos int error;
1603 1.1 rh
1604 1.45 dyoung ess = device_private(self);
1605 1.49 cegger ess->sc_dev = self;
1606 1.30 kent pa = (struct pci_attach_args *)aux;
1607 1.30 kent pc = pa->pa_pc;
1608 1.30 kent tag = pa->pa_tag;
1609 1.20 thorpej aprint_naive(": Audio controller\n");
1610 1.20 thorpej
1611 1.24 itojun pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
1612 1.1 rh revision = PCI_REVISION(pa->pa_class);
1613 1.20 thorpej aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision);
1614 1.1 rh
1615 1.54 jmcneill mutex_init(&ess->sc_lock, MUTEX_DEFAULT, IPL_NONE);
1616 1.54 jmcneill mutex_init(&ess->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
1617 1.54 jmcneill
1618 1.1 rh /* Enable the device. */
1619 1.1 rh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
1620 1.1 rh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
1621 1.1 rh csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
1622 1.1 rh
1623 1.1 rh /* Map I/O register */
1624 1.1 rh if (pci_mapreg_map(pa, PCI_CBIO, PCI_MAPREG_TYPE_IO, 0,
1625 1.45 dyoung &ess->st, &ess->sh, NULL, &ess->sz)) {
1626 1.49 cegger aprint_error_dev(ess->sc_dev, "can't map i/o space\n");
1627 1.54 jmcneill mutex_destroy(&ess->sc_lock);
1628 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock);
1629 1.1 rh return;
1630 1.1 rh }
1631 1.1 rh
1632 1.1 rh /* Initialize softc */
1633 1.1 rh ess->pch.num = 0;
1634 1.18 fredette ess->rch.num = 1;
1635 1.1 rh ess->dmat = pa->pa_dmat;
1636 1.1 rh ess->tag = tag;
1637 1.1 rh ess->pc = pc;
1638 1.1 rh ess->subid = pci_conf_read(pc, tag, PCI_SUBSYS_ID_REG);
1639 1.1 rh
1640 1.3 rh DPRINTF(ESM_DEBUG_PCI,
1641 1.3 rh ("%s: sub-system vendor 0x%4.4x, product 0x%4.4x\n",
1642 1.49 cegger device_xname(ess->sc_dev),
1643 1.3 rh PCI_VENDOR(ess->subid), PCI_PRODUCT(ess->subid)));
1644 1.3 rh
1645 1.1 rh /* Map and establish the interrupt. */
1646 1.1 rh if (pci_intr_map(pa, &ih)) {
1647 1.49 cegger aprint_error_dev(ess->sc_dev, "can't map interrupt\n");
1648 1.54 jmcneill mutex_destroy(&ess->sc_lock);
1649 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock);
1650 1.1 rh return;
1651 1.1 rh }
1652 1.1 rh intrstr = pci_intr_string(pc, ih);
1653 1.54 jmcneill ess->ih = pci_intr_establish(pc, ih, IPL_SCHED, esm_intr, self);
1654 1.1 rh if (ess->ih == NULL) {
1655 1.49 cegger aprint_error_dev(ess->sc_dev, "can't establish interrupt");
1656 1.1 rh if (intrstr != NULL)
1657 1.51 njoly aprint_error(" at %s", intrstr);
1658 1.51 njoly aprint_error("\n");
1659 1.54 jmcneill mutex_destroy(&ess->sc_lock);
1660 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock);
1661 1.1 rh return;
1662 1.1 rh }
1663 1.49 cegger aprint_normal_dev(ess->sc_dev, "interrupting at %s\n",
1664 1.47 cegger intrstr);
1665 1.1 rh
1666 1.1 rh /*
1667 1.1 rh * Setup PCI config registers
1668 1.1 rh */
1669 1.1 rh
1670 1.35 christos /* power up chip */
1671 1.46 dyoung if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
1672 1.35 christos pci_activate_null)) && error != EOPNOTSUPP) {
1673 1.49 cegger aprint_error_dev(ess->sc_dev, "cannot activate %d\n",
1674 1.35 christos error);
1675 1.54 jmcneill mutex_destroy(&ess->sc_lock);
1676 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock);
1677 1.35 christos return;
1678 1.35 christos }
1679 1.1 rh delay(100000);
1680 1.1 rh
1681 1.1 rh /* Disable all legacy emulations. */
1682 1.1 rh data = pci_conf_read(pc, tag, CONF_LEGACY);
1683 1.1 rh pci_conf_write(pc, tag, CONF_LEGACY, data | LEGACY_DISABLED);
1684 1.1 rh
1685 1.1 rh /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
1686 1.1 rh * Enable posted write.
1687 1.1 rh * Prefer PCI timing rather than that of ISA.
1688 1.1 rh * Don't swap L/R. */
1689 1.1 rh data = pci_conf_read(pc, tag, CONF_MAESTRO);
1690 1.1 rh data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
1691 1.1 rh data &= ~MAESTRO_SWAP_LR;
1692 1.1 rh pci_conf_write(pc, tag, CONF_MAESTRO, data);
1693 1.1 rh
1694 1.1 rh /* initialize sound chip */
1695 1.1 rh esm_init(ess);
1696 1.1 rh
1697 1.1 rh esm_read_codec(ess, 0, &codec_data);
1698 1.1 rh if (codec_data == 0x80) {
1699 1.49 cegger aprint_error_dev(ess->sc_dev, "PT101 codec detected!\n");
1700 1.54 jmcneill mutex_destroy(&ess->sc_lock);
1701 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock);
1702 1.1 rh return;
1703 1.1 rh }
1704 1.1 rh
1705 1.3 rh /*
1706 1.3 rh * Some cards and Notebooks appear to have left and right channels
1707 1.3 rh * reversed. Check if there is a corresponding quirk entry for
1708 1.3 rh * the subsystem vendor and product and if so, set the appropriate
1709 1.3 rh * codec flag.
1710 1.3 rh */
1711 1.3 rh if (esm_get_quirks(ess->subid) & ESM_QUIRKF_SWAPPEDCH) {
1712 1.3 rh ess->codec_flags |= AC97_HOST_SWAPPED_CHANNELS;
1713 1.3 rh }
1714 1.5 rh ess->codec_flags |= AC97_HOST_DONT_READ;
1715 1.3 rh
1716 1.1 rh /* initialize AC97 host interface */
1717 1.1 rh ess->host_if.arg = self;
1718 1.1 rh ess->host_if.attach = esm_attach_codec;
1719 1.1 rh ess->host_if.read = esm_read_codec;
1720 1.1 rh ess->host_if.write = esm_write_codec;
1721 1.1 rh ess->host_if.reset = esm_reset_codec;
1722 1.3 rh ess->host_if.flags = esm_flags_codec;
1723 1.1 rh
1724 1.54 jmcneill if (ac97_attach(&ess->host_if, self, &ess->sc_lock) != 0) {
1725 1.54 jmcneill mutex_destroy(&ess->sc_lock);
1726 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock);
1727 1.1 rh return;
1728 1.54 jmcneill }
1729 1.18 fredette
1730 1.18 fredette /* allocate our DMA region */
1731 1.18 fredette if (esm_allocmem(ess, MAESTRO_DMA_SZ, MAESTRO_DMA_ALIGN,
1732 1.18 fredette &ess->sc_dma)) {
1733 1.49 cegger aprint_error_dev(ess->sc_dev, "couldn't allocate memory!\n");
1734 1.54 jmcneill mutex_destroy(&ess->sc_lock);
1735 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock);
1736 1.18 fredette return;
1737 1.18 fredette }
1738 1.18 fredette ess->rings_alloced = 0;
1739 1.18 fredette
1740 1.18 fredette /* set DMA base address */
1741 1.18 fredette for (pcmbar = WAVCACHE_PCMBAR; pcmbar < WAVCACHE_PCMBAR + 4; pcmbar++)
1742 1.18 fredette wc_wrreg(ess, pcmbar,
1743 1.18 fredette DMAADDR(&ess->sc_dma) >> WAVCACHE_BASEADDR_SHIFT);
1744 1.1 rh
1745 1.49 cegger audio_attach_mi(&esm_hw_if, self, ess->sc_dev);
1746 1.7 ichiro
1747 1.44 jmcneill if (!pmf_device_register(self, esm_suspend, esm_resume))
1748 1.44 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
1749 1.7 ichiro }
1750 1.7 ichiro
1751 1.45 dyoung static void
1752 1.45 dyoung esm_childdet(device_t self, device_t child)
1753 1.45 dyoung {
1754 1.45 dyoung /* we hold no child references, so do nothing */
1755 1.45 dyoung }
1756 1.45 dyoung
1757 1.45 dyoung static int
1758 1.45 dyoung esm_detach(device_t self, int flags)
1759 1.45 dyoung {
1760 1.45 dyoung int rc;
1761 1.45 dyoung struct esm_softc *ess = device_private(self);
1762 1.45 dyoung
1763 1.45 dyoung if ((rc = config_detach_children(self, flags)) != 0)
1764 1.45 dyoung return rc;
1765 1.54 jmcneill pmf_device_deregister(self);
1766 1.45 dyoung
1767 1.45 dyoung /* free our DMA region */
1768 1.45 dyoung esm_freemem(ess, &ess->sc_dma);
1769 1.45 dyoung
1770 1.54 jmcneill if (ess->codec_if != NULL) {
1771 1.54 jmcneill mutex_enter(&ess->sc_lock);
1772 1.45 dyoung ess->codec_if->vtbl->detach(ess->codec_if);
1773 1.54 jmcneill mutex_exit(&ess->sc_lock);
1774 1.54 jmcneill }
1775 1.45 dyoung
1776 1.45 dyoung /* XXX Restore CONF_MAESTRO? */
1777 1.45 dyoung /* XXX Restore legacy emulations? */
1778 1.45 dyoung /* XXX Restore PCI config registers? */
1779 1.45 dyoung
1780 1.45 dyoung if (ess->ih != NULL)
1781 1.45 dyoung pci_intr_disestablish(ess->pc, ess->ih);
1782 1.45 dyoung
1783 1.45 dyoung bus_space_unmap(ess->st, ess->sh, ess->sz);
1784 1.54 jmcneill mutex_destroy(&ess->sc_lock);
1785 1.54 jmcneill mutex_destroy(&ess->sc_intr_lock);
1786 1.45 dyoung
1787 1.45 dyoung return 0;
1788 1.45 dyoung }
1789 1.45 dyoung
1790 1.44 jmcneill static bool
1791 1.53 dyoung esm_suspend(device_t dv, const pmf_qual_t *qual)
1792 1.1 rh {
1793 1.44 jmcneill struct esm_softc *ess = device_private(dv);
1794 1.1 rh
1795 1.54 jmcneill mutex_enter(&ess->sc_lock);
1796 1.54 jmcneill mutex_spin_enter(&ess->sc_intr_lock);
1797 1.1 rh wp_stoptimer(ess);
1798 1.1 rh bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1799 1.1 rh esm_halt_output(ess);
1800 1.1 rh esm_halt_input(ess);
1801 1.54 jmcneill mutex_spin_exit(&ess->sc_intr_lock);
1802 1.1 rh
1803 1.1 rh /* Power down everything except clock. */
1804 1.1 rh esm_write_codec(ess, AC97_REG_POWER, 0xdf00);
1805 1.1 rh delay(20);
1806 1.1 rh bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
1807 1.1 rh delay(1);
1808 1.54 jmcneill mutex_exit(&ess->sc_lock);
1809 1.1 rh
1810 1.44 jmcneill return true;
1811 1.1 rh }
1812 1.1 rh
1813 1.44 jmcneill static bool
1814 1.53 dyoung esm_resume(device_t dv, const pmf_qual_t *qual)
1815 1.1 rh {
1816 1.44 jmcneill struct esm_softc *ess = device_private(dv);
1817 1.38 jmcneill uint16_t pcmbar;
1818 1.1 rh
1819 1.1 rh delay(100000);
1820 1.54 jmcneill
1821 1.54 jmcneill mutex_enter(&ess->sc_lock);
1822 1.54 jmcneill mutex_spin_enter(&ess->sc_intr_lock);
1823 1.1 rh esm_init(ess);
1824 1.8 ichiro
1825 1.38 jmcneill /* set DMA base address */
1826 1.38 jmcneill for (pcmbar = WAVCACHE_PCMBAR; pcmbar < WAVCACHE_PCMBAR + 4; pcmbar++)
1827 1.38 jmcneill wc_wrreg(ess, pcmbar,
1828 1.38 jmcneill DMAADDR(&ess->sc_dma) >> WAVCACHE_BASEADDR_SHIFT);
1829 1.54 jmcneill mutex_spin_exit(&ess->sc_intr_lock);
1830 1.30 kent ess->codec_if->vtbl->restore_ports(ess->codec_if);
1831 1.54 jmcneill mutex_spin_enter(&ess->sc_intr_lock);
1832 1.8 ichiro #if 0
1833 1.1 rh if (mixer_reinit(dev)) {
1834 1.1 rh printf("%s: unable to reinitialize the mixer\n",
1835 1.49 cegger device_xname(ess->sc_dev));
1836 1.1 rh return ENXIO;
1837 1.1 rh }
1838 1.8 ichiro #endif
1839 1.1 rh
1840 1.8 ichiro #if TODO
1841 1.1 rh if (ess->pactive)
1842 1.1 rh esm_start_output(ess);
1843 1.1 rh if (ess->ractive)
1844 1.1 rh esm_start_input(ess);
1845 1.30 kent #endif
1846 1.1 rh if (ess->pactive || ess->ractive) {
1847 1.1 rh set_timer(ess);
1848 1.1 rh wp_starttimer(ess);
1849 1.1 rh }
1850 1.54 jmcneill mutex_spin_exit(&ess->sc_intr_lock);
1851 1.54 jmcneill mutex_exit(&ess->sc_lock);
1852 1.1 rh
1853 1.44 jmcneill return true;
1854 1.1 rh }
1855 1.54 jmcneill
1856 1.54 jmcneill void
1857 1.54 jmcneill esm_get_locks(void *addr, kmutex_t **intr, kmutex_t **proc)
1858 1.54 jmcneill {
1859 1.54 jmcneill struct esm_softc *esm;
1860 1.54 jmcneill
1861 1.54 jmcneill esm = addr;
1862 1.54 jmcneill *intr = &esm->sc_intr_lock;
1863 1.54 jmcneill *proc = &esm->sc_lock;
1864 1.54 jmcneill }
1865