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      1  1.20    andvar /*	$NetBSD: esmvar.h,v 1.20 2024/02/09 22:08:35 andvar Exp $	*/
      2   1.1        rh 
      3   1.1        rh /*-
      4   1.6  fredette  * Copyright (c) 2002, 2003 Matt Fredette
      5   1.6  fredette  * All rights reserved.
      6   1.6  fredette  *
      7   1.9    keihan  * Copyright (c) 2000, 2001 Rene Hexel <rh (at) NetBSD.org>
      8   1.1        rh  * All rights reserved.
      9   1.1        rh  *
     10   1.1        rh  * Copyright (c) 2000 Taku YAMAMOTO <taku (at) cent.saitama-u.ac.jp>
     11   1.1        rh  * All rights reserved.
     12   1.1        rh  *
     13   1.1        rh  * Redistribution and use in source and binary forms, with or without
     14   1.1        rh  * modification, are permitted provided that the following conditions
     15   1.1        rh  * are met:
     16   1.1        rh  * 1. Redistributions of source code must retain the above copyright
     17   1.1        rh  *    notice, this list of conditions and the following disclaimer.
     18   1.1        rh  * 2. Redistributions in binary form must reproduce the above copyright
     19   1.1        rh  *    notice, this list of conditions and the following disclaimer in the
     20   1.1        rh  *    documentation and/or other materials provided with the distribution.
     21   1.1        rh  *
     22   1.1        rh  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     23   1.1        rh  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24   1.1        rh  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25   1.1        rh  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     26   1.1        rh  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27   1.1        rh  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28   1.1        rh  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29   1.1        rh  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30   1.1        rh  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31   1.1        rh  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32   1.1        rh  * SUCH DAMAGE.
     33   1.1        rh  *
     34   1.1        rh  * Taku Id: maestro.c,v 1.12 2000/09/06 03:32:34 taku Exp
     35   1.1        rh  * FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.4 2000/12/18 01:36:35 cg Exp
     36   1.1        rh  *
     37   1.1        rh  */
     38   1.1        rh 
     39   1.1        rh /*
     40   1.1        rh  * Credits:
     41   1.1        rh  *
     42   1.1        rh  * This code is based on the FreeBSD driver written by Taku YAMAMOTO
     43   1.1        rh  *
     44   1.1        rh  *
     45   1.1        rh  * Original credits from the FreeBSD driver:
     46   1.1        rh  *
     47   1.1        rh  * Part of this code (especially in many magic numbers) was heavily inspired
     48   1.1        rh  * by the Linux driver originally written by
     49   1.1        rh  * Alan Cox <alan.cox (at) linux.org>, modified heavily by
     50   1.1        rh  * Zach Brown <zab (at) zabbo.net>.
     51   1.1        rh  *
     52   1.1        rh  * busdma()-ize and buffer size reduction were suggested by
     53   1.1        rh  * Cameron Grant <gandalf (at) vilnya.demon.co.uk>.
     54   1.1        rh  * Also he showed me the way to use busdma() suite.
     55   1.1        rh  *
     56   1.1        rh  * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
     57   1.1        rh  * were looked at by
     58   1.1        rh  * Munehiro Matsuda <haro (at) tk.kubota.co.jp>,
     59   1.1        rh  * who brought patches based on the Linux driver with some simplification.
     60   1.1        rh  */
     61   1.1        rh 
     62  1.20    andvar /* IRQ timer frequency limits */
     63   1.1        rh #define MAESTRO_MINFREQ	24
     64   1.1        rh #define MAESTRO_MAXFREQ	48000
     65   1.1        rh 
     66   1.6  fredette /*
     67   1.6  fredette  * This driver allocates a contiguous 256KB region of memory.
     68   1.6  fredette  * The Maestro's DMA interface, called the WaveCache, is weak
     69   1.6  fredette  * (or at least incorrectly documented), and forces us to keep
     70  1.12      kent  * things very simple.  This region is very carefully divided up
     71   1.6  fredette  * into 64KB quarters, making 64KB a fundamental constant for
     72  1.12      kent  * this implementation - and this is as large as we can allow
     73   1.6  fredette  * the upper-layer playback and record buffers to become.
     74   1.6  fredette  */
     75   1.6  fredette #define	MAESTRO_QUARTER_SZ	(64 * 1024)
     76   1.6  fredette 
     77   1.6  fredette /*
     78  1.12      kent  * The first quarter of memory is used while recording.  The
     79   1.6  fredette  * first 512 bytes of it is reserved as a scratch area for the
     80   1.6  fredette  * APUs that want to write (uninteresting, to us) FIFO status
     81   1.6  fredette  * information.  After some guard space, another 512 bytes is
     82   1.6  fredette  * reserved for the APUs doing mixing.  The remainder of this
     83   1.6  fredette  * quarter of memory is wasted.
     84   1.6  fredette  */
     85   1.6  fredette #define	MAESTRO_FIFO_OFF	(MAESTRO_QUARTER_SZ * 0)
     86   1.6  fredette #define	MAESTRO_FIFO_SZ		(512)
     87   1.6  fredette #define	MAESTRO_MIXBUF_OFF	(MAESTRO_FIFO_OFF + 4096)
     88   1.6  fredette #define	MAESTRO_MIXBUF_SZ	(512)
     89   1.6  fredette 
     90   1.6  fredette /*
     91   1.6  fredette  * The second quarter of memory is the playback buffer.
     92   1.6  fredette  */
     93   1.6  fredette #define	MAESTRO_PLAYBUF_OFF	(MAESTRO_QUARTER_SZ * 1)
     94   1.6  fredette #define	MAESTRO_PLAYBUF_SZ	MAESTRO_QUARTER_SZ
     95   1.6  fredette 
     96   1.6  fredette /*
     97  1.12      kent  * The third quarter of memory is the mono record buffer.
     98   1.6  fredette  * This is the only record buffer that the upper layer knows.
     99   1.6  fredette  * When recording in stereo, our driver combines (in software)
    100   1.6  fredette  * separately recorded left and right buffers here.
    101   1.6  fredette  */
    102   1.6  fredette #define	MAESTRO_RECBUF_OFF	(MAESTRO_QUARTER_SZ * 2)
    103   1.6  fredette #define	MAESTRO_RECBUF_SZ	MAESTRO_QUARTER_SZ
    104   1.6  fredette 
    105   1.6  fredette /*
    106   1.6  fredette  * The fourth quarter of memory is the stereo record buffer.
    107   1.6  fredette  * When recording in stereo, the left and right channels are
    108   1.6  fredette  * recorded separately into the two halves of this buffer.
    109   1.6  fredette  */
    110   1.6  fredette #define	MAESTRO_RECBUF_L_OFF	(MAESTRO_QUARTER_SZ * 3)
    111   1.6  fredette #define	MAESTRO_RECBUF_L_SZ	(MAESTRO_QUARTER_SZ / 2)
    112   1.6  fredette #define	MAESTRO_RECBUF_R_OFF	(MAESTRO_RECBUF_L_OFF + MAESTRO_RECBUF_L_SZ)
    113   1.6  fredette #define	MAESTRO_RECBUF_R_SZ	(MAESTRO_QUARTER_SZ / 2)
    114   1.6  fredette 
    115   1.6  fredette /*
    116   1.6  fredette  * The size and alignment of the entire region.  We keep
    117   1.6  fredette  * the region aligned to a 128KB boundary, since this should
    118   1.6  fredette  * force A16..A0 on all chip-generated addresses to correspond
    119   1.6  fredette  * exactly to APU register contents.
    120   1.6  fredette  */
    121   1.6  fredette #define	MAESTRO_DMA_SZ		(MAESTRO_QUARTER_SZ * 4)
    122   1.6  fredette #define	MAESTRO_DMA_ALIGN	(128 * 1024)
    123   1.6  fredette 
    124   1.1        rh struct esm_dma {
    125   1.1        rh 	bus_dmamap_t		map;
    126  1.14  christos 	void *			addr;
    127   1.1        rh 	bus_dma_segment_t	segs[1];
    128   1.1        rh 	int			nsegs;
    129   1.1        rh 	size_t			size;
    130   1.1        rh 	struct esm_dma		*next;
    131   1.1        rh };
    132   1.1        rh 
    133   1.1        rh #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
    134   1.1        rh #define KERNADDR(p) ((void *)((p)->addr))
    135   1.1        rh 
    136   1.1        rh struct esm_chinfo {
    137  1.12      kent 	uint32_t		base;		/* DMA base */
    138  1.14  christos 	void *			buffer;		/* upper layer buffer */
    139  1.12      kent 	uint32_t		offset;		/* offset into buffer */
    140  1.12      kent 	uint32_t		blocksize;	/* block size in bytes */
    141  1.12      kent 	uint32_t		bufsize;	/* buffer size in bytes */
    142   1.1        rh 	unsigned		num;		/* logical channel number */
    143  1.12      kent 	uint16_t		aputype;	/* APU channel type */
    144  1.12      kent 	uint16_t		apubase;	/* first sample number */
    145  1.12      kent 	uint16_t		apublk;		/* blk size in samples per ch */
    146  1.12      kent 	uint16_t		apubuf;		/* buf size in samples per ch */
    147  1.12      kent 	uint16_t		nextirq;	/* pos to trigger next IRQ at */
    148  1.12      kent 	uint16_t		wcreg_tpl;	/* wavecache tag and format */
    149  1.12      kent 	uint16_t		sample_rate;
    150   1.1        rh };
    151   1.1        rh 
    152   1.1        rh struct esm_softc {
    153  1.17    cegger 	device_t		sc_dev;
    154  1.18  jmcneill 	kmutex_t		sc_lock;
    155  1.18  jmcneill 	kmutex_t		sc_intr_lock;
    156   1.1        rh 
    157   1.1        rh 	bus_space_tag_t		st;
    158   1.1        rh 	bus_space_handle_t	sh;
    159  1.16    dyoung 	bus_size_t		sz;
    160   1.1        rh 
    161   1.1        rh 	pcitag_t		tag;
    162   1.1        rh 	pci_chipset_tag_t	pc;
    163   1.1        rh 	bus_dma_tag_t		dmat;
    164   1.1        rh 	pcireg_t		subid;
    165   1.1        rh 
    166   1.1        rh 	void			*ih;
    167   1.1        rh 
    168   1.1        rh 	struct ac97_codec_if	*codec_if;
    169   1.1        rh 	struct ac97_host_if	host_if;
    170   1.2        rh 	enum ac97_host_flags	codec_flags;
    171   1.1        rh 
    172   1.6  fredette 	struct esm_dma		sc_dma;
    173   1.6  fredette 	int			rings_alloced;
    174   1.1        rh 
    175   1.1        rh 	int			pactive, ractive;
    176   1.1        rh 	struct esm_chinfo	pch;
    177   1.1        rh 	struct esm_chinfo	rch;
    178   1.1        rh 
    179  1.12      kent 	void			(*sc_pintr)(void *);
    180  1.12      kent 	void			*sc_parg;
    181   1.1        rh 
    182  1.12      kent 	void			(*sc_rintr)(void *);
    183  1.12      kent 	void			*sc_rarg;
    184   1.1        rh };
    185   1.1        rh 
    186   1.5   thorpej enum esm_quirk_flags {
    187   1.5   thorpej 	ESM_QUIRKF_GPIO = 0x1,		/* needs GPIO operation */
    188   1.5   thorpej 	ESM_QUIRKF_SWAPPEDCH = 0x2,	/* left/right is reversed */
    189   1.5   thorpej };
    190   1.5   thorpej 
    191   1.2        rh struct esm_quirks {
    192   1.2        rh 	pci_vendor_id_t		eq_vendor;	/* subsystem vendor */
    193   1.2        rh 	pci_product_id_t	eq_product;	/* and product */
    194   1.2        rh 
    195   1.2        rh 	enum esm_quirk_flags	eq_quirks;	/* needed quirks */
    196   1.2        rh };
    197   1.2        rh 
    198  1.12      kent int	esm_read_codec(void *, uint8_t, uint16_t *);
    199  1.12      kent int	esm_write_codec(void *, uint8_t, uint16_t);
    200   1.1        rh int	esm_attach_codec(void *, struct ac97_codec_if *);
    201  1.10      kent int	esm_reset_codec(void *);
    202   1.2        rh enum ac97_host_flags	esm_flags_codec(void *);
    203   1.1        rh 
    204   1.1        rh void	esm_init(struct esm_softc *);
    205   1.1        rh void	esm_initcodec(struct esm_softc *);
    206   1.1        rh 
    207   1.1        rh int	esm_init_output(void *, void *, int);
    208   1.6  fredette int	esm_init_input(void *, void *, int);
    209   1.1        rh int	esm_trigger_output(void *, void *, void *, int, void (*)(void *),
    210  1.11      kent 	    void *, const audio_params_t *);
    211   1.1        rh int	esm_trigger_input(void *, void *, void *, int, void (*)(void *),
    212  1.11      kent 	    void *, const audio_params_t *);
    213   1.1        rh int	esm_halt_output(void *);
    214   1.1        rh int	esm_halt_input(void *);
    215   1.1        rh int	esm_getdev(void *, struct audio_device *);
    216  1.11      kent int	esm_round_blocksize(void *, int, int, const audio_params_t *);
    217  1.19     isaki int	esm_query_format(void *, audio_format_query_t *);
    218  1.19     isaki int	esm_set_format(void *, int,
    219  1.19     isaki 	    const audio_params_t *, const audio_params_t *,
    220  1.19     isaki 	    audio_filter_reg_t *, audio_filter_reg_t *);
    221   1.1        rh int	esm_set_port(void *, mixer_ctrl_t *);
    222   1.1        rh int	esm_get_port(void *, mixer_ctrl_t *);
    223   1.1        rh int	esm_query_devinfo(void *, mixer_devinfo_t *);
    224  1.18  jmcneill void	*esm_malloc(void *, int, size_t);
    225  1.18  jmcneill void	esm_free(void *, void *, size_t);
    226   1.1        rh size_t	esm_round_buffersize(void *, int, size_t);
    227   1.1        rh int	esm_get_props(void *);
    228  1.18  jmcneill void	esm_get_locks(void *, kmutex_t **, kmutex_t **);
    229   1.1        rh 
    230   1.2        rh enum esm_quirk_flags	esm_get_quirks(pcireg_t);
    231