fwohci_pci.c revision 1.34
1 /* $NetBSD: fwohci_pci.c,v 1.34 2010/01/08 19:56:51 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: fwohci_pci.c,v 1.34 2010/01/08 19:56:51 dyoung Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/socket.h> 38 #include <sys/device.h> 39 #include <sys/select.h> 40 41 #include <sys/bus.h> 42 #include <sys/intr.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/ieee1394/fw_port.h> 47 #include <dev/ieee1394/firewire.h> 48 #include <dev/ieee1394/firewirereg.h> 49 #include <dev/ieee1394/fwdma.h> 50 #include <dev/ieee1394/fwohcireg.h> 51 #include <dev/ieee1394/fwohcivar.h> 52 53 struct fwohci_pci_softc { 54 struct fwohci_softc psc_sc; 55 56 pci_chipset_tag_t psc_pc; 57 pcitag_t psc_tag; 58 59 void *psc_ih; 60 }; 61 62 static int fwohci_pci_match(device_t, cfdata_t, void *); 63 static void fwohci_pci_attach(device_t, device_t, void *); 64 65 static bool fwohci_pci_suspend(device_t, pmf_qual_t); 66 static bool fwohci_pci_resume(device_t, pmf_qual_t); 67 68 CFATTACH_DECL_NEW(fwohci_pci, sizeof(struct fwohci_pci_softc), 69 fwohci_pci_match, fwohci_pci_attach, NULL, NULL); 70 71 static int 72 fwohci_pci_match(device_t parent, cfdata_t match, 73 void *aux) 74 { 75 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 76 77 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 78 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_FIREWIRE && 79 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI) 80 return 1; 81 82 return 0; 83 } 84 85 static void 86 fwohci_pci_attach(device_t parent, device_t self, void *aux) 87 { 88 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 89 struct fwohci_pci_softc *psc = device_private(self); 90 char devinfo[256]; 91 char const *intrstr; 92 pci_intr_handle_t ih; 93 u_int32_t csr; 94 95 aprint_naive(": IEEE 1394 Controller\n"); 96 97 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 98 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 99 PCI_REVISION(pa->pa_class)); 100 101 psc->psc_sc.fc.dev = self; 102 psc->psc_sc.fc.dmat = pa->pa_dmat; 103 psc->psc_pc = pa->pa_pc; 104 psc->psc_tag = pa->pa_tag; 105 106 /* Map I/O registers */ 107 if (pci_mapreg_map(pa, PCI_OHCI_MAP_REGISTER, PCI_MAPREG_TYPE_MEM, 0, 108 &psc->psc_sc.bst, &psc->psc_sc.bsh, 109 NULL, &psc->psc_sc.bssize)) { 110 aprint_error_dev(self, "can't map OHCI register space\n"); 111 goto fail; 112 } 113 114 /* Disable interrupts, so we don't get any spurious ones. */ 115 OHCI_CSR_WRITE(&psc->psc_sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 116 117 /* Enable the device. */ 118 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 119 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 120 csr | PCI_COMMAND_MASTER_ENABLE); 121 122 /* Map and establish the interrupt. */ 123 if (pci_intr_map(pa, &ih)) { 124 aprint_error_dev(self, "couldn't map interrupt\n"); 125 goto fail; 126 } 127 intrstr = pci_intr_string(pa->pa_pc, ih); 128 psc->psc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, fwohci_filt, 129 &psc->psc_sc); 130 if (psc->psc_ih == NULL) { 131 aprint_error_dev(self, "couldn't establish interrupt"); 132 if (intrstr != NULL) 133 aprint_error(" at %s", intrstr); 134 aprint_error("\n"); 135 goto fail; 136 } 137 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 138 139 if (!pmf_device_register(self, fwohci_pci_suspend, fwohci_pci_resume)) 140 aprint_error_dev(self, "couldn't establish power handler\n"); 141 142 if (fwohci_init(&(psc->psc_sc), psc->psc_sc.fc.dev) != 0) { 143 pci_intr_disestablish(pa->pa_pc, psc->psc_ih); 144 bus_space_unmap(psc->psc_sc.bst, psc->psc_sc.bsh, 145 psc->psc_sc.bssize); 146 } 147 148 return; 149 150 fail: 151 /* In the event that we fail to attach, register a null pnp handler */ 152 if (!pmf_device_register(self, NULL, NULL)) 153 aprint_error_dev(self, "couldn't establish power handler\n"); 154 155 return; 156 } 157 158 static bool 159 fwohci_pci_suspend(device_t dv, pmf_qual_t qual) 160 { 161 struct fwohci_pci_softc *psc = device_private(dv); 162 int s; 163 164 s = splbio(); 165 fwohci_stop(&psc->psc_sc, psc->psc_sc.fc.dev); 166 splx(s); 167 168 return true; 169 } 170 171 static bool 172 fwohci_pci_resume(device_t dv, pmf_qual_t qual) 173 { 174 struct fwohci_pci_softc *psc = device_private(dv); 175 int s; 176 177 s = splbio(); 178 fwohci_resume(&psc->psc_sc, psc->psc_sc.fc.dev); 179 splx(s); 180 181 return true; 182 } 183
Indexes created Tue Sep 30 07:10:03 GMT 2025