fwohci_pci.c revision 1.39
1 /* $NetBSD: fwohci_pci.c,v 1.39 2010/04/29 06:41:27 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: fwohci_pci.c,v 1.39 2010/04/29 06:41:27 kiyohara Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/select.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/ieee1394/firewire.h> 47 #include <dev/ieee1394/firewirereg.h> 48 #include <dev/ieee1394/fwdma.h> 49 #include <dev/ieee1394/fwohcireg.h> 50 #include <dev/ieee1394/fwohcivar.h> 51 52 struct fwohci_pci_softc { 53 struct fwohci_softc psc_sc; 54 55 pci_chipset_tag_t psc_pc; 56 pcitag_t psc_tag; 57 58 void *psc_ih; 59 }; 60 61 static int fwohci_pci_match(device_t, cfdata_t, void *); 62 static void fwohci_pci_attach(device_t, device_t, void *); 63 static int fwohci_pci_detach(device_t, int); 64 65 static bool fwohci_pci_suspend(device_t, const pmf_qual_t *); 66 static bool fwohci_pci_resume(device_t, const pmf_qual_t *); 67 68 CFATTACH_DECL_NEW(fwohci_pci, sizeof(struct fwohci_pci_softc), 69 fwohci_pci_match, fwohci_pci_attach, fwohci_pci_detach, NULL); 70 71 static int 72 fwohci_pci_match(device_t parent, cfdata_t match, 73 void *aux) 74 { 75 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 76 77 /* 78 * XXX 79 * Firewire controllers used in some G3 PowerBooks hang the system 80 * when trying to discover devices - don't attach to those for now 81 * until someone with the right hardware can investigate 82 */ 83 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE) && 84 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_PBG3_FW)) 85 return 0; 86 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 87 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_FIREWIRE && 88 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI) 89 return 1; 90 91 return 0; 92 } 93 94 static void 95 fwohci_pci_attach(device_t parent, device_t self, void *aux) 96 { 97 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 98 struct fwohci_pci_softc *psc = device_private(self); 99 char devinfo[256]; 100 char const *intrstr; 101 pci_intr_handle_t ih; 102 uint32_t csr; 103 104 aprint_naive(": IEEE 1394 Controller\n"); 105 106 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 107 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 108 PCI_REVISION(pa->pa_class)); 109 110 psc->psc_sc.fc.dev = self; 111 psc->psc_sc.fc.dmat = pa->pa_dmat; 112 psc->psc_pc = pa->pa_pc; 113 psc->psc_tag = pa->pa_tag; 114 115 /* Map I/O registers */ 116 if (pci_mapreg_map(pa, PCI_OHCI_MAP_REGISTER, PCI_MAPREG_TYPE_MEM, 0, 117 &psc->psc_sc.bst, &psc->psc_sc.bsh, 118 NULL, &psc->psc_sc.bssize)) { 119 aprint_error_dev(self, "can't map OHCI register space\n"); 120 goto fail; 121 } 122 123 /* Disable interrupts, so we don't get any spurious ones. */ 124 OWRITE(&psc->psc_sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 125 126 /* Enable the device. */ 127 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 128 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 129 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 130 131 /* 132 * Some Sun FireWire controllers have their intpin register 133 * bogusly set to 0, although it should be 3. Correct that. 134 */ 135 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN) && 136 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_FIREWIRE)) 137 if (pa->pa_intrpin == 0) 138 pa->pa_intrpin = 3; 139 140 /* Map and establish the interrupt. */ 141 if (pci_intr_map(pa, &ih)) { 142 aprint_error_dev(self, "couldn't map interrupt\n"); 143 goto fail; 144 } 145 intrstr = pci_intr_string(pa->pa_pc, ih); 146 psc->psc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, fwohci_intr, 147 &psc->psc_sc); 148 if (psc->psc_ih == NULL) { 149 aprint_error_dev(self, "couldn't establish interrupt"); 150 if (intrstr != NULL) 151 aprint_error(" at %s", intrstr); 152 aprint_error("\n"); 153 goto fail; 154 } 155 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 156 157 if (!pmf_device_register(self, fwohci_pci_suspend, fwohci_pci_resume)) 158 aprint_error_dev(self, "couldn't establish power handler\n"); 159 160 if (fwohci_init(&psc->psc_sc) != 0) { 161 pci_intr_disestablish(pa->pa_pc, psc->psc_ih); 162 bus_space_unmap(psc->psc_sc.bst, psc->psc_sc.bsh, 163 psc->psc_sc.bssize); 164 } 165 166 return; 167 168 fail: 169 /* In the event that we fail to attach, register a null pnp handler */ 170 if (!pmf_device_register(self, NULL, NULL)) 171 aprint_error_dev(self, "couldn't establish power handler\n"); 172 173 return; 174 } 175 176 static int 177 fwohci_pci_detach(device_t self, int flags) 178 { 179 struct fwohci_pci_softc *psc = device_private(self); 180 int rv; 181 182 pmf_device_deregister(self); 183 rv = fwohci_detach(&psc->psc_sc, flags); 184 if (rv) 185 return rv; 186 187 if (psc->psc_ih != NULL) { 188 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 189 psc->psc_ih = NULL; 190 } 191 if (psc->psc_sc.bssize) { 192 bus_space_unmap(psc->psc_sc.bst, psc->psc_sc.bsh, 193 psc->psc_sc.bssize); 194 psc->psc_sc.bssize = 0; 195 } 196 return 0; 197 } 198 199 static bool 200 fwohci_pci_suspend(device_t dv, const pmf_qual_t *qual) 201 { 202 struct fwohci_pci_softc *psc = device_private(dv); 203 int s; 204 205 s = splbio(); 206 fwohci_stop(&psc->psc_sc); 207 splx(s); 208 209 return true; 210 } 211 212 static bool 213 fwohci_pci_resume(device_t dv, const pmf_qual_t *qual) 214 { 215 struct fwohci_pci_softc *psc = device_private(dv); 216 int s; 217 218 s = splbio(); 219 fwohci_resume(&psc->psc_sc); 220 splx(s); 221 222 return true; 223 } 224
Indexes created Mon Sep 29 21:09:56 GMT 2025