fwohci_pci.c revision 1.46
1 /* $NetBSD: fwohci_pci.c,v 1.46 2018/03/31 17:54:53 sevan Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: fwohci_pci.c,v 1.46 2018/03/31 17:54:53 sevan Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/select.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/ieee1394/firewire.h> 47 #include <dev/ieee1394/firewirereg.h> 48 #include <dev/ieee1394/fwdma.h> 49 #include <dev/ieee1394/fwohcireg.h> 50 #include <dev/ieee1394/fwohcivar.h> 51 52 struct fwohci_pci_softc { 53 struct fwohci_softc psc_sc; 54 55 pci_chipset_tag_t psc_pc; 56 pcitag_t psc_tag; 57 58 void *psc_ih; 59 }; 60 61 static int fwohci_pci_match(device_t, cfdata_t, void *); 62 static void fwohci_pci_attach(device_t, device_t, void *); 63 static int fwohci_pci_detach(device_t, int); 64 65 static bool fwohci_pci_suspend(device_t, const pmf_qual_t *); 66 static bool fwohci_pci_resume(device_t, const pmf_qual_t *); 67 68 CFATTACH_DECL_NEW(fwohci_pci, sizeof(struct fwohci_pci_softc), 69 fwohci_pci_match, fwohci_pci_attach, fwohci_pci_detach, NULL); 70 71 static int 72 fwohci_pci_match(device_t parent, cfdata_t match, void *aux) 73 { 74 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 75 76 /* 77 * XXX 78 * UniNorth Firewire controller commonly found in Pismo G3 PowerBooks, 79 * G4 Titanium PowerBooks and some iMac G3s, hang the system 80 * when trying to discover devices - don't attach to those for now 81 * until someone with the right hardware can investigate. 82 * These controllers are based on the Ti TSB41AB1 chipset. 83 */ 84 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE) && 85 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_UNINORTH_FW)) 86 return 0; 87 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 88 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_FIREWIRE && 89 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI) 90 return 1; 91 92 return 0; 93 } 94 95 static void 96 fwohci_pci_attach(device_t parent, device_t self, void *aux) 97 { 98 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 99 struct fwohci_pci_softc *psc = device_private(self); 100 char const *intrstr; 101 pci_intr_handle_t ih; 102 uint32_t csr; 103 char intrbuf[PCI_INTRSTR_LEN]; 104 105 pci_aprint_devinfo(pa, "IEEE 1394 Controller"); 106 107 fwohci_init(&psc->psc_sc); 108 109 psc->psc_sc.fc.dev = self; 110 psc->psc_sc.fc.dmat = pa->pa_dmat; 111 psc->psc_pc = pa->pa_pc; 112 psc->psc_tag = pa->pa_tag; 113 114 /* Map I/O registers */ 115 if (pci_mapreg_map(pa, PCI_OHCI_MAP_REGISTER, PCI_MAPREG_TYPE_MEM, 0, 116 &psc->psc_sc.bst, &psc->psc_sc.bsh, NULL, &psc->psc_sc.bssize)) { 117 aprint_error_dev(self, "can't map OHCI register space\n"); 118 goto fail; 119 } 120 121 /* Disable interrupts, so we don't get any spurious ones. */ 122 OWRITE(&psc->psc_sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 123 124 /* Enable the device. */ 125 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 126 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 127 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 128 129 /* 130 * Some Sun FireWire controllers have their intpin register 131 * bogusly set to 0, although it should be 3. Correct that. 132 */ 133 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN) && 134 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_FIREWIRE)) 135 if (pa->pa_intrpin == 0) 136 pa->pa_intrpin = 3; 137 138 /* Map and establish the interrupt. */ 139 if (pci_intr_map(pa, &ih)) { 140 aprint_error_dev(self, "couldn't map interrupt\n"); 141 goto fail; 142 } 143 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 144 psc->psc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_BIO, 145 fwohci_intr, &psc->psc_sc, device_xname(self)); 146 if (psc->psc_ih == NULL) { 147 aprint_error_dev(self, "couldn't establish interrupt"); 148 if (intrstr != NULL) 149 aprint_error(" at %s", intrstr); 150 aprint_error("\n"); 151 goto fail; 152 } 153 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 154 155 if (fwohci_attach(&psc->psc_sc) != 0) 156 goto fail; 157 158 if (!pmf_device_register(self, fwohci_pci_suspend, fwohci_pci_resume)) 159 aprint_error_dev(self, "couldn't establish power handler\n"); 160 161 return; 162 163 fail: 164 /* In the event that we fail to attach, register a null pnp handler */ 165 if (!pmf_device_register(self, NULL, NULL)) 166 aprint_error_dev(self, "couldn't establish power handler\n"); 167 168 return; 169 } 170 171 static int 172 fwohci_pci_detach(device_t self, int flags) 173 { 174 struct fwohci_pci_softc *psc = device_private(self); 175 int rv; 176 177 pmf_device_deregister(self); 178 rv = fwohci_detach(&psc->psc_sc, flags); 179 if (rv) 180 return rv; 181 182 if (psc->psc_ih != NULL) { 183 pci_intr_disestablish(psc->psc_pc, psc->psc_ih); 184 psc->psc_ih = NULL; 185 } 186 if (psc->psc_sc.bssize) { 187 bus_space_unmap(psc->psc_sc.bst, psc->psc_sc.bsh, 188 psc->psc_sc.bssize); 189 psc->psc_sc.bssize = 0; 190 } 191 return 0; 192 } 193 194 static bool 195 fwohci_pci_suspend(device_t dv, const pmf_qual_t *qual) 196 { 197 struct fwohci_pci_softc *psc = device_private(dv); 198 int s; 199 200 s = splbio(); 201 fwohci_stop(&psc->psc_sc); 202 splx(s); 203 204 return true; 205 } 206 207 static bool 208 fwohci_pci_resume(device_t dv, const pmf_qual_t *qual) 209 { 210 struct fwohci_pci_softc *psc = device_private(dv); 211 int s; 212 213 s = splbio(); 214 fwohci_resume(&psc->psc_sc); 215 splx(s); 216 217 return true; 218 } 219
Indexes created Mon Sep 29 21:09:56 GMT 2025