fwohci_pci.c revision 1.5
1 /* $NetBSD: fwohci_pci.c,v 1.5 2000/12/13 11:30:14 enami Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/types.h> 42 #include <sys/socket.h> 43 #include <sys/device.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/ieee1394/ieee1394reg.h> 51 #include <dev/ieee1394/ieee1394var.h> 52 #include <dev/ieee1394/fwohcireg.h> 53 #include <dev/ieee1394/fwohcivar.h> 54 55 struct fwohci_pci_softc { 56 struct fwohci_softc psc_sc; 57 pci_chipset_tag_t psc_pc; 58 void *psc_ih; 59 }; 60 61 static int fwohci_pci_match __P((struct device *, struct cfdata *, void *)); 62 static void fwohci_pci_attach __P((struct device *, struct device *, void *)); 63 64 struct cfattach fwohci_pci_ca = { 65 sizeof(struct fwohci_pci_softc), fwohci_pci_match, fwohci_pci_attach, 66 #if 0 67 fwohci_pci_detach, fwohci_activate 68 #endif 69 }; 70 71 static int 72 fwohci_pci_match(struct device *parent, struct cfdata *match, void *aux) 73 { 74 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 75 76 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS && 77 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_FIREWIRE && 78 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI) 79 return 1; 80 81 return 0; 82 } 83 84 static void 85 fwohci_pci_attach(struct device *parent, struct device *self, void *aux) 86 { 87 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 88 struct fwohci_pci_softc *psc = (struct fwohci_pci_softc *) self; 89 char devinfo[256]; 90 char const *intrstr; 91 pci_intr_handle_t ih; 92 u_int32_t csr; 93 94 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 95 printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class)); 96 97 psc->psc_sc.sc_dmat = pa->pa_dmat; 98 psc->psc_pc = pa->pa_pc; 99 100 /* Map I/O registers */ 101 if (pci_mapreg_map(pa, PCI_OHCI_MAP_REGISTER, PCI_MAPREG_TYPE_MEM, 0, 102 &psc->psc_sc.sc_memt, &psc->psc_sc.sc_memh, 103 NULL, &psc->psc_sc.sc_memsize)) { 104 printf("%s: can't map OCHI register space\n", self->dv_xname); 105 return; 106 } 107 108 /* Disable interrupts, so we don't get any spurious ones. */ 109 OHCI_CSR_WRITE(&psc->psc_sc, OHCI_REG_IntMaskClear, OHCI_Int_MasterEnable); 110 111 /* Enable the device. */ 112 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 113 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 114 csr | PCI_COMMAND_MASTER_ENABLE); 115 116 /* Map and establish the interrupt. */ 117 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 118 pa->pa_intrline, &ih)) { 119 printf("%s: couldn't map interrupt\n", self->dv_xname); 120 return; 121 } 122 intrstr = pci_intr_string(pa->pa_pc, ih); 123 psc->psc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, fwohci_intr, &psc->psc_sc); 124 if (psc->psc_ih == NULL) { 125 printf("%s: couldn't establish interrupt", self->dv_xname); 126 if (intrstr != NULL) 127 printf(" at %s", intrstr); 128 printf("\n"); 129 return; 130 } 131 printf("%s: interrupting at %s\n", self->dv_xname, intrstr); 132 133 if (fwohci_init(&psc->psc_sc, pci_intr_evcnt(pa->pa_pc, ih)) != 0) { 134 pci_intr_disestablish(pa->pa_pc, psc->psc_ih); 135 bus_space_unmap(psc->psc_sc.sc_memt, psc->psc_sc.sc_memh, 136 psc->psc_sc.sc_memsize); 137 } 138 } 139
Indexes created Mon Sep 29 18:09:42 GMT 2025