geodeide.c revision 1.2.2.5
1 1.2.2.5 skrll /* $NetBSD: geodeide.c,v 1.2.2.5 2004/09/18 14:49:03 skrll Exp $ */ 2 1.2.2.2 skrll 3 1.2.2.2 skrll /* 4 1.2.2.2 skrll * Copyright (c) 2004 Manuel Bouyer. 5 1.2.2.2 skrll * 6 1.2.2.2 skrll * Redistribution and use in source and binary forms, with or without 7 1.2.2.2 skrll * modification, are permitted provided that the following conditions 8 1.2.2.2 skrll * are met: 9 1.2.2.2 skrll * 1. Redistributions of source code must retain the above copyright 10 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer. 11 1.2.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.2.2.2 skrll * notice, this list of conditions and the following disclaimer in the 13 1.2.2.2 skrll * documentation and/or other materials provided with the distribution. 14 1.2.2.2 skrll * 3. All advertising materials mentioning features or use of this software 15 1.2.2.2 skrll * must display the following acknowledgement: 16 1.2.2.2 skrll * This product includes software developed by Manuel Bouyer. 17 1.2.2.2 skrll * 4. The name of the author may not be used to endorse or promote products 18 1.2.2.2 skrll * derived from this software without specific prior written permission. 19 1.2.2.2 skrll * 20 1.2.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 1.2.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 1.2.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 1.2.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 1.2.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 1.2.2.2 skrll * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.2.2.2 skrll * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 1.2.2.2 skrll * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 1.2.2.2 skrll * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 1.2.2.2 skrll * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 skrll * 31 1.2.2.2 skrll */ 32 1.2.2.2 skrll 33 1.2.2.2 skrll /* 34 1.2.2.3 skrll * Driver for the IDE part of the AMD Geode CS5530A companion chip 35 1.2.2.3 skrll * and AMD Geode SC1100. 36 1.2.2.2 skrll * Docs available from AMD's web site 37 1.2.2.2 skrll */ 38 1.2.2.2 skrll 39 1.2.2.2 skrll #include <sys/cdefs.h> 40 1.2.2.5 skrll __KERNEL_RCSID(0, "$NetBSD: geodeide.c,v 1.2.2.5 2004/09/18 14:49:03 skrll Exp $"); 41 1.2.2.2 skrll 42 1.2.2.2 skrll #include <sys/param.h> 43 1.2.2.2 skrll #include <sys/systm.h> 44 1.2.2.2 skrll 45 1.2.2.3 skrll #include <uvm/uvm_extern.h> 46 1.2.2.3 skrll 47 1.2.2.2 skrll #include <dev/pci/pcivar.h> 48 1.2.2.2 skrll #include <dev/pci/pcidevs.h> 49 1.2.2.2 skrll #include <dev/pci/pciidereg.h> 50 1.2.2.2 skrll #include <dev/pci/pciidevar.h> 51 1.2.2.2 skrll 52 1.2.2.2 skrll #include <dev/pci/pciide_geode_reg.h> 53 1.2.2.2 skrll 54 1.2.2.2 skrll static void geodeide_chip_map(struct pciide_softc *, 55 1.2.2.2 skrll struct pci_attach_args *); 56 1.2.2.4 skrll static void geodeide_setup_channel(struct ata_channel *); 57 1.2.2.2 skrll 58 1.2.2.2 skrll static int geodeide_match(struct device *, struct cfdata *, void *); 59 1.2.2.2 skrll static void geodeide_attach(struct device *, struct device *, void *); 60 1.2.2.2 skrll 61 1.2.2.2 skrll CFATTACH_DECL(geodeide, sizeof(struct pciide_softc), 62 1.2.2.2 skrll geodeide_match, geodeide_attach, NULL, NULL); 63 1.2.2.2 skrll 64 1.2.2.2 skrll static const struct pciide_product_desc pciide_geode_products[] = { 65 1.2.2.2 skrll { PCI_PRODUCT_CYRIX_CX5530_IDE, 66 1.2.2.2 skrll 0, 67 1.2.2.2 skrll "AMD Geode CX5530 IDE controller", 68 1.2.2.2 skrll geodeide_chip_map, 69 1.2.2.2 skrll }, 70 1.2.2.3 skrll { PCI_PRODUCT_NS_SC1100_IDE, 71 1.2.2.3 skrll 0, 72 1.2.2.3 skrll "AMD Geode SC1100 IDE controller", 73 1.2.2.3 skrll geodeide_chip_map, 74 1.2.2.3 skrll }, 75 1.2.2.2 skrll { 0, 76 1.2.2.2 skrll 0, 77 1.2.2.2 skrll NULL, 78 1.2.2.2 skrll NULL, 79 1.2.2.2 skrll }, 80 1.2.2.2 skrll }; 81 1.2.2.2 skrll 82 1.2.2.2 skrll static int 83 1.2.2.2 skrll geodeide_match(struct device *parent, struct cfdata *match, void *aux) 84 1.2.2.2 skrll { 85 1.2.2.2 skrll struct pci_attach_args *pa = aux; 86 1.2.2.2 skrll 87 1.2.2.3 skrll if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYRIX || 88 1.2.2.3 skrll PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS) && 89 1.2.2.3 skrll PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 90 1.2.2.3 skrll PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 91 1.2.2.3 skrll pciide_lookup_product(pa->pa_id, pciide_geode_products)) 92 1.2.2.2 skrll return(2); 93 1.2.2.2 skrll return (0); 94 1.2.2.2 skrll } 95 1.2.2.2 skrll 96 1.2.2.2 skrll static void 97 1.2.2.2 skrll geodeide_attach(struct device *parent, struct device *self, void *aux) 98 1.2.2.2 skrll { 99 1.2.2.2 skrll struct pci_attach_args *pa = aux; 100 1.2.2.2 skrll struct pciide_softc *sc = (void *)self; 101 1.2.2.2 skrll 102 1.2.2.2 skrll pciide_common_attach(sc, pa, 103 1.2.2.2 skrll pciide_lookup_product(pa->pa_id, pciide_geode_products)); 104 1.2.2.2 skrll } 105 1.2.2.2 skrll 106 1.2.2.2 skrll static void 107 1.2.2.2 skrll geodeide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 108 1.2.2.2 skrll { 109 1.2.2.2 skrll struct pciide_channel *cp; 110 1.2.2.2 skrll int channel; 111 1.2.2.2 skrll bus_size_t cmdsize, ctlsize; 112 1.2.2.2 skrll 113 1.2.2.2 skrll if (pciide_chipen(sc, pa) == 0) 114 1.2.2.2 skrll return; 115 1.2.2.2 skrll 116 1.2.2.2 skrll aprint_normal("%s: bus-master DMA support present", 117 1.2.2.4 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 118 1.2.2.2 skrll pciide_mapreg_dma(sc, pa); 119 1.2.2.2 skrll aprint_normal("\n"); 120 1.2.2.2 skrll if (sc->sc_dma_ok) { 121 1.2.2.4 skrll sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 122 1.2.2.2 skrll sc->sc_wdcdev.irqack = pciide_irqack; 123 1.2.2.2 skrll } 124 1.2.2.4 skrll sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 125 1.2.2.4 skrll sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 126 1.2.2.4 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 127 1.2.2.4 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = geodeide_setup_channel; 128 1.2.2.4 skrll sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 129 1.2.2.4 skrll sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 130 1.2.2.4 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 131 1.2.2.2 skrll 132 1.2.2.3 skrll /* 133 1.2.2.3 skrll * Soekris Engineering Issue #0003: 134 1.2.2.3 skrll * "The SC1100 built in busmaster IDE controller is pretty 135 1.2.2.3 skrll * standard, but have two bugs: data transfers need to be 136 1.2.2.3 skrll * dword aligned and it cannot do an exact 64Kbyte data 137 1.2.2.3 skrll * transfer." 138 1.2.2.3 skrll */ 139 1.2.2.3 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SC1100_IDE) { 140 1.2.2.3 skrll if (sc->sc_dma_boundary == 0x10000) 141 1.2.2.3 skrll sc->sc_dma_boundary -= PAGE_SIZE; 142 1.2.2.3 skrll 143 1.2.2.3 skrll if (sc->sc_dma_maxsegsz == 0x10000) 144 1.2.2.3 skrll sc->sc_dma_maxsegsz -= PAGE_SIZE; 145 1.2.2.3 skrll } 146 1.2.2.3 skrll 147 1.2.2.4 skrll wdc_allocate_regs(&sc->sc_wdcdev); 148 1.2.2.4 skrll 149 1.2.2.4 skrll for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 150 1.2.2.4 skrll channel++) { 151 1.2.2.2 skrll cp = &sc->pciide_channels[channel]; 152 1.2.2.2 skrll /* controller is compat-only */ 153 1.2.2.2 skrll if (pciide_chansetup(sc, channel, 0) == 0) 154 1.2.2.2 skrll continue; 155 1.2.2.2 skrll pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 156 1.2.2.2 skrll } 157 1.2.2.2 skrll } 158 1.2.2.2 skrll 159 1.2.2.2 skrll static void 160 1.2.2.4 skrll geodeide_setup_channel(struct ata_channel *chp) 161 1.2.2.2 skrll { 162 1.2.2.2 skrll struct ata_drive_datas *drvp; 163 1.2.2.4 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 164 1.2.2.4 skrll struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 165 1.2.2.2 skrll int channel = chp->ch_channel; 166 1.2.2.4 skrll int drive, s; 167 1.2.2.2 skrll u_int32_t dma_timing; 168 1.2.2.2 skrll u_int8_t idedma_ctl; 169 1.2.2.3 skrll const int32_t *geode_pio; 170 1.2.2.3 skrll const int32_t *geode_dma; 171 1.2.2.3 skrll const int32_t *geode_udma; 172 1.2.2.3 skrll bus_size_t dmaoff, piooff; 173 1.2.2.3 skrll 174 1.2.2.3 skrll switch (sc->sc_pp->ide_product) { 175 1.2.2.3 skrll case PCI_PRODUCT_CYRIX_CX5530_IDE: 176 1.2.2.3 skrll geode_pio = geode_cs5530_pio; 177 1.2.2.3 skrll geode_dma = geode_cs5530_dma; 178 1.2.2.3 skrll geode_udma = geode_cs5530_udma; 179 1.2.2.3 skrll break; 180 1.2.2.3 skrll 181 1.2.2.3 skrll case PCI_PRODUCT_NS_SC1100_IDE: 182 1.2.2.3 skrll default: /* XXX gcc */ 183 1.2.2.3 skrll geode_pio = geode_sc1100_pio; 184 1.2.2.3 skrll geode_dma = geode_sc1100_dma; 185 1.2.2.3 skrll geode_udma = geode_sc1100_udma; 186 1.2.2.3 skrll break; 187 1.2.2.3 skrll } 188 1.2.2.2 skrll 189 1.2.2.2 skrll /* setup DMA if needed */ 190 1.2.2.2 skrll pciide_channel_dma_setup(cp); 191 1.2.2.2 skrll 192 1.2.2.2 skrll idedma_ctl = 0; 193 1.2.2.2 skrll 194 1.2.2.2 skrll /* Per drive settings */ 195 1.2.2.2 skrll for (drive = 0; drive < 2; drive++) { 196 1.2.2.2 skrll drvp = &chp->ch_drive[drive]; 197 1.2.2.2 skrll /* If no drive, skip */ 198 1.2.2.2 skrll if ((drvp->drive_flags & DRIVE) == 0) 199 1.2.2.2 skrll continue; 200 1.2.2.3 skrll 201 1.2.2.3 skrll switch (sc->sc_pp->ide_product) { 202 1.2.2.3 skrll case PCI_PRODUCT_CYRIX_CX5530_IDE: 203 1.2.2.3 skrll dmaoff = CS5530_DMA_REG(channel, drive); 204 1.2.2.3 skrll piooff = CS5530_PIO_REG(channel, drive); 205 1.2.2.3 skrll dma_timing = CS5530_DMA_REG_PIO_FORMAT; 206 1.2.2.3 skrll break; 207 1.2.2.3 skrll 208 1.2.2.3 skrll case PCI_PRODUCT_NS_SC1100_IDE: 209 1.2.2.3 skrll default: /* XXX gcc */ 210 1.2.2.3 skrll dmaoff = SC1100_DMA_REG(channel, drive); 211 1.2.2.3 skrll piooff = SC1100_PIO_REG(channel, drive); 212 1.2.2.3 skrll dma_timing = 0; 213 1.2.2.3 skrll break; 214 1.2.2.3 skrll } 215 1.2.2.3 skrll 216 1.2.2.2 skrll /* add timing values, setup DMA if needed */ 217 1.2.2.2 skrll if (drvp->drive_flags & DRIVE_UDMA) { 218 1.2.2.2 skrll /* Use Ultra-DMA */ 219 1.2.2.2 skrll dma_timing |= geode_udma[drvp->UDMA_mode]; 220 1.2.2.2 skrll idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 221 1.2.2.2 skrll } else if (drvp->drive_flags & DRIVE_DMA) { 222 1.2.2.2 skrll /* use Multiword DMA */ 223 1.2.2.2 skrll dma_timing |= geode_dma[drvp->DMA_mode]; 224 1.2.2.2 skrll idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 225 1.2.2.2 skrll } else { 226 1.2.2.2 skrll /* PIO only */ 227 1.2.2.4 skrll s = splbio(); 228 1.2.2.2 skrll drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 229 1.2.2.4 skrll splx(s); 230 1.2.2.2 skrll } 231 1.2.2.3 skrll 232 1.2.2.3 skrll switch (sc->sc_pp->ide_product) { 233 1.2.2.3 skrll case PCI_PRODUCT_CYRIX_CX5530_IDE: 234 1.2.2.3 skrll bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 235 1.2.2.3 skrll dmaoff, dma_timing); 236 1.2.2.3 skrll bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 237 1.2.2.3 skrll piooff, geode_pio[drvp->PIO_mode]); 238 1.2.2.3 skrll break; 239 1.2.2.3 skrll 240 1.2.2.3 skrll case PCI_PRODUCT_NS_SC1100_IDE: 241 1.2.2.3 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, dmaoff, 242 1.2.2.3 skrll dma_timing); 243 1.2.2.3 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, piooff, 244 1.2.2.3 skrll geode_pio[drvp->PIO_mode]); 245 1.2.2.3 skrll break; 246 1.2.2.3 skrll } 247 1.2.2.2 skrll } 248 1.2.2.2 skrll 249 1.2.2.2 skrll if (idedma_ctl != 0) { 250 1.2.2.2 skrll /* Add software bits in status register */ 251 1.2.2.2 skrll bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 252 1.2.2.2 skrll idedma_ctl); 253 1.2.2.2 skrll } 254 1.2.2.2 skrll } 255
Indexes created Fri Oct 03 02:09:57 GMT 2025