geodeide.c revision 1.1.2.3.2.1
1 /* $NetBSD: geodeide.c,v 1.1.2.3.2.1 2005/07/18 03:57:33 riz Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for the IDE part of the AMD Geode CS5530A companion chip 35 * and AMD Geode SC1100. 36 * Docs available from AMD's web site 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: geodeide.c,v 1.1.2.3.2.1 2005/07/18 03:57:33 riz Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/pciidereg.h> 50 #include <dev/pci/pciidevar.h> 51 52 #include <dev/pci/pciide_geode_reg.h> 53 54 static void geodeide_chip_map(struct pciide_softc *, 55 struct pci_attach_args *); 56 static void geodeide_setup_channel(struct wdc_channel *); 57 static int geodeide_dma_init(void *, int, int, void *, size_t, int); 58 59 static int geodeide_match(struct device *, struct cfdata *, void *); 60 static void geodeide_attach(struct device *, struct device *, void *); 61 62 CFATTACH_DECL(geodeide, sizeof(struct pciide_softc), 63 geodeide_match, geodeide_attach, NULL, NULL); 64 65 static const struct pciide_product_desc pciide_geode_products[] = { 66 { PCI_PRODUCT_CYRIX_CX5530_IDE, 67 0, 68 "AMD Geode CX5530 IDE controller", 69 geodeide_chip_map, 70 }, 71 { PCI_PRODUCT_NS_SC1100_IDE, 72 0, 73 "AMD Geode SC1100 IDE controller", 74 geodeide_chip_map, 75 }, 76 { 0, 77 0, 78 NULL, 79 NULL, 80 }, 81 }; 82 83 static int 84 geodeide_match(struct device *parent, struct cfdata *match, void *aux) 85 { 86 struct pci_attach_args *pa = aux; 87 88 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYRIX || 89 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS) && 90 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 91 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 92 pciide_lookup_product(pa->pa_id, pciide_geode_products)) 93 return(2); 94 return (0); 95 } 96 97 static void 98 geodeide_attach(struct device *parent, struct device *self, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 struct pciide_softc *sc = (void *)self; 102 103 pciide_common_attach(sc, pa, 104 pciide_lookup_product(pa->pa_id, pciide_geode_products)); 105 } 106 107 static void 108 geodeide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 109 { 110 struct pciide_channel *cp; 111 int channel; 112 bus_size_t cmdsize, ctlsize; 113 114 if (pciide_chipen(sc, pa) == 0) 115 return; 116 117 aprint_normal("%s: bus-master DMA support present", 118 sc->sc_wdcdev.sc_dev.dv_xname); 119 pciide_mapreg_dma(sc, pa); 120 aprint_normal("\n"); 121 if (sc->sc_dma_ok) { 122 sc->sc_wdcdev.cap = WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA | 123 WDC_CAPABILITY_IRQACK; 124 sc->sc_wdcdev.irqack = pciide_irqack; 125 /* 126 * XXXJRT What chip revisions actually need the DMA 127 * alignment work-around? 128 */ 129 sc->sc_wdcdev.dma_init = geodeide_dma_init; 130 } 131 sc->sc_wdcdev.PIO_cap = 4; 132 sc->sc_wdcdev.DMA_cap = 2; 133 sc->sc_wdcdev.UDMA_cap = 2; 134 sc->sc_wdcdev.set_modes = geodeide_setup_channel; 135 sc->sc_wdcdev.channels = sc->wdc_chanarray; 136 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 137 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 138 WDC_CAPABILITY_MODE; 139 140 /* 141 * Soekris Engineering Issue #0003: 142 * "The SC1100 built in busmaster IDE controller is pretty 143 * standard, but have two bugs: data transfers need to be 144 * dword aligned and it cannot do an exact 64Kbyte data 145 * transfer." 146 */ 147 if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SC1100_IDE) { 148 if (sc->sc_dma_boundary == 0x10000) 149 sc->sc_dma_boundary -= PAGE_SIZE; 150 151 if (sc->sc_dma_maxsegsz == 0x10000) 152 sc->sc_dma_maxsegsz -= PAGE_SIZE; 153 } 154 155 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 156 cp = &sc->pciide_channels[channel]; 157 /* controller is compat-only */ 158 if (pciide_chansetup(sc, channel, 0) == 0) 159 continue; 160 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 161 } 162 } 163 164 static void 165 geodeide_setup_channel(struct wdc_channel *chp) 166 { 167 struct ata_drive_datas *drvp; 168 struct pciide_channel *cp = (struct pciide_channel*)chp; 169 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 170 int channel = chp->ch_channel; 171 int drive; 172 u_int32_t dma_timing; 173 u_int8_t idedma_ctl; 174 const int32_t *geode_pio; 175 const int32_t *geode_dma; 176 const int32_t *geode_udma; 177 bus_size_t dmaoff, piooff; 178 179 switch (sc->sc_pp->ide_product) { 180 case PCI_PRODUCT_CYRIX_CX5530_IDE: 181 geode_pio = geode_cs5530_pio; 182 geode_dma = geode_cs5530_dma; 183 geode_udma = geode_cs5530_udma; 184 break; 185 186 case PCI_PRODUCT_NS_SC1100_IDE: 187 default: /* XXX gcc */ 188 geode_pio = geode_sc1100_pio; 189 geode_dma = geode_sc1100_dma; 190 geode_udma = geode_sc1100_udma; 191 break; 192 } 193 194 /* setup DMA if needed */ 195 pciide_channel_dma_setup(cp); 196 197 idedma_ctl = 0; 198 199 /* Per drive settings */ 200 for (drive = 0; drive < 2; drive++) { 201 drvp = &chp->ch_drive[drive]; 202 /* If no drive, skip */ 203 if ((drvp->drive_flags & DRIVE) == 0) 204 continue; 205 206 switch (sc->sc_pp->ide_product) { 207 case PCI_PRODUCT_CYRIX_CX5530_IDE: 208 dmaoff = CS5530_DMA_REG(channel, drive); 209 piooff = CS5530_PIO_REG(channel, drive); 210 dma_timing = CS5530_DMA_REG_PIO_FORMAT; 211 break; 212 213 case PCI_PRODUCT_NS_SC1100_IDE: 214 default: /* XXX gcc */ 215 dmaoff = SC1100_DMA_REG(channel, drive); 216 piooff = SC1100_PIO_REG(channel, drive); 217 dma_timing = 0; 218 break; 219 } 220 221 /* add timing values, setup DMA if needed */ 222 if (drvp->drive_flags & DRIVE_UDMA) { 223 /* Use Ultra-DMA */ 224 dma_timing |= geode_udma[drvp->UDMA_mode]; 225 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 226 } else if (drvp->drive_flags & DRIVE_DMA) { 227 /* use Multiword DMA */ 228 dma_timing |= geode_dma[drvp->DMA_mode]; 229 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 230 } else { 231 /* PIO only */ 232 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 233 } 234 235 switch (sc->sc_pp->ide_product) { 236 case PCI_PRODUCT_CYRIX_CX5530_IDE: 237 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 238 dmaoff, dma_timing); 239 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 240 piooff, geode_pio[drvp->PIO_mode]); 241 break; 242 243 case PCI_PRODUCT_NS_SC1100_IDE: 244 pci_conf_write(sc->sc_pc, sc->sc_tag, dmaoff, 245 dma_timing); 246 pci_conf_write(sc->sc_pc, sc->sc_tag, piooff, 247 geode_pio[drvp->PIO_mode]); 248 break; 249 } 250 } 251 252 if (idedma_ctl != 0) { 253 /* Add software bits in status register */ 254 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 255 idedma_ctl); 256 } 257 } 258 259 static int 260 geodeide_dma_init(void *v, int channel, int drive, void *databuf, 261 size_t datalen, int flags) 262 { 263 264 /* 265 * If the buffer is not properly aligned, we can't allow DMA 266 * and need to fall back to PIO. 267 */ 268 if (((uintptr_t)databuf) & 0xf) 269 return (EINVAL); 270 271 return (pciide_dma_init(v, channel, drive, databuf, datalen, flags)); 272 } 273
Indexes created Thu Oct 02 14:10:14 GMT 2025