geodeide.c revision 1.10
1 /* $NetBSD: geodeide.c,v 1.10 2005/07/06 01:46:52 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for the IDE part of the AMD Geode CS5530A companion chip 35 * and AMD Geode SC1100. 36 * Docs available from AMD's web site 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: geodeide.c,v 1.10 2005/07/06 01:46:52 thorpej Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcidevs.h> 49 #include <dev/pci/pciidereg.h> 50 #include <dev/pci/pciidevar.h> 51 52 #include <dev/pci/pciide_geode_reg.h> 53 54 static void geodeide_chip_map(struct pciide_softc *, 55 struct pci_attach_args *); 56 static void geodeide_setup_channel(struct ata_channel *); 57 static int geodeide_dma_init(void *, int, int, void *, size_t, int); 58 59 static int geodeide_match(struct device *, struct cfdata *, void *); 60 static void geodeide_attach(struct device *, struct device *, void *); 61 62 CFATTACH_DECL(geodeide, sizeof(struct pciide_softc), 63 geodeide_match, geodeide_attach, NULL, NULL); 64 65 static const struct pciide_product_desc pciide_geode_products[] = { 66 { PCI_PRODUCT_CYRIX_CX5530_IDE, 67 0, 68 "AMD Geode CX5530 IDE controller", 69 geodeide_chip_map, 70 }, 71 { PCI_PRODUCT_NS_SC1100_IDE, 72 0, 73 "AMD Geode SC1100 IDE controller", 74 geodeide_chip_map, 75 }, 76 { 0, 77 0, 78 NULL, 79 NULL, 80 }, 81 }; 82 83 static int 84 geodeide_match(struct device *parent, struct cfdata *match, void *aux) 85 { 86 struct pci_attach_args *pa = aux; 87 88 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYRIX || 89 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS) && 90 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 91 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 92 pciide_lookup_product(pa->pa_id, pciide_geode_products)) 93 return(2); 94 return (0); 95 } 96 97 static void 98 geodeide_attach(struct device *parent, struct device *self, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 struct pciide_softc *sc = (void *)self; 102 103 pciide_common_attach(sc, pa, 104 pciide_lookup_product(pa->pa_id, pciide_geode_products)); 105 } 106 107 static void 108 geodeide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 109 { 110 struct pciide_channel *cp; 111 int channel; 112 bus_size_t cmdsize, ctlsize; 113 114 if (pciide_chipen(sc, pa) == 0) 115 return; 116 117 aprint_normal("%s: bus-master DMA support present", 118 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 119 pciide_mapreg_dma(sc, pa); 120 aprint_normal("\n"); 121 if (sc->sc_dma_ok) { 122 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 123 sc->sc_wdcdev.irqack = pciide_irqack; 124 /* 125 * XXXJRT What chip revisions actually need the DMA 126 * alignment work-around? 127 */ 128 sc->sc_wdcdev.dma_init = geodeide_dma_init; 129 } 130 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 131 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 132 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 133 /* 134 * The 5530 is utterly swamped by UDMA mode 2, so limit to mode 1 135 * so that the chip is able to perform the other functions it has 136 * while IDE UDMA is going on. 137 */ 138 if (sc->sc_pp->ide_product == PCI_PRODUCT_CYRIX_CX5530_IDE) { 139 sc->sc_wdcdev.sc_atac.atac_udma_cap = 1; 140 } 141 sc->sc_wdcdev.sc_atac.atac_set_modes = geodeide_setup_channel; 142 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 143 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 144 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 145 146 /* 147 * Soekris Engineering Issue #0003: 148 * "The SC1100 built in busmaster IDE controller is pretty 149 * standard, but have two bugs: data transfers need to be 150 * dword aligned and it cannot do an exact 64Kbyte data 151 * transfer." 152 */ 153 if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SC1100_IDE) { 154 if (sc->sc_dma_boundary == 0x10000) 155 sc->sc_dma_boundary -= PAGE_SIZE; 156 157 if (sc->sc_dma_maxsegsz == 0x10000) 158 sc->sc_dma_maxsegsz -= PAGE_SIZE; 159 } 160 161 wdc_allocate_regs(&sc->sc_wdcdev); 162 163 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 164 channel++) { 165 cp = &sc->pciide_channels[channel]; 166 /* controller is compat-only */ 167 if (pciide_chansetup(sc, channel, 0) == 0) 168 continue; 169 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 170 } 171 } 172 173 static void 174 geodeide_setup_channel(struct ata_channel *chp) 175 { 176 struct ata_drive_datas *drvp; 177 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 178 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 179 int channel = chp->ch_channel; 180 int drive, s; 181 u_int32_t dma_timing; 182 u_int8_t idedma_ctl; 183 const int32_t *geode_pio; 184 const int32_t *geode_dma; 185 const int32_t *geode_udma; 186 bus_size_t dmaoff, piooff; 187 188 switch (sc->sc_pp->ide_product) { 189 case PCI_PRODUCT_CYRIX_CX5530_IDE: 190 geode_pio = geode_cs5530_pio; 191 geode_dma = geode_cs5530_dma; 192 geode_udma = geode_cs5530_udma; 193 break; 194 195 case PCI_PRODUCT_NS_SC1100_IDE: 196 default: /* XXX gcc */ 197 geode_pio = geode_sc1100_pio; 198 geode_dma = geode_sc1100_dma; 199 geode_udma = geode_sc1100_udma; 200 break; 201 } 202 203 /* setup DMA if needed */ 204 pciide_channel_dma_setup(cp); 205 206 idedma_ctl = 0; 207 208 /* Per drive settings */ 209 for (drive = 0; drive < 2; drive++) { 210 drvp = &chp->ch_drive[drive]; 211 /* If no drive, skip */ 212 if ((drvp->drive_flags & DRIVE) == 0) 213 continue; 214 215 switch (sc->sc_pp->ide_product) { 216 case PCI_PRODUCT_CYRIX_CX5530_IDE: 217 dmaoff = CS5530_DMA_REG(channel, drive); 218 piooff = CS5530_PIO_REG(channel, drive); 219 dma_timing = CS5530_DMA_REG_PIO_FORMAT; 220 break; 221 222 case PCI_PRODUCT_NS_SC1100_IDE: 223 default: /* XXX gcc */ 224 dmaoff = SC1100_DMA_REG(channel, drive); 225 piooff = SC1100_PIO_REG(channel, drive); 226 dma_timing = 0; 227 break; 228 } 229 230 /* add timing values, setup DMA if needed */ 231 if (drvp->drive_flags & DRIVE_UDMA) { 232 /* Use Ultra-DMA */ 233 dma_timing |= geode_udma[drvp->UDMA_mode]; 234 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 235 } else if (drvp->drive_flags & DRIVE_DMA) { 236 /* use Multiword DMA */ 237 dma_timing |= geode_dma[drvp->DMA_mode]; 238 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 239 } else { 240 /* PIO only */ 241 s = splbio(); 242 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 243 splx(s); 244 } 245 246 switch (sc->sc_pp->ide_product) { 247 case PCI_PRODUCT_CYRIX_CX5530_IDE: 248 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 249 dmaoff, dma_timing); 250 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 251 piooff, geode_pio[drvp->PIO_mode]); 252 break; 253 254 case PCI_PRODUCT_NS_SC1100_IDE: 255 pci_conf_write(sc->sc_pc, sc->sc_tag, dmaoff, 256 dma_timing); 257 pci_conf_write(sc->sc_pc, sc->sc_tag, piooff, 258 geode_pio[drvp->PIO_mode]); 259 break; 260 } 261 } 262 263 if (idedma_ctl != 0) { 264 /* Add software bits in status register */ 265 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 266 idedma_ctl); 267 } 268 } 269 270 static int 271 geodeide_dma_init(void *v, int channel, int drive, void *databuf, 272 size_t datalen, int flags) 273 { 274 275 /* 276 * If the buffer is not properly aligned, we can't allow DMA 277 * and need to fall back to PIO. 278 */ 279 if (((uintptr_t)databuf) & 0xf) 280 return (EINVAL); 281 282 return (pciide_dma_init(v, channel, drive, databuf, datalen, flags)); 283 } 284
Indexes created Thu Sep 25 02:09:54 GMT 2025