geodeide.c revision 1.17
1 /* $NetBSD: geodeide.c,v 1.17 2010/11/05 18:07:24 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 /* 29 * Driver for the IDE part of the AMD Geode CS5530A companion chip 30 * and AMD Geode SC1100. 31 * Docs available from AMD's web site 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: geodeide.c,v 1.17 2010/11/05 18:07:24 jakllsch Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/pciidereg.h> 45 #include <dev/pci/pciidevar.h> 46 47 #include <dev/pci/pciide_geode_reg.h> 48 49 static void geodeide_chip_map(struct pciide_softc *, 50 struct pci_attach_args *); 51 static void geodeide_setup_channel(struct ata_channel *); 52 static int geodeide_dma_init(void *, int, int, void *, size_t, int); 53 54 static int geodeide_match(device_t, cfdata_t, void *); 55 static void geodeide_attach(device_t, device_t, void *); 56 57 CFATTACH_DECL_NEW(geodeide, sizeof(struct pciide_softc), 58 geodeide_match, geodeide_attach, NULL, NULL); 59 60 static const struct pciide_product_desc pciide_geode_products[] = { 61 { PCI_PRODUCT_CYRIX_CX5530_IDE, 62 0, 63 "AMD Geode CX5530 IDE controller", 64 geodeide_chip_map, 65 }, 66 { PCI_PRODUCT_NS_SC1100_IDE, 67 0, 68 "AMD Geode SC1100 IDE controller", 69 geodeide_chip_map, 70 }, 71 { 0, 72 0, 73 NULL, 74 NULL, 75 }, 76 }; 77 78 static int 79 geodeide_match(device_t parent, cfdata_t match, void *aux) 80 { 81 struct pci_attach_args *pa = aux; 82 83 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYRIX || 84 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS) && 85 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 86 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 87 pciide_lookup_product(pa->pa_id, pciide_geode_products)) 88 return(2); 89 return (0); 90 } 91 92 static void 93 geodeide_attach(device_t parent, device_t self, void *aux) 94 { 95 struct pci_attach_args *pa = aux; 96 struct pciide_softc *sc = device_private(self); 97 98 sc->sc_wdcdev.sc_atac.atac_dev = self; 99 100 pciide_common_attach(sc, pa, 101 pciide_lookup_product(pa->pa_id, pciide_geode_products)); 102 } 103 104 static void 105 geodeide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 106 { 107 struct pciide_channel *cp; 108 int channel; 109 110 if (pciide_chipen(sc, pa) == 0) 111 return; 112 113 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 114 "bus-master DMA support present"); 115 pciide_mapreg_dma(sc, pa); 116 aprint_verbose("\n"); 117 if (sc->sc_dma_ok) { 118 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 119 sc->sc_wdcdev.irqack = pciide_irqack; 120 /* 121 * XXXJRT What chip revisions actually need the DMA 122 * alignment work-around? 123 */ 124 sc->sc_wdcdev.dma_init = geodeide_dma_init; 125 } 126 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 127 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 128 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 129 /* 130 * The 5530 is utterly swamped by UDMA mode 2, so limit to mode 1 131 * so that the chip is able to perform the other functions it has 132 * while IDE UDMA is going on. 133 */ 134 if (sc->sc_pp->ide_product == PCI_PRODUCT_CYRIX_CX5530_IDE) { 135 sc->sc_wdcdev.sc_atac.atac_udma_cap = 1; 136 } 137 sc->sc_wdcdev.sc_atac.atac_set_modes = geodeide_setup_channel; 138 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 139 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 140 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 141 142 /* 143 * Soekris Engineering Issue #0003: 144 * "The SC1100 built in busmaster IDE controller is pretty 145 * standard, but have two bugs: data transfers need to be 146 * dword aligned and it cannot do an exact 64Kbyte data 147 * transfer." 148 */ 149 if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SC1100_IDE) { 150 if (sc->sc_dma_boundary == 0x10000) 151 sc->sc_dma_boundary -= PAGE_SIZE; 152 153 if (sc->sc_dma_maxsegsz == 0x10000) 154 sc->sc_dma_maxsegsz -= PAGE_SIZE; 155 } 156 157 wdc_allocate_regs(&sc->sc_wdcdev); 158 159 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 160 channel++) { 161 cp = &sc->pciide_channels[channel]; 162 /* controller is compat-only */ 163 if (pciide_chansetup(sc, channel, 0) == 0) 164 continue; 165 pciide_mapchan(pa, cp, 0, pciide_pci_intr); 166 } 167 } 168 169 static void 170 geodeide_setup_channel(struct ata_channel *chp) 171 { 172 struct ata_drive_datas *drvp; 173 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 174 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 175 int channel = chp->ch_channel; 176 int drive, s; 177 u_int32_t dma_timing; 178 u_int8_t idedma_ctl; 179 const int32_t *geode_pio; 180 const int32_t *geode_dma; 181 const int32_t *geode_udma; 182 bus_size_t dmaoff, piooff; 183 184 switch (sc->sc_pp->ide_product) { 185 case PCI_PRODUCT_CYRIX_CX5530_IDE: 186 geode_pio = geode_cs5530_pio; 187 geode_dma = geode_cs5530_dma; 188 geode_udma = geode_cs5530_udma; 189 break; 190 191 case PCI_PRODUCT_NS_SC1100_IDE: 192 default: /* XXX gcc */ 193 geode_pio = geode_sc1100_pio; 194 geode_dma = geode_sc1100_dma; 195 geode_udma = geode_sc1100_udma; 196 break; 197 } 198 199 /* setup DMA if needed */ 200 pciide_channel_dma_setup(cp); 201 202 idedma_ctl = 0; 203 204 /* Per drive settings */ 205 for (drive = 0; drive < 2; drive++) { 206 drvp = &chp->ch_drive[drive]; 207 /* If no drive, skip */ 208 if ((drvp->drive_flags & DRIVE) == 0) 209 continue; 210 211 switch (sc->sc_pp->ide_product) { 212 case PCI_PRODUCT_CYRIX_CX5530_IDE: 213 dmaoff = CS5530_DMA_REG(channel, drive); 214 piooff = CS5530_PIO_REG(channel, drive); 215 dma_timing = CS5530_DMA_REG_PIO_FORMAT; 216 break; 217 218 case PCI_PRODUCT_NS_SC1100_IDE: 219 default: /* XXX gcc */ 220 dmaoff = SC1100_DMA_REG(channel, drive); 221 piooff = SC1100_PIO_REG(channel, drive); 222 dma_timing = 0; 223 break; 224 } 225 226 /* add timing values, setup DMA if needed */ 227 if (drvp->drive_flags & DRIVE_UDMA) { 228 /* Use Ultra-DMA */ 229 dma_timing |= geode_udma[drvp->UDMA_mode]; 230 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 231 } else if (drvp->drive_flags & DRIVE_DMA) { 232 /* use Multiword DMA */ 233 dma_timing |= geode_dma[drvp->DMA_mode]; 234 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 235 } else { 236 /* PIO only */ 237 s = splbio(); 238 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 239 splx(s); 240 } 241 242 switch (sc->sc_pp->ide_product) { 243 case PCI_PRODUCT_CYRIX_CX5530_IDE: 244 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 245 dmaoff, dma_timing); 246 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 247 piooff, geode_pio[drvp->PIO_mode]); 248 break; 249 250 case PCI_PRODUCT_NS_SC1100_IDE: 251 pci_conf_write(sc->sc_pc, sc->sc_tag, dmaoff, 252 dma_timing); 253 pci_conf_write(sc->sc_pc, sc->sc_tag, piooff, 254 geode_pio[drvp->PIO_mode]); 255 break; 256 } 257 } 258 259 if (idedma_ctl != 0) { 260 /* Add software bits in status register */ 261 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 262 idedma_ctl); 263 } 264 } 265 266 static int 267 geodeide_dma_init(void *v, int channel, int drive, void *databuf, 268 size_t datalen, int flags) 269 { 270 271 /* 272 * If the buffer is not properly aligned, we can't allow DMA 273 * and need to fall back to PIO. 274 */ 275 if (((uintptr_t)databuf) & 0xf) 276 return (EINVAL); 277 278 return (pciide_dma_init(v, channel, drive, databuf, datalen, flags)); 279 } 280
Indexes created Thu Sep 25 02:09:54 GMT 2025