geodeide.c revision 1.24.2.2
1 /* $NetBSD: geodeide.c,v 1.24.2.2 2014/08/20 00:03:42 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 /* 29 * Driver for the IDE part of the AMD Geode CS5530A companion chip 30 * and AMD Geode SC1100. 31 * Docs available from AMD's web site 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: geodeide.c,v 1.24.2.2 2014/08/20 00:03:42 tls Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <dev/pci/pcidevs.h> 42 #include <dev/pci/pciidereg.h> 43 #include <dev/pci/pciidevar.h> 44 45 #include <dev/pci/pciide_geode_reg.h> 46 47 static void geodeide_chip_map(struct pciide_softc *, 48 const struct pci_attach_args *); 49 static void geodeide_setup_channel(struct ata_channel *); 50 static int geodeide_dma_init(void *, int, int, void *, size_t, int); 51 52 static int geodeide_match(device_t, cfdata_t, void *); 53 static void geodeide_attach(device_t, device_t, void *); 54 55 CFATTACH_DECL_NEW(geodeide, sizeof(struct pciide_softc), 56 geodeide_match, geodeide_attach, pciide_detach, NULL); 57 58 static const struct pciide_product_desc pciide_geode_products[] = { 59 { PCI_PRODUCT_CYRIX_CX5530_IDE, 60 0, 61 "AMD Geode CX5530 IDE controller", 62 geodeide_chip_map, 63 }, 64 { PCI_PRODUCT_NS_SC1100_IDE, 65 0, 66 "AMD Geode SC1100 IDE controller", 67 geodeide_chip_map, 68 }, 69 { 0, 70 0, 71 NULL, 72 NULL, 73 }, 74 }; 75 76 static int 77 geodeide_match(device_t parent, cfdata_t match, void *aux) 78 { 79 struct pci_attach_args *pa = aux; 80 81 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYRIX || 82 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS) && 83 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 84 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 85 pciide_lookup_product(pa->pa_id, pciide_geode_products)) 86 return(2); 87 return (0); 88 } 89 90 static void 91 geodeide_attach(device_t parent, device_t self, void *aux) 92 { 93 struct pci_attach_args *pa = aux; 94 struct pciide_softc *sc = device_private(self); 95 96 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 97 98 sc->sc_wdcdev.sc_atac.atac_dev = self; 99 100 pciide_common_attach(sc, pa, 101 pciide_lookup_product(pa->pa_id, pciide_geode_products)); 102 } 103 104 static void 105 geodeide_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 106 { 107 struct pciide_channel *cp; 108 int channel; 109 110 if (pciide_chipen(sc, pa) == 0) 111 return; 112 113 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 114 "bus-master DMA support present"); 115 pciide_mapreg_dma(sc, pa); 116 aprint_verbose("\n"); 117 if (sc->sc_dma_ok) { 118 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 119 sc->sc_wdcdev.irqack = pciide_irqack; 120 /* 121 * XXXJRT What chip revisions actually need the DMA 122 * alignment work-around? 123 */ 124 sc->sc_wdcdev.dma_init = geodeide_dma_init; 125 } 126 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 127 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 128 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 129 /* 130 * The 5530 is utterly swamped by UDMA mode 2, so limit to mode 1 131 * so that the chip is able to perform the other functions it has 132 * while IDE UDMA is going on. 133 */ 134 if (sc->sc_pp->ide_product == PCI_PRODUCT_CYRIX_CX5530_IDE) { 135 sc->sc_wdcdev.sc_atac.atac_udma_cap = 1; 136 } 137 sc->sc_wdcdev.sc_atac.atac_set_modes = geodeide_setup_channel; 138 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 139 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 140 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 141 sc->sc_wdcdev.wdc_maxdrives = 2; 142 143 /* 144 * Soekris Engineering Issue #0003: 145 * "The SC1100 built in busmaster IDE controller is pretty 146 * standard, but have two bugs: data transfers need to be 147 * dword aligned and it cannot do an exact 64Kbyte data 148 * transfer." 149 */ 150 if (sc->sc_pp->ide_product == PCI_PRODUCT_NS_SC1100_IDE) { 151 if (sc->sc_dma_boundary == 0x10000) 152 sc->sc_dma_boundary -= PAGE_SIZE; 153 154 if (sc->sc_dma_maxsegsz == 0x10000) 155 sc->sc_dma_maxsegsz -= PAGE_SIZE; 156 } 157 158 wdc_allocate_regs(&sc->sc_wdcdev); 159 160 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 161 channel++) { 162 cp = &sc->pciide_channels[channel]; 163 /* controller is compat-only */ 164 if (pciide_chansetup(sc, channel, 0) == 0) 165 continue; 166 pciide_mapchan(pa, cp, 0, pciide_pci_intr); 167 } 168 } 169 170 static void 171 geodeide_setup_channel(struct ata_channel *chp) 172 { 173 struct ata_drive_datas *drvp; 174 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 175 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 176 int channel = chp->ch_channel; 177 int drive, s; 178 u_int32_t dma_timing; 179 u_int8_t idedma_ctl; 180 const int32_t *geode_pio; 181 const int32_t *geode_dma; 182 const int32_t *geode_udma; 183 bus_size_t dmaoff, piooff; 184 185 switch (sc->sc_pp->ide_product) { 186 case PCI_PRODUCT_CYRIX_CX5530_IDE: 187 geode_pio = geode_cs5530_pio; 188 geode_dma = geode_cs5530_dma; 189 geode_udma = geode_cs5530_udma; 190 break; 191 192 case PCI_PRODUCT_NS_SC1100_IDE: 193 default: /* XXX gcc */ 194 geode_pio = geode_sc1100_pio; 195 geode_dma = geode_sc1100_dma; 196 geode_udma = geode_sc1100_udma; 197 break; 198 } 199 200 /* setup DMA if needed */ 201 pciide_channel_dma_setup(cp); 202 203 idedma_ctl = 0; 204 205 /* Per drive settings */ 206 for (drive = 0; drive < 2; drive++) { 207 drvp = &chp->ch_drive[drive]; 208 /* If no drive, skip */ 209 if (drvp->drive_type == ATA_DRIVET_NONE) 210 continue; 211 212 switch (sc->sc_pp->ide_product) { 213 case PCI_PRODUCT_CYRIX_CX5530_IDE: 214 dmaoff = CS5530_DMA_REG(channel, drive); 215 piooff = CS5530_PIO_REG(channel, drive); 216 dma_timing = CS5530_DMA_REG_PIO_FORMAT; 217 break; 218 219 case PCI_PRODUCT_NS_SC1100_IDE: 220 default: /* XXX gcc */ 221 dmaoff = SC1100_DMA_REG(channel, drive); 222 piooff = SC1100_PIO_REG(channel, drive); 223 dma_timing = 0; 224 break; 225 } 226 227 /* add timing values, setup DMA if needed */ 228 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 229 /* Use Ultra-DMA */ 230 dma_timing |= geode_udma[drvp->UDMA_mode]; 231 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 232 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 233 /* use Multiword DMA */ 234 dma_timing |= geode_dma[drvp->DMA_mode]; 235 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 236 } else { 237 /* PIO only */ 238 s = splbio(); 239 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 240 splx(s); 241 } 242 243 switch (sc->sc_pp->ide_product) { 244 case PCI_PRODUCT_CYRIX_CX5530_IDE: 245 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 246 dmaoff, dma_timing); 247 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 248 piooff, geode_pio[drvp->PIO_mode]); 249 break; 250 251 case PCI_PRODUCT_NS_SC1100_IDE: 252 pci_conf_write(sc->sc_pc, sc->sc_tag, dmaoff, 253 dma_timing); 254 pci_conf_write(sc->sc_pc, sc->sc_tag, piooff, 255 geode_pio[drvp->PIO_mode]); 256 break; 257 } 258 } 259 260 if (idedma_ctl != 0) { 261 /* Add software bits in status register */ 262 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 263 idedma_ctl); 264 } 265 } 266 267 static int 268 geodeide_dma_init(void *v, int channel, int drive, void *databuf, 269 size_t datalen, int flags) 270 { 271 272 /* 273 * If the buffer is not properly aligned, we can't allow DMA 274 * and need to fall back to PIO. 275 */ 276 if (((uintptr_t)databuf) & 0xf) 277 return (EINVAL); 278 279 return (pciide_dma_init(v, channel, drive, databuf, datalen, flags)); 280 } 281
Indexes created Thu Oct 02 14:10:14 GMT 2025