gffb.c revision 1.12.14.1
1 /* $NetBSD: gffb.c,v 1.12.14.1 2019/06/10 22:07:15 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * A console driver for nvidia geforce graphics controllers 30 * tested on macppc only so far, should work on other hardware as long as 31 * something sets up a usable graphics mode and sets the right device properties 32 * This driver should work with all NV1x hardware but so far it's been tested 33 * only on NV11 / GeForce2 MX. Needs testing with more hardware and if 34 * successful, PCI IDs need to be added to gffb_match() 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: gffb.c,v 1.12.14.1 2019/06/10 22:07:15 christos Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 #include <sys/atomic.h> 48 49 #include <dev/videomode/videomode.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 #include <dev/pci/pciio.h> 55 #include <dev/pci/gffbreg.h> 56 57 #include <dev/wscons/wsdisplayvar.h> 58 #include <dev/wscons/wsconsio.h> 59 #include <dev/wsfont/wsfont.h> 60 #include <dev/rasops/rasops.h> 61 #include <dev/wscons/wsdisplay_vconsvar.h> 62 #include <dev/pci/wsdisplay_pci.h> 63 #include <dev/wscons/wsdisplay_glyphcachevar.h> 64 65 #include <dev/i2c/i2cvar.h> 66 67 #include "opt_gffb.h" 68 #include "opt_vcons.h" 69 70 #ifdef GFFB_DEBUG 71 #define DPRINTF printf 72 #else 73 #define DPRINTF while(0) printf 74 #endif 75 76 struct gffb_softc { 77 device_t sc_dev; 78 79 pci_chipset_tag_t sc_pc; 80 pcitag_t sc_pcitag; 81 82 bus_space_tag_t sc_memt; 83 bus_space_tag_t sc_iot; 84 85 bus_space_handle_t sc_regh, sc_fbh; 86 bus_addr_t sc_fb, sc_reg; 87 bus_size_t sc_fbsize, sc_regsize; 88 uint8_t *sc_fbaddr; 89 size_t sc_vramsize; 90 uint32_t sc_fboffset; 91 92 int sc_width, sc_height, sc_depth, sc_stride; 93 int sc_locked, sc_accel; 94 struct vcons_screen sc_console_screen; 95 struct wsscreen_descr sc_defaultscreen_descr; 96 const struct wsscreen_descr *sc_screens[1]; 97 struct wsscreen_list sc_screenlist; 98 struct vcons_data vd; 99 int sc_mode; 100 u_char sc_cmap_red[256]; 101 u_char sc_cmap_green[256]; 102 u_char sc_cmap_blue[256]; 103 int sc_put, sc_current, sc_free; 104 uint32_t sc_rop; 105 void (*sc_putchar)(void *, int, int, u_int, long); 106 kmutex_t sc_lock; 107 glyphcache sc_gc; 108 }; 109 110 static int gffb_match(device_t, cfdata_t, void *); 111 static void gffb_attach(device_t, device_t, void *); 112 113 CFATTACH_DECL_NEW(gffb, sizeof(struct gffb_softc), 114 gffb_match, gffb_attach, NULL, NULL); 115 116 static int gffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 117 static paddr_t gffb_mmap(void *, void *, off_t, int); 118 static void gffb_init_screen(void *, struct vcons_screen *, int, long *); 119 120 static int gffb_putcmap(struct gffb_softc *, struct wsdisplay_cmap *); 121 static int gffb_getcmap(struct gffb_softc *, struct wsdisplay_cmap *); 122 static void gffb_restore_palette(struct gffb_softc *); 123 static int gffb_putpalreg(struct gffb_softc *, uint8_t, uint8_t, 124 uint8_t, uint8_t); 125 126 static void gffb_init(struct gffb_softc *); 127 128 static void gffb_make_room(struct gffb_softc *, int); 129 static void gffb_sync(struct gffb_softc *); 130 131 static void gffb_rectfill(struct gffb_softc *, int, int, int, int, 132 uint32_t); 133 static void gffb_bitblt(void *, int, int, int, int, int, int, int); 134 static void gffb_rop(struct gffb_softc *, int); 135 136 static void gffb_cursor(void *, int, int, int); 137 static void gffb_putchar(void *, int, int, u_int, long); 138 static void gffb_copycols(void *, int, int, int, int); 139 static void gffb_erasecols(void *, int, int, int, long); 140 static void gffb_copyrows(void *, int, int, int); 141 static void gffb_eraserows(void *, int, int, long); 142 143 #define GFFB_READ_4(o) bus_space_read_4(sc->sc_memt, sc->sc_regh, (o)) 144 #define GFFB_WRITE_4(o, v) bus_space_write_4(sc->sc_memt, sc->sc_regh, (o), (v)) 145 146 struct wsdisplay_accessops gffb_accessops = { 147 gffb_ioctl, 148 gffb_mmap, 149 NULL, /* alloc_screen */ 150 NULL, /* free_screen */ 151 NULL, /* show_screen */ 152 NULL, /* load_font */ 153 NULL, /* pollc */ 154 NULL /* scroll */ 155 }; 156 157 static int 158 gffb_match(device_t parent, cfdata_t match, void *aux) 159 { 160 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 161 162 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 163 return 0; 164 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_NVIDIA) 165 return 0; 166 167 /* only card tested on so far - likely need a list */ 168 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GEFORCE2MX) 169 return 100; 170 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GEFORCE_6800U) 171 return 100; 172 return (0); 173 } 174 175 static void 176 gffb_attach(device_t parent, device_t self, void *aux) 177 { 178 struct gffb_softc *sc = device_private(self); 179 struct pci_attach_args *pa = aux; 180 struct rasops_info *ri; 181 bus_space_tag_t tag; 182 struct wsemuldisplaydev_attach_args aa; 183 prop_dictionary_t dict; 184 unsigned long defattr; 185 pcireg_t reg; 186 bool is_console = FALSE; 187 uint32_t addr; 188 int i, j, f; 189 uint8_t cmap[768]; 190 191 sc->sc_pc = pa->pa_pc; 192 sc->sc_pcitag = pa->pa_tag; 193 sc->sc_memt = pa->pa_memt; 194 sc->sc_iot = pa->pa_iot; 195 sc->sc_dev = self; 196 197 /* first, see what kind of chip we've got */ 198 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_ID_REG); 199 sc->sc_accel = PCI_PRODUCT(reg) == PCI_PRODUCT_NVIDIA_GEFORCE2MX; 200 201 pci_aprint_devinfo(pa, NULL); 202 203 /* fill in parameters from properties */ 204 dict = device_properties(self); 205 if (!prop_dictionary_get_uint32(dict, "width", &sc->sc_width)) { 206 aprint_error("%s: no width property\n", device_xname(self)); 207 return; 208 } 209 if (!prop_dictionary_get_uint32(dict, "height", &sc->sc_height)) { 210 aprint_error("%s: no height property\n", device_xname(self)); 211 return; 212 } 213 214 #ifdef GLYPHCACHE_DEBUG 215 /* leave some visible VRAM unused so we can see the glyph cache */ 216 sc->sc_height -= 300; 217 #endif 218 219 if (!prop_dictionary_get_uint32(dict, "depth", &sc->sc_depth)) { 220 aprint_error("%s: no depth property\n", device_xname(self)); 221 return; 222 } 223 if (!prop_dictionary_get_uint32(dict, "linebytes", &sc->sc_stride)) { 224 aprint_error("%s: no linebytes property\n", 225 device_xname(self)); 226 return; 227 } 228 229 /* 230 * on !2MX we need to use the firmware's offset - for some reason 231 * register writes to anything other than the DACs go wrong 232 */ 233 sc->sc_fboffset = 0; 234 if (prop_dictionary_get_uint32(dict, "address", &addr)) { 235 sc->sc_fboffset = addr & 0x000fffff; /* XXX */ 236 } 237 238 prop_dictionary_get_bool(dict, "is_console", &is_console); 239 240 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_MEM, 0, 241 &tag, &sc->sc_regh, &sc->sc_reg, &sc->sc_regsize)) { 242 aprint_error("%s: failed to map registers.\n", 243 device_xname(sc->sc_dev)); 244 } 245 sc->sc_vramsize = GFFB_READ_4(GFFB_VRAM) & 0xfff00000; 246 247 /* don't map more VRAM than we actually have */ 248 if (pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, 249 0x14, PCI_MAPREG_TYPE_MEM, &sc->sc_fb, &sc->sc_fbsize, &f)) { 250 aprint_error("%s: can't find the framebuffer?!\n", 251 device_xname(sc->sc_dev)); 252 } 253 if (sc->sc_vramsize == 0) sc->sc_vramsize = sc->sc_fbsize; 254 255 /* don't map (much) more than we actually need */ 256 if (bus_space_map(sc->sc_memt, sc->sc_fb, 0x1000000, 257 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, 258 &sc->sc_fbh)) { 259 aprint_error("%s: failed to map the framebuffer.\n", 260 device_xname(sc->sc_dev)); 261 } 262 sc->sc_fbaddr = bus_space_vaddr(tag, sc->sc_fbh); 263 264 aprint_normal("%s: %d MB aperture at 0x%08x\n", device_xname(self), 265 (int)(sc->sc_fbsize >> 20), (uint32_t)sc->sc_fb); 266 aprint_normal_dev(sc->sc_dev, "%d MB video memory\n", 267 (int)(sc->sc_vramsize >> 20)); 268 269 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 270 "default", 271 0, 0, 272 NULL, 273 8, 16, 274 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 275 NULL 276 }; 277 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 278 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 279 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 280 sc->sc_locked = 0; 281 282 #ifdef GFFB_DEBUG 283 printf("put: %08x\n", GFFB_READ_4(GFFB_FIFO_PUT)); 284 printf("get: %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 285 #endif 286 287 /* 288 * we don't have hardware synchronization so we need a lock to serialize 289 * access to the DMA buffer between normal and kernel output 290 * actually it might be enough to use atomic ops on sc_current, sc_free 291 * etc. but for now we'll play it safe 292 * XXX we will probably deadlock if we take an interrupt while sc_lock 293 * is held and then try to printf() 294 */ 295 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 296 297 /* init engine here */ 298 gffb_init(sc); 299 300 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 301 &gffb_accessops); 302 sc->vd.init_screen = gffb_init_screen; 303 304 305 ri = &sc->sc_console_screen.scr_ri; 306 307 if (sc->sc_accel) { 308 sc->sc_gc.gc_bitblt = gffb_bitblt; 309 sc->sc_gc.gc_blitcookie = sc; 310 sc->sc_gc.gc_rop = 0xcc; 311 } 312 313 if (is_console) { 314 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 315 &defattr); 316 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 317 318 if (sc->sc_accel) { 319 gffb_rectfill(sc, 0, 0, sc->sc_width, sc->sc_height, 320 ri->ri_devcmap[(defattr >> 16) & 0xf]); 321 } else { 322 memset(sc->sc_fbaddr + sc->sc_fboffset, 323 ri->ri_devcmap[(defattr >> 16) & 0xf], 324 sc->sc_stride * sc->sc_height); 325 } 326 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 327 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 328 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 329 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 330 331 if (sc->sc_accel) 332 glyphcache_init(&sc->sc_gc, sc->sc_height + 5, 333 (0x800000 / sc->sc_stride) - sc->sc_height - 5, 334 sc->sc_width, 335 ri->ri_font->fontwidth, 336 ri->ri_font->fontheight, 337 defattr); 338 339 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 340 defattr); 341 vcons_replay_msgbuf(&sc->sc_console_screen); 342 } else { 343 /* 344 * since we're not the console we can postpone the rest 345 * until someone actually allocates a screen for us 346 */ 347 if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 348 /* do some minimal setup to avoid weirdnesses later */ 349 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 350 &defattr); 351 } else 352 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 353 354 if (sc->sc_accel) 355 glyphcache_init(&sc->sc_gc, sc->sc_height + 5, 356 (0x800000 / sc->sc_stride) - sc->sc_height - 5, 357 sc->sc_width, 358 ri->ri_font->fontwidth, 359 ri->ri_font->fontheight, 360 defattr); 361 } 362 363 j = 0; 364 rasops_get_cmap(ri, cmap, sizeof(cmap)); 365 for (i = 0; i < 256; i++) { 366 sc->sc_cmap_red[i] = cmap[j]; 367 sc->sc_cmap_green[i] = cmap[j + 1]; 368 sc->sc_cmap_blue[i] = cmap[j + 2]; 369 gffb_putpalreg(sc, i, cmap[j], cmap[j + 1], cmap[j + 2]); 370 j += 3; 371 } 372 373 /* no suspend/resume support yet */ 374 if (!pmf_device_register(sc->sc_dev, NULL, NULL)) 375 aprint_error_dev(sc->sc_dev, 376 "couldn't establish power handler\n"); 377 378 aa.console = is_console; 379 aa.scrdata = &sc->sc_screenlist; 380 aa.accessops = &gffb_accessops; 381 aa.accesscookie = &sc->vd; 382 383 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 384 385 #ifdef GFFB_DEBUG 386 for (i = 0; i < 40; i++) { 387 for (j = 0; j < 40; j++) { 388 gffb_rectfill(sc, i * 20, j * 20, 20, 20, 389 (i + j ) & 1 ? 0xe0e0e0e0 : 0x03030303); 390 } 391 } 392 393 gffb_rectfill(sc, 0, 800, 1280, 224, 0x92929292); 394 gffb_bitblt(sc, 0, 10, 10, 810, 200, 20, 0xcc); 395 gffb_bitblt(sc, 0, 10, 10, 840, 300, 20, 0xcc); 396 gffb_bitblt(sc, 0, 10, 10, 870, 400, 20, 0xcc); 397 gffb_bitblt(sc, 0, 10, 10, 900, 500, 20, 0xcc); 398 gffb_bitblt(sc, 0, 10, 10, 930, 600, 20, 0xcc); 399 gffb_bitblt(sc, 0, 10, 610, 810, 200, 20, 0xcc); 400 gffb_bitblt(sc, 0, 10, 610, 840, 300, 20, 0xcc); 401 gffb_bitblt(sc, 0, 10, 610, 870, 400, 20, 0xcc); 402 gffb_bitblt(sc, 0, 10, 610, 900, 500, 20, 0xcc); 403 gffb_bitblt(sc, 0, 10, 610, 930, 600, 20, 0xcc); 404 gffb_sync(sc); 405 printf("put %x current %x\n", sc->sc_put, sc->sc_current); 406 #endif 407 } 408 409 static int 410 gffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 411 { 412 struct vcons_data *vd = v; 413 struct gffb_softc *sc = vd->cookie; 414 struct wsdisplay_fbinfo *wdf; 415 struct vcons_screen *ms = vd->active; 416 417 switch (cmd) { 418 case WSDISPLAYIO_GTYPE: 419 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 420 return 0; 421 422 /* PCI config read/write passthrough. */ 423 case PCI_IOC_CFGREAD: 424 case PCI_IOC_CFGWRITE: 425 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 426 cmd, data, flag, l); 427 428 case WSDISPLAYIO_GET_BUSID: 429 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 430 sc->sc_pcitag, data); 431 432 case WSDISPLAYIO_GINFO: 433 if (ms == NULL) 434 return ENODEV; 435 wdf = (void *)data; 436 wdf->height = ms->scr_ri.ri_height; 437 wdf->width = ms->scr_ri.ri_width; 438 wdf->depth = ms->scr_ri.ri_depth; 439 wdf->cmsize = 256; 440 return 0; 441 442 case WSDISPLAYIO_GETCMAP: 443 return gffb_getcmap(sc, 444 (struct wsdisplay_cmap *)data); 445 446 case WSDISPLAYIO_PUTCMAP: 447 return gffb_putcmap(sc, 448 (struct wsdisplay_cmap *)data); 449 450 case WSDISPLAYIO_LINEBYTES: 451 *(u_int *)data = sc->sc_stride; 452 return 0; 453 454 case WSDISPLAYIO_SMODE: { 455 int new_mode = *(int*)data; 456 if (new_mode != sc->sc_mode) { 457 sc->sc_mode = new_mode; 458 if(new_mode == WSDISPLAYIO_MODE_EMUL) { 459 gffb_init(sc); 460 gffb_restore_palette(sc); 461 if (sc->sc_accel) { 462 glyphcache_wipe(&sc->sc_gc); 463 gffb_rectfill(sc, 0, 0, sc->sc_width, 464 sc->sc_height, ms->scr_ri.ri_devcmap[ 465 (ms->scr_defattr >> 16) & 0xf]); 466 } else { 467 memset(sc->sc_fbaddr + sc->sc_fboffset, 468 ms->scr_ri.ri_devcmap[ 469 (ms->scr_defattr >> 16) & 0xf], 470 sc->sc_stride * sc->sc_height); 471 } 472 vcons_redraw_screen(ms); 473 } 474 } 475 } 476 return 0; 477 478 case WSDISPLAYIO_GET_EDID: { 479 struct wsdisplayio_edid_info *d = data; 480 return wsdisplayio_get_edid(sc->sc_dev, d); 481 } 482 483 case WSDISPLAYIO_GET_FBINFO: { 484 struct wsdisplayio_fbinfo *fbi = data; 485 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 486 } 487 } 488 return EPASSTHROUGH; 489 } 490 491 static paddr_t 492 gffb_mmap(void *v, void *vs, off_t offset, int prot) 493 { 494 struct vcons_data *vd = v; 495 struct gffb_softc *sc = vd->cookie; 496 paddr_t pa; 497 498 /* 'regular' framebuffer mmap()ing */ 499 if (offset < sc->sc_vramsize) { 500 pa = bus_space_mmap(sc->sc_memt, sc->sc_fb + offset + 0x2000, 501 0, prot, BUS_SPACE_MAP_LINEAR); 502 return pa; 503 } 504 505 /* 506 * restrict all other mappings to processes with superuser privileges 507 * or the kernel itself 508 */ 509 if (kauth_authorize_machdep(kauth_cred_get(), 510 KAUTH_MACHDEP_UNMANAGEDMEM, 511 NULL, NULL, NULL, NULL) != 0) { 512 aprint_normal("%s: mmap() rejected.\n", 513 device_xname(sc->sc_dev)); 514 return -1; 515 } 516 517 if ((offset >= sc->sc_fb) && (offset < (sc->sc_fb + sc->sc_fbsize))) { 518 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 519 BUS_SPACE_MAP_LINEAR); 520 return pa; 521 } 522 523 if ((offset >= sc->sc_reg) && 524 (offset < (sc->sc_reg + sc->sc_regsize))) { 525 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 526 BUS_SPACE_MAP_LINEAR); 527 return pa; 528 } 529 530 #ifdef PCI_MAGIC_IO_RANGE 531 /* allow mapping of IO space */ 532 if ((offset >= PCI_MAGIC_IO_RANGE) && 533 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 534 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 535 0, prot, BUS_SPACE_MAP_LINEAR); 536 return pa; 537 } 538 #endif 539 540 return -1; 541 } 542 543 static void 544 gffb_init_screen(void *cookie, struct vcons_screen *scr, 545 int existing, long *defattr) 546 { 547 struct gffb_softc *sc = cookie; 548 struct rasops_info *ri = &scr->scr_ri; 549 550 ri->ri_depth = sc->sc_depth; 551 ri->ri_width = sc->sc_width; 552 ri->ri_height = sc->sc_height; 553 ri->ri_stride = sc->sc_stride; 554 if (sc->sc_depth == 8) 555 ri->ri_bits = sc->sc_fbaddr + sc->sc_fboffset; 556 ri->ri_flg = RI_CENTER; 557 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA; 558 559 rasops_init(ri, 0, 0); 560 ri->ri_caps = WSSCREEN_WSCOLORS; 561 562 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 563 sc->sc_width / ri->ri_font->fontwidth); 564 565 ri->ri_hw = scr; 566 567 if (sc->sc_accel) { 568 sc->sc_putchar = ri->ri_ops.putchar; 569 ri->ri_ops.copyrows = gffb_copyrows; 570 ri->ri_ops.copycols = gffb_copycols; 571 ri->ri_ops.eraserows = gffb_eraserows; 572 ri->ri_ops.erasecols = gffb_erasecols; 573 ri->ri_ops.cursor = gffb_cursor; 574 ri->ri_ops.putchar = gffb_putchar; 575 } else { 576 scr->scr_flags |= VCONS_DONT_READ; 577 } 578 } 579 580 static int 581 gffb_putcmap(struct gffb_softc *sc, struct wsdisplay_cmap *cm) 582 { 583 u_char *r, *g, *b; 584 u_int index = cm->index; 585 u_int count = cm->count; 586 int i, error; 587 u_char rbuf[256], gbuf[256], bbuf[256]; 588 589 #ifdef GFFB_DEBUG 590 aprint_debug("putcmap: %d %d\n",index, count); 591 #endif 592 if (cm->index >= 256 || cm->count > 256 || 593 (cm->index + cm->count) > 256) 594 return EINVAL; 595 error = copyin(cm->red, &rbuf[index], count); 596 if (error) 597 return error; 598 error = copyin(cm->green, &gbuf[index], count); 599 if (error) 600 return error; 601 error = copyin(cm->blue, &bbuf[index], count); 602 if (error) 603 return error; 604 605 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 606 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 607 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 608 609 r = &sc->sc_cmap_red[index]; 610 g = &sc->sc_cmap_green[index]; 611 b = &sc->sc_cmap_blue[index]; 612 613 for (i = 0; i < count; i++) { 614 gffb_putpalreg(sc, index, *r, *g, *b); 615 index++; 616 r++, g++, b++; 617 } 618 return 0; 619 } 620 621 static int 622 gffb_getcmap(struct gffb_softc *sc, struct wsdisplay_cmap *cm) 623 { 624 u_int index = cm->index; 625 u_int count = cm->count; 626 int error; 627 628 if (index >= 255 || count > 256 || index + count > 256) 629 return EINVAL; 630 631 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 632 if (error) 633 return error; 634 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 635 if (error) 636 return error; 637 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 638 if (error) 639 return error; 640 641 return 0; 642 } 643 644 static void 645 gffb_restore_palette(struct gffb_softc *sc) 646 { 647 int i; 648 649 for (i = 0; i < (1 << sc->sc_depth); i++) { 650 gffb_putpalreg(sc, i, sc->sc_cmap_red[i], 651 sc->sc_cmap_green[i], sc->sc_cmap_blue[i]); 652 } 653 } 654 655 static int 656 gffb_putpalreg(struct gffb_softc *sc, uint8_t idx, uint8_t r, uint8_t g, 657 uint8_t b) 658 { 659 /* port 0 */ 660 bus_space_write_1(sc->sc_memt, sc->sc_regh, 661 GFFB_PDIO0 + GFFB_PEL_IW, idx); 662 bus_space_write_1(sc->sc_memt, sc->sc_regh, 663 GFFB_PDIO0 + GFFB_PEL_D, r); 664 bus_space_write_1(sc->sc_memt, sc->sc_regh, 665 GFFB_PDIO0 + GFFB_PEL_D, g); 666 bus_space_write_1(sc->sc_memt, sc->sc_regh, 667 GFFB_PDIO0 + GFFB_PEL_D, b); 668 669 /* port 1 */ 670 bus_space_write_1(sc->sc_memt, sc->sc_regh, 671 GFFB_PDIO1 + GFFB_PEL_IW, idx); 672 bus_space_write_1(sc->sc_memt, sc->sc_regh, 673 GFFB_PDIO1 + GFFB_PEL_D, r); 674 bus_space_write_1(sc->sc_memt, sc->sc_regh, 675 GFFB_PDIO1 + GFFB_PEL_D, g); 676 bus_space_write_1(sc->sc_memt, sc->sc_regh, 677 GFFB_PDIO1 + GFFB_PEL_D, b); 678 679 return 0; 680 } 681 682 683 static void 684 gffb_dma_kickoff(struct gffb_softc *sc) 685 { 686 687 if (sc->sc_current != sc->sc_put) { 688 sc->sc_put = sc->sc_current; 689 membar_sync(); 690 (void)*sc->sc_fbaddr; 691 GFFB_WRITE_4(GFFB_FIFO_PUT, sc->sc_put); 692 membar_sync(); 693 } 694 } 695 696 static void 697 gffb_dmanext(struct gffb_softc *sc, uint32_t data) 698 { 699 bus_space_write_stream_4(sc->sc_memt, sc->sc_fbh, sc->sc_current, data); 700 sc->sc_current += 4; 701 } 702 703 static void 704 gffb_dmastart(struct gffb_softc *sc, uint32_t tag, int size) 705 { 706 if(sc->sc_free <= (size << 2)) 707 gffb_make_room(sc, size); 708 gffb_dmanext(sc, ((size) << 18) | (tag)); 709 sc->sc_free -= ((size + 1) << 2); 710 } 711 712 /* 713 * from xf86_video_nv/nv_xaa.c: 714 * There is a HW race condition with videoram command buffers. 715 * You can't jump to the location of your put offset. We write put 716 * at the jump offset + SKIPS dwords with noop padding in between 717 * to solve this problem 718 */ 719 720 #define SKIPS 8 721 722 static void 723 gffb_make_room(struct gffb_softc *sc, int size) 724 { 725 uint32_t get; 726 727 size = (size + 1) << 2; /* slots -> offset */ 728 729 while (sc->sc_free < size) { 730 get = GFFB_READ_4(GFFB_FIFO_GET); 731 732 if (sc->sc_put >= get) { 733 sc->sc_free = 0x2000 - sc->sc_current; 734 if (sc->sc_free < size) { 735 gffb_dmanext(sc, 0x20000000); 736 if(get <= (SKIPS << 2)) { 737 if (sc->sc_put <= (SKIPS << 2)) { 738 /* corner case - will be idle */ 739 GFFB_WRITE_4(GFFB_FIFO_PUT, 740 (SKIPS + 1) << 2); 741 } 742 do { 743 get =GFFB_READ_4(GFFB_FIFO_GET); 744 } while (get <= (SKIPS << 2)); 745 } 746 GFFB_WRITE_4(GFFB_FIFO_PUT, SKIPS << 2); 747 sc->sc_current = sc->sc_put = (SKIPS << 2); 748 sc->sc_free = get - ((SKIPS + 1) << 2); 749 } 750 } else 751 sc->sc_free = get - sc->sc_current - 4; 752 } 753 } 754 755 static void 756 gffb_sync(struct gffb_softc *sc) 757 { 758 int bail; 759 int i; 760 761 /* 762 * if there are commands in the buffer make sure the chip is actually 763 * trying to run them 764 */ 765 gffb_dma_kickoff(sc); 766 767 /* now wait for the command buffer to drain... */ 768 bail = 100000000; 769 while ((GFFB_READ_4(GFFB_FIFO_GET) != sc->sc_put) && (bail > 0)) { 770 bail--; 771 } 772 if (bail == 0) goto crap; 773 774 /* ... and for the engine to go idle */ 775 bail = 100000000; 776 while((GFFB_READ_4(GFFB_BUSY) != 0) && (bail > 0)) { 777 bail--; 778 } 779 if (bail == 0) goto crap; 780 return; 781 crap: 782 /* if we time out fill the buffer with NOPs and cross fingers */ 783 sc->sc_put = 0; 784 sc->sc_current = 0; 785 for (i = 0; i < 0x2000; i += 4) 786 bus_space_write_stream_4(sc->sc_memt, sc->sc_fbh, i, 0); 787 aprint_error_dev(sc->sc_dev, "DMA lockup\n"); 788 } 789 790 static void 791 gffb_init(struct gffb_softc *sc) 792 { 793 int i; 794 uint32_t foo; 795 796 if (!sc->sc_accel) return; 797 798 sc->sc_fboffset = 0x2000; 799 800 /* init display start */ 801 GFFB_WRITE_4(GFFB_CRTC0 + GFFB_DISPLAYSTART, sc->sc_fboffset); 802 GFFB_WRITE_4(GFFB_CRTC1 + GFFB_DISPLAYSTART, sc->sc_fboffset); 803 GFFB_WRITE_4(GFFB_PDIO0 + GFFB_PEL_MASK, 0xff); 804 GFFB_WRITE_4(GFFB_PDIO1 + GFFB_PEL_MASK, 0xff); 805 806 /* DMA stuff. A whole lot of magic number voodoo from xf86-video-nv */ 807 GFFB_WRITE_4(GFFB_PMC + 0x140, 0); 808 GFFB_WRITE_4(GFFB_PMC + 0x200, 0xffff00ff); 809 GFFB_WRITE_4(GFFB_PMC + 0x200, 0xffffffff); 810 GFFB_WRITE_4(GFFB_PTIMER + 0x800, 8); 811 GFFB_WRITE_4(GFFB_PTIMER + 0x840, 3); 812 GFFB_WRITE_4(GFFB_PTIMER + 0x500, 0); 813 GFFB_WRITE_4(GFFB_PTIMER + 0x400, 0xffffffff); 814 for (i = 0; i < 8; i++) { 815 GFFB_WRITE_4(GFFB_PMC + 0x240 + (i * 0x10), 0); 816 GFFB_WRITE_4(GFFB_PMC + 0x244 + (i * 0x10), 817 sc->sc_vramsize - 1); 818 } 819 820 for (i = 0; i < 8; i++) { 821 GFFB_WRITE_4(GFFB_PFB + 0x0240 + (i * 0x10), 0); 822 GFFB_WRITE_4(GFFB_PFB + 0x0244 + (i * 0x10), 823 sc->sc_vramsize - 1); 824 } 825 826 GFFB_WRITE_4(GFFB_PRAMIN, 0x80000010); 827 GFFB_WRITE_4(GFFB_PRAMIN + 0x04, 0x80011201); 828 GFFB_WRITE_4(GFFB_PRAMIN + 0x08, 0x80000011); 829 GFFB_WRITE_4(GFFB_PRAMIN + 0x0c, 0x80011202); 830 GFFB_WRITE_4(GFFB_PRAMIN + 0x10, 0x80000012); 831 GFFB_WRITE_4(GFFB_PRAMIN + 0x14, 0x80011203); 832 GFFB_WRITE_4(GFFB_PRAMIN + 0x18, 0x80000013); 833 GFFB_WRITE_4(GFFB_PRAMIN + 0x1c, 0x80011204); 834 GFFB_WRITE_4(GFFB_PRAMIN + 0x20, 0x80000014); 835 GFFB_WRITE_4(GFFB_PRAMIN + 0x24, 0x80011205); 836 GFFB_WRITE_4(GFFB_PRAMIN + 0x28, 0x80000015); 837 GFFB_WRITE_4(GFFB_PRAMIN + 0x2c, 0x80011206); 838 GFFB_WRITE_4(GFFB_PRAMIN + 0x30, 0x80000016); 839 GFFB_WRITE_4(GFFB_PRAMIN + 0x34, 0x80011207); 840 GFFB_WRITE_4(GFFB_PRAMIN + 0x38, 0x80000017); 841 GFFB_WRITE_4(GFFB_PRAMIN + 0x3c, 0x80011208); 842 GFFB_WRITE_4(GFFB_PRAMIN + 0x2000, 0x00003000); 843 GFFB_WRITE_4(GFFB_PRAMIN + 0x2004, sc->sc_vramsize - 1); 844 GFFB_WRITE_4(GFFB_PRAMIN + 0x2008, 0x00000002); 845 GFFB_WRITE_4(GFFB_PRAMIN + 0x200c, 0x00000002); 846 GFFB_WRITE_4(GFFB_PRAMIN + 0x2010, 0x01008042); /* different for nv40 */ 847 GFFB_WRITE_4(GFFB_PRAMIN + 0x2014, 0); 848 GFFB_WRITE_4(GFFB_PRAMIN + 0x2018, 0x12001200); 849 GFFB_WRITE_4(GFFB_PRAMIN + 0x201c, 0); 850 GFFB_WRITE_4(GFFB_PRAMIN + 0x2020, 0x01008043); 851 GFFB_WRITE_4(GFFB_PRAMIN + 0x2024, 0); 852 GFFB_WRITE_4(GFFB_PRAMIN + 0x2028, 0); 853 GFFB_WRITE_4(GFFB_PRAMIN + 0x202c, 0); 854 GFFB_WRITE_4(GFFB_PRAMIN + 0x2030, 0x01008044); 855 GFFB_WRITE_4(GFFB_PRAMIN + 0x2034, 0x00000002); 856 GFFB_WRITE_4(GFFB_PRAMIN + 0x2038, 0); 857 GFFB_WRITE_4(GFFB_PRAMIN + 0x203c, 0); 858 GFFB_WRITE_4(GFFB_PRAMIN + 0x2040, 0x01008019); 859 GFFB_WRITE_4(GFFB_PRAMIN + 0x2044, 0); 860 GFFB_WRITE_4(GFFB_PRAMIN + 0x2048, 0); 861 GFFB_WRITE_4(GFFB_PRAMIN + 0x204c, 0); 862 GFFB_WRITE_4(GFFB_PRAMIN + 0x2050, 0x0100a05c); 863 GFFB_WRITE_4(GFFB_PRAMIN + 0x2054, 0); 864 GFFB_WRITE_4(GFFB_PRAMIN + 0x2058, 0); 865 GFFB_WRITE_4(GFFB_PRAMIN + 0x205c, 0); 866 /* XXX 0x0100805f if !WaitVSynvPossible */ 867 GFFB_WRITE_4(GFFB_PRAMIN + 0x2060, 0x0100809f); 868 GFFB_WRITE_4(GFFB_PRAMIN + 0x2064, 0); 869 GFFB_WRITE_4(GFFB_PRAMIN + 0x2068, 0x12001200); 870 GFFB_WRITE_4(GFFB_PRAMIN + 0x206c, 0); 871 GFFB_WRITE_4(GFFB_PRAMIN + 0x2070, 0x0100804a); 872 GFFB_WRITE_4(GFFB_PRAMIN + 0x2074, 0x00000002); 873 GFFB_WRITE_4(GFFB_PRAMIN + 0x2078, 0); 874 GFFB_WRITE_4(GFFB_PRAMIN + 0x207c, 0); 875 GFFB_WRITE_4(GFFB_PRAMIN + 0x2080, 0x01018077); 876 GFFB_WRITE_4(GFFB_PRAMIN + 0x2084, 0); 877 GFFB_WRITE_4(GFFB_PRAMIN + 0x2088, 0x12001200); 878 GFFB_WRITE_4(GFFB_PRAMIN + 0x208c, 0); 879 GFFB_WRITE_4(GFFB_PRAMIN + 0x2090, 0x00003002); 880 GFFB_WRITE_4(GFFB_PRAMIN + 0x2094, 0x00007fff); 881 /* command buffer start with some flag in the lower bits */ 882 GFFB_WRITE_4(GFFB_PRAMIN + 0x2098, 0x00000002); 883 GFFB_WRITE_4(GFFB_PRAMIN + 0x209c, 0x00000002); 884 #if BYTE_ORDER == BIG_ENDIAN 885 GFFB_WRITE_4(GFFB_PRAMIN + 0x2010, 0x01088042); 886 GFFB_WRITE_4(GFFB_PRAMIN + 0x2020, 0x01088043); 887 GFFB_WRITE_4(GFFB_PRAMIN + 0x2030, 0x01088044); 888 GFFB_WRITE_4(GFFB_PRAMIN + 0x2040, 0x01088019); 889 GFFB_WRITE_4(GFFB_PRAMIN + 0x2050, 0x0108a05c); 890 GFFB_WRITE_4(GFFB_PRAMIN + 0x2060, 0x0108809f); 891 GFFB_WRITE_4(GFFB_PRAMIN + 0x2070, 0x0108804a); 892 GFFB_WRITE_4(GFFB_PRAMIN + 0x2080, 0x01098077); 893 GFFB_WRITE_4(GFFB_PRAMIN + 0x2034, 0x00000001); 894 GFFB_WRITE_4(GFFB_PRAMIN + 0x2074, 0x00000001); 895 #endif 896 897 /* PGRAPH setup */ 898 GFFB_WRITE_4(GFFB_PFIFO + 0x0500, 0); 899 GFFB_WRITE_4(GFFB_PFIFO + 0x0504, 0x00000001); 900 GFFB_WRITE_4(GFFB_PFIFO + 0x1200, 0); 901 GFFB_WRITE_4(GFFB_PFIFO + 0x1250, 0); 902 GFFB_WRITE_4(GFFB_PFIFO + 0x1204, 0x00000100); /* different on nv40 */ 903 GFFB_WRITE_4(GFFB_PFIFO + 0x1240, 0); 904 GFFB_WRITE_4(GFFB_PFIFO + 0x1244, 0); 905 GFFB_WRITE_4(GFFB_PFIFO + 0x122c, 0x00001209); /* different on nv40 */ 906 GFFB_WRITE_4(GFFB_PFIFO + 0x1000, 0); 907 GFFB_WRITE_4(GFFB_PFIFO + 0x1050, 0); 908 GFFB_WRITE_4(GFFB_PFIFO + 0x0210, 0x03000100); 909 GFFB_WRITE_4(GFFB_PFIFO + 0x0214, 0x00000110); 910 GFFB_WRITE_4(GFFB_PFIFO + 0x0218, 0x00000112); 911 GFFB_WRITE_4(GFFB_PFIFO + 0x050c, 0x0000ffff); 912 GFFB_WRITE_4(GFFB_PFIFO + 0x1258, 0x0000ffff); 913 GFFB_WRITE_4(GFFB_PFIFO + 0x0140, 0); 914 GFFB_WRITE_4(GFFB_PFIFO + 0x0100, 0xffffffff); 915 GFFB_WRITE_4(GFFB_PFIFO + 0x1054, 0x00000001); 916 GFFB_WRITE_4(GFFB_PFIFO + 0x1230, 0); 917 GFFB_WRITE_4(GFFB_PFIFO + 0x1280, 0); 918 #if BYTE_ORDER == BIG_ENDIAN 919 GFFB_WRITE_4(GFFB_PFIFO + 0x1224, 0x800f0078); 920 #else 921 GFFB_WRITE_4(GFFB_PFIFO + 0x1224, 0x000f0078); 922 #endif 923 GFFB_WRITE_4(GFFB_PFIFO + 0x1220, 0x00000001); 924 GFFB_WRITE_4(GFFB_PFIFO + 0x1200, 0x00000001); 925 GFFB_WRITE_4(GFFB_PFIFO + 0x1250, 0x00000001); 926 GFFB_WRITE_4(GFFB_PFIFO + 0x1254, 0x00000001); 927 GFFB_WRITE_4(GFFB_PFIFO + 0x0500, 0x00000001); 928 929 GFFB_WRITE_4(GFFB_PGRAPH + 0x0080, 0xFFFFFFFF); 930 GFFB_WRITE_4(GFFB_PGRAPH + 0x0080, 0x00000000); 931 932 GFFB_WRITE_4(GFFB_PGRAPH + 0x0140, 0x00000000); 933 GFFB_WRITE_4(GFFB_PGRAPH + 0x0100, 0xFFFFFFFF); 934 GFFB_WRITE_4(GFFB_PGRAPH + 0x0144, 0x10010100); 935 GFFB_WRITE_4(GFFB_PGRAPH + 0x0714, 0xFFFFFFFF); 936 GFFB_WRITE_4(GFFB_PGRAPH + 0x0720, 0x00000001); 937 /* 938 * xf86_video_nv does this in two writes, 939 * not sure if they can be combined 940 */ 941 foo = GFFB_READ_4(GFFB_PGRAPH + 0x0710); 942 GFFB_WRITE_4(GFFB_PGRAPH + 0x0710, foo & 0x0007ff00); 943 foo = GFFB_READ_4(GFFB_PGRAPH + 0x0710); 944 GFFB_WRITE_4(GFFB_PGRAPH + 0x0710, foo | 0x00020100); 945 946 /* NV_ARCH_10 */ 947 GFFB_WRITE_4(GFFB_PGRAPH + 0x0084, 0x00118700); 948 GFFB_WRITE_4(GFFB_PGRAPH + 0x0088, 0x24E00810); 949 GFFB_WRITE_4(GFFB_PGRAPH + 0x008C, 0x55DE0030); 950 951 for(i = 0; i < 128; i += 4) { 952 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B00 + i, 953 GFFB_READ_4(GFFB_PFB + 0x0240 + i)); 954 } 955 956 GFFB_WRITE_4(GFFB_PGRAPH + 0x640, 0); 957 GFFB_WRITE_4(GFFB_PGRAPH + 0x644, 0); 958 GFFB_WRITE_4(GFFB_PGRAPH + 0x684, sc->sc_vramsize - 1); 959 GFFB_WRITE_4(GFFB_PGRAPH + 0x688, sc->sc_vramsize - 1); 960 961 GFFB_WRITE_4(GFFB_PGRAPH + 0x0810, 0x00000000); 962 GFFB_WRITE_4(GFFB_PGRAPH + 0x0608, 0xFFFFFFFF); 963 964 GFFB_WRITE_4(GFFB_PGRAPH + 0x053C, 0); 965 GFFB_WRITE_4(GFFB_PGRAPH + 0x0540, 0); 966 GFFB_WRITE_4(GFFB_PGRAPH + 0x0544, 0x00007FFF); 967 GFFB_WRITE_4(GFFB_PGRAPH + 0x0548, 0x00007FFF); 968 969 GFFB_WRITE_4(GFFB_CMDSTART, 0x00000002); 970 GFFB_WRITE_4(GFFB_FIFO_GET, 0); 971 sc->sc_put = 0; 972 sc->sc_current = 0; 973 sc->sc_free = 0x2000; 974 975 for(i = 0; i < SKIPS; i++) 976 gffb_dmanext(sc, 0); 977 978 gffb_dmanext(sc, 0x00040000); 979 gffb_dmanext(sc, 0x80000010); 980 gffb_dmanext(sc, 0x00042000); 981 gffb_dmanext(sc, 0x80000011); 982 gffb_dmanext(sc, 0x00044000); 983 gffb_dmanext(sc, 0x80000012); 984 gffb_dmanext(sc, 0x00046000); 985 gffb_dmanext(sc, 0x80000013); 986 gffb_dmanext(sc, 0x00048000); 987 gffb_dmanext(sc, 0x80000014); 988 gffb_dmanext(sc, 0x0004A000); 989 gffb_dmanext(sc, 0x80000015); 990 gffb_dmanext(sc, 0x0004C000); 991 gffb_dmanext(sc, 0x80000016); 992 gffb_dmanext(sc, 0x0004E000); 993 gffb_dmanext(sc, 0x80000017); 994 sc->sc_free = 0x2000 - sc->sc_current; 995 996 gffb_dmastart(sc, SURFACE_FORMAT, 4); 997 gffb_dmanext(sc, SURFACE_FORMAT_DEPTH8); 998 gffb_dmanext(sc, sc->sc_stride | (sc->sc_stride << 16)); 999 gffb_dmanext(sc, 0x2000); /* src offset */ 1000 gffb_dmanext(sc, 0x2000); /* dst offset */ 1001 1002 gffb_dmastart(sc, RECT_FORMAT, 1); 1003 gffb_dmanext(sc, RECT_FORMAT_DEPTH8); 1004 1005 gffb_dmastart(sc, PATTERN_FORMAT, 1); 1006 gffb_dmanext(sc, PATTERN_FORMAT_DEPTH8); 1007 1008 gffb_dmastart(sc, PATTERN_COLOR_0, 4); 1009 gffb_dmanext(sc, 0xffffffff); 1010 gffb_dmanext(sc, 0xffffffff); 1011 gffb_dmanext(sc, 0xffffffff); 1012 gffb_dmanext(sc, 0xffffffff); 1013 1014 gffb_dmastart(sc, ROP_SET, 1); 1015 gffb_dmanext(sc, 0xcc); 1016 sc->sc_rop = 0xcc; 1017 1018 gffb_dma_kickoff(sc); 1019 gffb_sync(sc); 1020 DPRINTF("put %x current %x\n", sc->sc_put, sc->sc_current); 1021 1022 } 1023 1024 static void 1025 gffb_rop(struct gffb_softc *sc, int rop) 1026 { 1027 if (rop == sc->sc_rop) 1028 return; 1029 sc->sc_rop = rop; 1030 gffb_dmastart(sc, ROP_SET, 1); 1031 gffb_dmanext(sc, rop); 1032 } 1033 1034 static void 1035 gffb_rectfill(struct gffb_softc *sc, int x, int y, int wi, int he, 1036 uint32_t colour) 1037 { 1038 if (!sc->sc_accel) return; 1039 mutex_enter(&sc->sc_lock); 1040 gffb_rop(sc, 0xcc); 1041 1042 gffb_dmastart(sc, RECT_SOLID_COLOR, 1); 1043 gffb_dmanext(sc, colour); 1044 1045 gffb_dmastart(sc, RECT_SOLID_RECTS(0), 2); 1046 gffb_dmanext(sc, (x << 16) | y); 1047 gffb_dmanext(sc, (wi << 16) | he); 1048 gffb_dma_kickoff(sc); 1049 mutex_exit(&sc->sc_lock); 1050 } 1051 1052 static void 1053 gffb_bitblt(void *cookie, int xs, int ys, int xd, int yd, 1054 int wi, int he, int rop) 1055 { 1056 struct gffb_softc *sc = cookie; 1057 1058 if (!sc->sc_accel) return; 1059 mutex_enter(&sc->sc_lock); 1060 1061 gffb_rop(sc, rop); 1062 1063 gffb_dmastart(sc, BLIT_POINT_SRC, 3); 1064 gffb_dmanext(sc, (ys << 16) | xs); 1065 gffb_dmanext(sc, (yd << 16) | xd); 1066 gffb_dmanext(sc, (he << 16) | wi); 1067 gffb_dma_kickoff(sc); 1068 mutex_exit(&sc->sc_lock); 1069 } 1070 1071 static void 1072 gffb_cursor(void *cookie, int on, int row, int col) 1073 { 1074 struct rasops_info *ri = cookie; 1075 struct vcons_screen *scr = ri->ri_hw; 1076 struct gffb_softc *sc = scr->scr_cookie; 1077 int x, y, wi, he; 1078 1079 wi = ri->ri_font->fontwidth; 1080 he = ri->ri_font->fontheight; 1081 1082 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1083 x = ri->ri_ccol * wi + ri->ri_xorigin; 1084 y = ri->ri_crow * he + ri->ri_yorigin; 1085 if (ri->ri_flg & RI_CURSOR) { 1086 gffb_bitblt(sc, x, y, x, y, wi, he, 0x33); 1087 ri->ri_flg &= ~RI_CURSOR; 1088 } 1089 ri->ri_crow = row; 1090 ri->ri_ccol = col; 1091 if (on) { 1092 x = ri->ri_ccol * wi + ri->ri_xorigin; 1093 y = ri->ri_crow * he + ri->ri_yorigin; 1094 gffb_bitblt(sc, x, y, x, y, wi, he, 0x33); 1095 ri->ri_flg |= RI_CURSOR; 1096 } 1097 } else { 1098 scr->scr_ri.ri_crow = row; 1099 scr->scr_ri.ri_ccol = col; 1100 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1101 } 1102 1103 } 1104 1105 static void 1106 gffb_putchar(void *cookie, int row, int col, u_int c, long attr) 1107 { 1108 struct rasops_info *ri = cookie; 1109 struct wsdisplay_font *font = PICK_FONT(ri, c); 1110 struct vcons_screen *scr = ri->ri_hw; 1111 struct gffb_softc *sc = scr->scr_cookie; 1112 int x, y, wi, he, rv = GC_NOPE; 1113 uint32_t bg; 1114 1115 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1116 return; 1117 1118 if (!CHAR_IN_FONT(c, font)) 1119 return; 1120 1121 wi = font->fontwidth; 1122 he = font->fontheight; 1123 1124 x = ri->ri_xorigin + col * wi; 1125 y = ri->ri_yorigin + row * he; 1126 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1127 1128 if (c == 0x20) { 1129 gffb_rectfill(sc, x, y, wi, he, bg); 1130 return; 1131 } 1132 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1133 if (rv == GC_OK) 1134 return; 1135 1136 mutex_enter(&sc->sc_lock); 1137 gffb_sync(sc); 1138 sc->sc_putchar(cookie, row, col, c, attr); 1139 membar_sync(); 1140 mutex_exit(&sc->sc_lock); 1141 1142 if (rv == GC_ADD) { 1143 glyphcache_add(&sc->sc_gc, c, x, y); 1144 } 1145 } 1146 1147 static void 1148 gffb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1149 { 1150 struct rasops_info *ri = cookie; 1151 struct vcons_screen *scr = ri->ri_hw; 1152 struct gffb_softc *sc = scr->scr_cookie; 1153 int32_t xs, xd, y, width, height; 1154 1155 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1156 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1157 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1158 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1159 width = ri->ri_font->fontwidth * ncols; 1160 height = ri->ri_font->fontheight; 1161 gffb_bitblt(sc, xs, y, xd, y, width, height, 0xcc); 1162 } 1163 } 1164 1165 static void 1166 gffb_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1167 { 1168 struct rasops_info *ri = cookie; 1169 struct vcons_screen *scr = ri->ri_hw; 1170 struct gffb_softc *sc = scr->scr_cookie; 1171 int32_t x, y, width, height, fg, bg, ul; 1172 1173 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1174 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1175 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1176 width = ri->ri_font->fontwidth * ncols; 1177 height = ri->ri_font->fontheight; 1178 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1179 1180 gffb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1181 } 1182 } 1183 1184 static void 1185 gffb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1186 { 1187 struct rasops_info *ri = cookie; 1188 struct vcons_screen *scr = ri->ri_hw; 1189 struct gffb_softc *sc = scr->scr_cookie; 1190 int32_t x, ys, yd, width, height; 1191 1192 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1193 x = ri->ri_xorigin; 1194 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1195 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1196 width = ri->ri_emuwidth; 1197 height = ri->ri_font->fontheight * nrows; 1198 gffb_bitblt(sc, x, ys, x, yd, width, height, 0xcc); 1199 } 1200 } 1201 1202 static void 1203 gffb_eraserows(void *cookie, int row, int nrows, long fillattr) 1204 { 1205 struct rasops_info *ri = cookie; 1206 struct vcons_screen *scr = ri->ri_hw; 1207 struct gffb_softc *sc = scr->scr_cookie; 1208 int32_t x, y, width, height, fg, bg, ul; 1209 1210 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1211 x = ri->ri_xorigin; 1212 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1213 width = ri->ri_emuwidth; 1214 height = ri->ri_font->fontheight * nrows; 1215 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1216 1217 gffb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1218 } 1219 } 1220
Indexes created Fri Oct 17 09:09:57 GMT 2025