gffb.c revision 1.17
1 /* $NetBSD: gffb.c,v 1.17 2021/08/07 16:19:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * A console driver for nvidia geforce graphics controllers 30 * tested on macppc only so far, should work on other hardware as long as 31 * something sets up a usable graphics mode and sets the right device properties 32 * This driver should work with all NV1x hardware but so far it's been tested 33 * only on NV11 / GeForce2 MX. Needs testing with more hardware and if 34 * successful, PCI IDs need to be added to gffb_match() 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: gffb.c,v 1.17 2021/08/07 16:19:14 thorpej Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/lwp.h> 46 #include <sys/kauth.h> 47 #include <sys/atomic.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/pciio.h> 53 #include <dev/pci/gffbreg.h> 54 55 #include <dev/wscons/wsdisplayvar.h> 56 #include <dev/wscons/wsconsio.h> 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/rasops/rasops.h> 59 #include <dev/wscons/wsdisplay_vconsvar.h> 60 #include <dev/pci/wsdisplay_pci.h> 61 #include <dev/wscons/wsdisplay_glyphcachevar.h> 62 63 #include "opt_gffb.h" 64 #include "opt_vcons.h" 65 66 #ifdef GFFB_DEBUG 67 #define DPRINTF printf 68 #else 69 #define DPRINTF while(0) printf 70 #endif 71 72 struct gffb_softc { 73 device_t sc_dev; 74 75 pci_chipset_tag_t sc_pc; 76 pcitag_t sc_pcitag; 77 78 bus_space_tag_t sc_memt; 79 bus_space_tag_t sc_iot; 80 81 bus_space_handle_t sc_regh, sc_fbh; 82 bus_addr_t sc_fb, sc_reg; 83 bus_size_t sc_fbsize, sc_regsize; 84 uint8_t *sc_fbaddr; 85 size_t sc_vramsize; 86 uint32_t sc_fboffset; 87 88 int sc_width, sc_height, sc_depth, sc_stride; 89 int sc_locked, sc_accel; 90 struct vcons_screen sc_console_screen; 91 struct wsscreen_descr sc_defaultscreen_descr; 92 const struct wsscreen_descr *sc_screens[1]; 93 struct wsscreen_list sc_screenlist; 94 struct vcons_data vd; 95 int sc_mode; 96 u_char sc_cmap_red[256]; 97 u_char sc_cmap_green[256]; 98 u_char sc_cmap_blue[256]; 99 int sc_put, sc_current, sc_free; 100 uint32_t sc_rop; 101 void (*sc_putchar)(void *, int, int, u_int, long); 102 kmutex_t sc_lock; 103 glyphcache sc_gc; 104 }; 105 106 static int gffb_match(device_t, cfdata_t, void *); 107 static void gffb_attach(device_t, device_t, void *); 108 109 CFATTACH_DECL_NEW(gffb, sizeof(struct gffb_softc), 110 gffb_match, gffb_attach, NULL, NULL); 111 112 static int gffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 113 static paddr_t gffb_mmap(void *, void *, off_t, int); 114 static void gffb_init_screen(void *, struct vcons_screen *, int, long *); 115 116 static int gffb_putcmap(struct gffb_softc *, struct wsdisplay_cmap *); 117 static int gffb_getcmap(struct gffb_softc *, struct wsdisplay_cmap *); 118 static void gffb_restore_palette(struct gffb_softc *); 119 static int gffb_putpalreg(struct gffb_softc *, uint8_t, uint8_t, 120 uint8_t, uint8_t); 121 122 static void gffb_init(struct gffb_softc *); 123 124 static void gffb_make_room(struct gffb_softc *, int); 125 static void gffb_sync(struct gffb_softc *); 126 127 static void gffb_rectfill(struct gffb_softc *, int, int, int, int, 128 uint32_t); 129 static void gffb_bitblt(void *, int, int, int, int, int, int, int); 130 static void gffb_rop(struct gffb_softc *, int); 131 132 static void gffb_cursor(void *, int, int, int); 133 static void gffb_putchar(void *, int, int, u_int, long); 134 static void gffb_copycols(void *, int, int, int, int); 135 static void gffb_erasecols(void *, int, int, int, long); 136 static void gffb_copyrows(void *, int, int, int); 137 static void gffb_eraserows(void *, int, int, long); 138 139 #define GFFB_READ_4(o) bus_space_read_4(sc->sc_memt, sc->sc_regh, (o)) 140 #define GFFB_WRITE_4(o, v) bus_space_write_4(sc->sc_memt, sc->sc_regh, (o), (v)) 141 142 struct wsdisplay_accessops gffb_accessops = { 143 gffb_ioctl, 144 gffb_mmap, 145 NULL, /* alloc_screen */ 146 NULL, /* free_screen */ 147 NULL, /* show_screen */ 148 NULL, /* load_font */ 149 NULL, /* pollc */ 150 NULL /* scroll */ 151 }; 152 153 static int 154 gffb_match(device_t parent, cfdata_t match, void *aux) 155 { 156 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 157 158 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 159 return 0; 160 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_NVIDIA) 161 return 0; 162 163 /* only card tested on so far - likely need a list */ 164 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GEFORCE2MX) 165 return 100; 166 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GEFORCE_6800U) 167 return 100; 168 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GF_FXGO5200) 169 return 100; 170 return (0); 171 } 172 173 static void 174 gffb_attach(device_t parent, device_t self, void *aux) 175 { 176 struct gffb_softc *sc = device_private(self); 177 struct pci_attach_args *pa = aux; 178 struct rasops_info *ri; 179 bus_space_tag_t tag; 180 struct wsemuldisplaydev_attach_args aa; 181 prop_dictionary_t dict; 182 unsigned long defattr; 183 pcireg_t reg; 184 bool is_console = FALSE; 185 uint32_t addr; 186 int i, j, f; 187 uint8_t cmap[768]; 188 189 sc->sc_pc = pa->pa_pc; 190 sc->sc_pcitag = pa->pa_tag; 191 sc->sc_memt = pa->pa_memt; 192 sc->sc_iot = pa->pa_iot; 193 sc->sc_dev = self; 194 195 /* first, see what kind of chip we've got */ 196 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_ID_REG); 197 sc->sc_accel = PCI_PRODUCT(reg) == PCI_PRODUCT_NVIDIA_GEFORCE2MX; 198 199 pci_aprint_devinfo(pa, NULL); 200 201 /* fill in parameters from properties */ 202 dict = device_properties(self); 203 if (!prop_dictionary_get_uint32(dict, "width", &sc->sc_width)) { 204 aprint_error("%s: no width property\n", device_xname(self)); 205 return; 206 } 207 if (!prop_dictionary_get_uint32(dict, "height", &sc->sc_height)) { 208 aprint_error("%s: no height property\n", device_xname(self)); 209 return; 210 } 211 212 #ifdef GLYPHCACHE_DEBUG 213 /* leave some visible VRAM unused so we can see the glyph cache */ 214 sc->sc_height -= 300; 215 #endif 216 217 if (!prop_dictionary_get_uint32(dict, "depth", &sc->sc_depth)) { 218 aprint_error("%s: no depth property\n", device_xname(self)); 219 return; 220 } 221 if (!prop_dictionary_get_uint32(dict, "linebytes", &sc->sc_stride)) { 222 aprint_error("%s: no linebytes property\n", 223 device_xname(self)); 224 return; 225 } 226 227 /* 228 * on !2MX we need to use the firmware's offset - for some reason 229 * register writes to anything other than the DACs go wrong 230 */ 231 sc->sc_fboffset = 0; 232 if (prop_dictionary_get_uint32(dict, "address", &addr)) { 233 sc->sc_fboffset = addr & 0x000fffff; /* XXX */ 234 } 235 236 prop_dictionary_get_bool(dict, "is_console", &is_console); 237 238 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_MEM, 0, 239 &tag, &sc->sc_regh, &sc->sc_reg, &sc->sc_regsize)) { 240 aprint_error("%s: failed to map registers.\n", 241 device_xname(sc->sc_dev)); 242 } 243 sc->sc_vramsize = GFFB_READ_4(GFFB_VRAM) & 0xfff00000; 244 245 /* don't map more VRAM than we actually have */ 246 if (pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, 247 0x14, PCI_MAPREG_TYPE_MEM, &sc->sc_fb, &sc->sc_fbsize, &f)) { 248 aprint_error("%s: can't find the framebuffer?!\n", 249 device_xname(sc->sc_dev)); 250 } 251 if (sc->sc_vramsize == 0) sc->sc_vramsize = sc->sc_fbsize; 252 253 /* don't map (much) more than we actually need */ 254 if (bus_space_map(sc->sc_memt, sc->sc_fb, 0x1000000, 255 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, 256 &sc->sc_fbh)) { 257 aprint_error("%s: failed to map the framebuffer.\n", 258 device_xname(sc->sc_dev)); 259 } 260 sc->sc_fbaddr = bus_space_vaddr(tag, sc->sc_fbh); 261 262 aprint_normal("%s: %d MB aperture at 0x%08x\n", device_xname(self), 263 (int)(sc->sc_fbsize >> 20), (uint32_t)sc->sc_fb); 264 aprint_normal_dev(sc->sc_dev, "%d MB video memory\n", 265 (int)(sc->sc_vramsize >> 20)); 266 267 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 268 "default", 269 0, 0, 270 NULL, 271 8, 16, 272 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 273 NULL 274 }; 275 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 276 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 277 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 278 sc->sc_locked = 0; 279 280 #ifdef GFFB_DEBUG 281 printf("put: %08x\n", GFFB_READ_4(GFFB_FIFO_PUT)); 282 printf("get: %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 283 #endif 284 285 /* 286 * we don't have hardware synchronization so we need a lock to serialize 287 * access to the DMA buffer between normal and kernel output 288 * actually it might be enough to use atomic ops on sc_current, sc_free 289 * etc. but for now we'll play it safe 290 * XXX we will probably deadlock if we take an interrupt while sc_lock 291 * is held and then try to printf() 292 */ 293 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 294 295 /* init engine here */ 296 gffb_init(sc); 297 298 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 299 &gffb_accessops); 300 sc->vd.init_screen = gffb_init_screen; 301 302 303 ri = &sc->sc_console_screen.scr_ri; 304 305 if (sc->sc_accel) { 306 sc->sc_gc.gc_bitblt = gffb_bitblt; 307 sc->sc_gc.gc_blitcookie = sc; 308 sc->sc_gc.gc_rop = 0xcc; 309 } 310 311 if (is_console) { 312 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 313 &defattr); 314 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 315 316 if (sc->sc_accel) { 317 gffb_rectfill(sc, 0, 0, sc->sc_width, sc->sc_height, 318 ri->ri_devcmap[(defattr >> 16) & 0xf]); 319 } else { 320 memset(sc->sc_fbaddr + sc->sc_fboffset, 321 ri->ri_devcmap[(defattr >> 16) & 0xf], 322 sc->sc_stride * sc->sc_height); 323 } 324 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 325 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 326 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 327 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 328 329 if (sc->sc_accel) 330 glyphcache_init(&sc->sc_gc, sc->sc_height + 5, 331 (0x800000 / sc->sc_stride) - sc->sc_height - 5, 332 sc->sc_width, 333 ri->ri_font->fontwidth, 334 ri->ri_font->fontheight, 335 defattr); 336 337 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 338 defattr); 339 vcons_replay_msgbuf(&sc->sc_console_screen); 340 } else { 341 /* 342 * since we're not the console we can postpone the rest 343 * until someone actually allocates a screen for us 344 */ 345 if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 346 /* do some minimal setup to avoid weirdnesses later */ 347 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 348 &defattr); 349 } else 350 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 351 352 if (sc->sc_accel) 353 glyphcache_init(&sc->sc_gc, sc->sc_height + 5, 354 (0x800000 / sc->sc_stride) - sc->sc_height - 5, 355 sc->sc_width, 356 ri->ri_font->fontwidth, 357 ri->ri_font->fontheight, 358 defattr); 359 } 360 361 j = 0; 362 rasops_get_cmap(ri, cmap, sizeof(cmap)); 363 for (i = 0; i < 256; i++) { 364 sc->sc_cmap_red[i] = cmap[j]; 365 sc->sc_cmap_green[i] = cmap[j + 1]; 366 sc->sc_cmap_blue[i] = cmap[j + 2]; 367 gffb_putpalreg(sc, i, cmap[j], cmap[j + 1], cmap[j + 2]); 368 j += 3; 369 } 370 371 /* no suspend/resume support yet */ 372 if (!pmf_device_register(sc->sc_dev, NULL, NULL)) 373 aprint_error_dev(sc->sc_dev, 374 "couldn't establish power handler\n"); 375 376 aa.console = is_console; 377 aa.scrdata = &sc->sc_screenlist; 378 aa.accessops = &gffb_accessops; 379 aa.accesscookie = &sc->vd; 380 381 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint, CFARGS_NONE); 382 383 #ifdef GFFB_DEBUG 384 for (i = 0; i < 40; i++) { 385 for (j = 0; j < 40; j++) { 386 gffb_rectfill(sc, i * 20, j * 20, 20, 20, 387 (i + j ) & 1 ? 0xe0e0e0e0 : 0x03030303); 388 } 389 } 390 391 gffb_rectfill(sc, 0, 800, 1280, 224, 0x92929292); 392 gffb_bitblt(sc, 0, 10, 10, 810, 200, 20, 0xcc); 393 gffb_bitblt(sc, 0, 10, 10, 840, 300, 20, 0xcc); 394 gffb_bitblt(sc, 0, 10, 10, 870, 400, 20, 0xcc); 395 gffb_bitblt(sc, 0, 10, 10, 900, 500, 20, 0xcc); 396 gffb_bitblt(sc, 0, 10, 10, 930, 600, 20, 0xcc); 397 gffb_bitblt(sc, 0, 10, 610, 810, 200, 20, 0xcc); 398 gffb_bitblt(sc, 0, 10, 610, 840, 300, 20, 0xcc); 399 gffb_bitblt(sc, 0, 10, 610, 870, 400, 20, 0xcc); 400 gffb_bitblt(sc, 0, 10, 610, 900, 500, 20, 0xcc); 401 gffb_bitblt(sc, 0, 10, 610, 930, 600, 20, 0xcc); 402 gffb_sync(sc); 403 printf("put %x current %x\n", sc->sc_put, sc->sc_current); 404 #endif 405 } 406 407 static int 408 gffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 409 { 410 struct vcons_data *vd = v; 411 struct gffb_softc *sc = vd->cookie; 412 struct wsdisplay_fbinfo *wdf; 413 struct vcons_screen *ms = vd->active; 414 415 switch (cmd) { 416 case WSDISPLAYIO_GTYPE: 417 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 418 return 0; 419 420 /* PCI config read/write passthrough. */ 421 case PCI_IOC_CFGREAD: 422 case PCI_IOC_CFGWRITE: 423 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 424 cmd, data, flag, l); 425 426 case WSDISPLAYIO_GET_BUSID: 427 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 428 sc->sc_pcitag, data); 429 430 case WSDISPLAYIO_GINFO: 431 if (ms == NULL) 432 return ENODEV; 433 wdf = (void *)data; 434 wdf->height = ms->scr_ri.ri_height; 435 wdf->width = ms->scr_ri.ri_width; 436 wdf->depth = ms->scr_ri.ri_depth; 437 wdf->cmsize = 256; 438 return 0; 439 440 case WSDISPLAYIO_GETCMAP: 441 return gffb_getcmap(sc, 442 (struct wsdisplay_cmap *)data); 443 444 case WSDISPLAYIO_PUTCMAP: 445 return gffb_putcmap(sc, 446 (struct wsdisplay_cmap *)data); 447 448 case WSDISPLAYIO_LINEBYTES: 449 *(u_int *)data = sc->sc_stride; 450 return 0; 451 452 case WSDISPLAYIO_SMODE: { 453 int new_mode = *(int*)data; 454 if (new_mode != sc->sc_mode) { 455 sc->sc_mode = new_mode; 456 if(new_mode == WSDISPLAYIO_MODE_EMUL) { 457 gffb_init(sc); 458 gffb_restore_palette(sc); 459 if (sc->sc_accel) { 460 glyphcache_wipe(&sc->sc_gc); 461 gffb_rectfill(sc, 0, 0, sc->sc_width, 462 sc->sc_height, ms->scr_ri.ri_devcmap[ 463 (ms->scr_defattr >> 16) & 0xf]); 464 } else { 465 memset(sc->sc_fbaddr + sc->sc_fboffset, 466 ms->scr_ri.ri_devcmap[ 467 (ms->scr_defattr >> 16) & 0xf], 468 sc->sc_stride * sc->sc_height); 469 } 470 vcons_redraw_screen(ms); 471 } 472 } 473 } 474 return 0; 475 476 case WSDISPLAYIO_GET_EDID: { 477 struct wsdisplayio_edid_info *d = data; 478 return wsdisplayio_get_edid(sc->sc_dev, d); 479 } 480 481 case WSDISPLAYIO_GET_FBINFO: { 482 struct wsdisplayio_fbinfo *fbi = data; 483 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 484 } 485 } 486 return EPASSTHROUGH; 487 } 488 489 static paddr_t 490 gffb_mmap(void *v, void *vs, off_t offset, int prot) 491 { 492 struct vcons_data *vd = v; 493 struct gffb_softc *sc = vd->cookie; 494 paddr_t pa; 495 496 /* 'regular' framebuffer mmap()ing */ 497 if (offset < sc->sc_vramsize) { 498 pa = bus_space_mmap(sc->sc_memt, sc->sc_fb + offset + 0x2000, 499 0, prot, BUS_SPACE_MAP_LINEAR); 500 return pa; 501 } 502 503 /* 504 * restrict all other mappings to processes with superuser privileges 505 * or the kernel itself 506 */ 507 if (kauth_authorize_machdep(kauth_cred_get(), 508 KAUTH_MACHDEP_UNMANAGEDMEM, 509 NULL, NULL, NULL, NULL) != 0) { 510 aprint_normal("%s: mmap() rejected.\n", 511 device_xname(sc->sc_dev)); 512 return -1; 513 } 514 515 if ((offset >= sc->sc_fb) && (offset < (sc->sc_fb + sc->sc_fbsize))) { 516 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 517 BUS_SPACE_MAP_LINEAR); 518 return pa; 519 } 520 521 if ((offset >= sc->sc_reg) && 522 (offset < (sc->sc_reg + sc->sc_regsize))) { 523 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 524 BUS_SPACE_MAP_LINEAR); 525 return pa; 526 } 527 528 #ifdef PCI_MAGIC_IO_RANGE 529 /* allow mapping of IO space */ 530 if ((offset >= PCI_MAGIC_IO_RANGE) && 531 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 532 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 533 0, prot, BUS_SPACE_MAP_LINEAR); 534 return pa; 535 } 536 #endif 537 538 return -1; 539 } 540 541 static void 542 gffb_init_screen(void *cookie, struct vcons_screen *scr, 543 int existing, long *defattr) 544 { 545 struct gffb_softc *sc = cookie; 546 struct rasops_info *ri = &scr->scr_ri; 547 548 ri->ri_depth = sc->sc_depth; 549 ri->ri_width = sc->sc_width; 550 ri->ri_height = sc->sc_height; 551 ri->ri_stride = sc->sc_stride; 552 if (sc->sc_depth == 8) 553 ri->ri_bits = sc->sc_fbaddr + sc->sc_fboffset; 554 ri->ri_flg = RI_CENTER; 555 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA; 556 557 rasops_init(ri, 0, 0); 558 ri->ri_caps = WSSCREEN_WSCOLORS; 559 560 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 561 sc->sc_width / ri->ri_font->fontwidth); 562 563 ri->ri_hw = scr; 564 565 if (sc->sc_accel) { 566 sc->sc_putchar = ri->ri_ops.putchar; 567 ri->ri_ops.copyrows = gffb_copyrows; 568 ri->ri_ops.copycols = gffb_copycols; 569 ri->ri_ops.eraserows = gffb_eraserows; 570 ri->ri_ops.erasecols = gffb_erasecols; 571 ri->ri_ops.cursor = gffb_cursor; 572 ri->ri_ops.putchar = gffb_putchar; 573 } else { 574 scr->scr_flags |= VCONS_DONT_READ; 575 } 576 } 577 578 static int 579 gffb_putcmap(struct gffb_softc *sc, struct wsdisplay_cmap *cm) 580 { 581 u_char *r, *g, *b; 582 u_int index = cm->index; 583 u_int count = cm->count; 584 int i, error; 585 u_char rbuf[256], gbuf[256], bbuf[256]; 586 587 #ifdef GFFB_DEBUG 588 aprint_debug("putcmap: %d %d\n",index, count); 589 #endif 590 if (cm->index >= 256 || cm->count > 256 || 591 (cm->index + cm->count) > 256) 592 return EINVAL; 593 error = copyin(cm->red, &rbuf[index], count); 594 if (error) 595 return error; 596 error = copyin(cm->green, &gbuf[index], count); 597 if (error) 598 return error; 599 error = copyin(cm->blue, &bbuf[index], count); 600 if (error) 601 return error; 602 603 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 604 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 605 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 606 607 r = &sc->sc_cmap_red[index]; 608 g = &sc->sc_cmap_green[index]; 609 b = &sc->sc_cmap_blue[index]; 610 611 for (i = 0; i < count; i++) { 612 gffb_putpalreg(sc, index, *r, *g, *b); 613 index++; 614 r++, g++, b++; 615 } 616 return 0; 617 } 618 619 static int 620 gffb_getcmap(struct gffb_softc *sc, struct wsdisplay_cmap *cm) 621 { 622 u_int index = cm->index; 623 u_int count = cm->count; 624 int error; 625 626 if (index >= 255 || count > 256 || index + count > 256) 627 return EINVAL; 628 629 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 630 if (error) 631 return error; 632 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 633 if (error) 634 return error; 635 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 636 if (error) 637 return error; 638 639 return 0; 640 } 641 642 static void 643 gffb_restore_palette(struct gffb_softc *sc) 644 { 645 int i; 646 647 for (i = 0; i < (1 << sc->sc_depth); i++) { 648 gffb_putpalreg(sc, i, sc->sc_cmap_red[i], 649 sc->sc_cmap_green[i], sc->sc_cmap_blue[i]); 650 } 651 } 652 653 static int 654 gffb_putpalreg(struct gffb_softc *sc, uint8_t idx, uint8_t r, uint8_t g, 655 uint8_t b) 656 { 657 /* port 0 */ 658 bus_space_write_1(sc->sc_memt, sc->sc_regh, 659 GFFB_PDIO0 + GFFB_PEL_IW, idx); 660 bus_space_write_1(sc->sc_memt, sc->sc_regh, 661 GFFB_PDIO0 + GFFB_PEL_D, r); 662 bus_space_write_1(sc->sc_memt, sc->sc_regh, 663 GFFB_PDIO0 + GFFB_PEL_D, g); 664 bus_space_write_1(sc->sc_memt, sc->sc_regh, 665 GFFB_PDIO0 + GFFB_PEL_D, b); 666 667 /* port 1 */ 668 bus_space_write_1(sc->sc_memt, sc->sc_regh, 669 GFFB_PDIO1 + GFFB_PEL_IW, idx); 670 bus_space_write_1(sc->sc_memt, sc->sc_regh, 671 GFFB_PDIO1 + GFFB_PEL_D, r); 672 bus_space_write_1(sc->sc_memt, sc->sc_regh, 673 GFFB_PDIO1 + GFFB_PEL_D, g); 674 bus_space_write_1(sc->sc_memt, sc->sc_regh, 675 GFFB_PDIO1 + GFFB_PEL_D, b); 676 677 return 0; 678 } 679 680 681 static void 682 gffb_dma_kickoff(struct gffb_softc *sc) 683 { 684 685 if (sc->sc_current != sc->sc_put) { 686 sc->sc_put = sc->sc_current; 687 membar_sync(); 688 (void)*sc->sc_fbaddr; 689 GFFB_WRITE_4(GFFB_FIFO_PUT, sc->sc_put); 690 membar_sync(); 691 } 692 } 693 694 static void 695 gffb_dmanext(struct gffb_softc *sc, uint32_t data) 696 { 697 bus_space_write_stream_4(sc->sc_memt, sc->sc_fbh, sc->sc_current, data); 698 sc->sc_current += 4; 699 } 700 701 static void 702 gffb_dmastart(struct gffb_softc *sc, uint32_t tag, int size) 703 { 704 if(sc->sc_free <= (size << 2)) 705 gffb_make_room(sc, size); 706 gffb_dmanext(sc, ((size) << 18) | (tag)); 707 sc->sc_free -= ((size + 1) << 2); 708 } 709 710 /* 711 * from xf86_video_nv/nv_xaa.c: 712 * There is a HW race condition with videoram command buffers. 713 * You can't jump to the location of your put offset. We write put 714 * at the jump offset + SKIPS dwords with noop padding in between 715 * to solve this problem 716 */ 717 718 #define SKIPS 8 719 720 static void 721 gffb_make_room(struct gffb_softc *sc, int size) 722 { 723 uint32_t get; 724 725 size = (size + 1) << 2; /* slots -> offset */ 726 727 while (sc->sc_free < size) { 728 get = GFFB_READ_4(GFFB_FIFO_GET); 729 730 if (sc->sc_put >= get) { 731 sc->sc_free = 0x2000 - sc->sc_current; 732 if (sc->sc_free < size) { 733 gffb_dmanext(sc, 0x20000000); 734 if(get <= (SKIPS << 2)) { 735 if (sc->sc_put <= (SKIPS << 2)) { 736 /* corner case - will be idle */ 737 GFFB_WRITE_4(GFFB_FIFO_PUT, 738 (SKIPS + 1) << 2); 739 } 740 do { 741 get =GFFB_READ_4(GFFB_FIFO_GET); 742 } while (get <= (SKIPS << 2)); 743 } 744 GFFB_WRITE_4(GFFB_FIFO_PUT, SKIPS << 2); 745 sc->sc_current = sc->sc_put = (SKIPS << 2); 746 sc->sc_free = get - ((SKIPS + 1) << 2); 747 } 748 } else 749 sc->sc_free = get - sc->sc_current - 4; 750 } 751 } 752 753 static void 754 gffb_sync(struct gffb_softc *sc) 755 { 756 int bail; 757 int i; 758 759 /* 760 * if there are commands in the buffer make sure the chip is actually 761 * trying to run them 762 */ 763 gffb_dma_kickoff(sc); 764 765 /* now wait for the command buffer to drain... */ 766 bail = 100000000; 767 while ((GFFB_READ_4(GFFB_FIFO_GET) != sc->sc_put) && (bail > 0)) { 768 bail--; 769 } 770 if (bail == 0) goto crap; 771 772 /* ... and for the engine to go idle */ 773 bail = 100000000; 774 while((GFFB_READ_4(GFFB_BUSY) != 0) && (bail > 0)) { 775 bail--; 776 } 777 if (bail == 0) goto crap; 778 return; 779 crap: 780 /* if we time out fill the buffer with NOPs and cross fingers */ 781 sc->sc_put = 0; 782 sc->sc_current = 0; 783 for (i = 0; i < 0x2000; i += 4) 784 bus_space_write_stream_4(sc->sc_memt, sc->sc_fbh, i, 0); 785 aprint_error_dev(sc->sc_dev, "DMA lockup\n"); 786 } 787 788 static void 789 gffb_init(struct gffb_softc *sc) 790 { 791 int i; 792 uint32_t foo; 793 794 if (!sc->sc_accel) return; 795 796 sc->sc_fboffset = 0x2000; 797 798 /* init display start */ 799 GFFB_WRITE_4(GFFB_CRTC0 + GFFB_DISPLAYSTART, sc->sc_fboffset); 800 GFFB_WRITE_4(GFFB_CRTC1 + GFFB_DISPLAYSTART, sc->sc_fboffset); 801 GFFB_WRITE_4(GFFB_PDIO0 + GFFB_PEL_MASK, 0xff); 802 GFFB_WRITE_4(GFFB_PDIO1 + GFFB_PEL_MASK, 0xff); 803 804 /* DMA stuff. A whole lot of magic number voodoo from xf86-video-nv */ 805 GFFB_WRITE_4(GFFB_PMC + 0x140, 0); 806 GFFB_WRITE_4(GFFB_PMC + 0x200, 0xffff00ff); 807 GFFB_WRITE_4(GFFB_PMC + 0x200, 0xffffffff); 808 GFFB_WRITE_4(GFFB_PTIMER + 0x800, 8); 809 GFFB_WRITE_4(GFFB_PTIMER + 0x840, 3); 810 GFFB_WRITE_4(GFFB_PTIMER + 0x500, 0); 811 GFFB_WRITE_4(GFFB_PTIMER + 0x400, 0xffffffff); 812 for (i = 0; i < 8; i++) { 813 GFFB_WRITE_4(GFFB_PMC + 0x240 + (i * 0x10), 0); 814 GFFB_WRITE_4(GFFB_PMC + 0x244 + (i * 0x10), 815 sc->sc_vramsize - 1); 816 } 817 818 for (i = 0; i < 8; i++) { 819 GFFB_WRITE_4(GFFB_PFB + 0x0240 + (i * 0x10), 0); 820 GFFB_WRITE_4(GFFB_PFB + 0x0244 + (i * 0x10), 821 sc->sc_vramsize - 1); 822 } 823 824 GFFB_WRITE_4(GFFB_PRAMIN, 0x80000010); 825 GFFB_WRITE_4(GFFB_PRAMIN + 0x04, 0x80011201); 826 GFFB_WRITE_4(GFFB_PRAMIN + 0x08, 0x80000011); 827 GFFB_WRITE_4(GFFB_PRAMIN + 0x0c, 0x80011202); 828 GFFB_WRITE_4(GFFB_PRAMIN + 0x10, 0x80000012); 829 GFFB_WRITE_4(GFFB_PRAMIN + 0x14, 0x80011203); 830 GFFB_WRITE_4(GFFB_PRAMIN + 0x18, 0x80000013); 831 GFFB_WRITE_4(GFFB_PRAMIN + 0x1c, 0x80011204); 832 GFFB_WRITE_4(GFFB_PRAMIN + 0x20, 0x80000014); 833 GFFB_WRITE_4(GFFB_PRAMIN + 0x24, 0x80011205); 834 GFFB_WRITE_4(GFFB_PRAMIN + 0x28, 0x80000015); 835 GFFB_WRITE_4(GFFB_PRAMIN + 0x2c, 0x80011206); 836 GFFB_WRITE_4(GFFB_PRAMIN + 0x30, 0x80000016); 837 GFFB_WRITE_4(GFFB_PRAMIN + 0x34, 0x80011207); 838 GFFB_WRITE_4(GFFB_PRAMIN + 0x38, 0x80000017); 839 GFFB_WRITE_4(GFFB_PRAMIN + 0x3c, 0x80011208); 840 GFFB_WRITE_4(GFFB_PRAMIN + 0x2000, 0x00003000); 841 GFFB_WRITE_4(GFFB_PRAMIN + 0x2004, sc->sc_vramsize - 1); 842 GFFB_WRITE_4(GFFB_PRAMIN + 0x2008, 0x00000002); 843 GFFB_WRITE_4(GFFB_PRAMIN + 0x200c, 0x00000002); 844 GFFB_WRITE_4(GFFB_PRAMIN + 0x2010, 0x01008042); /* different for nv40 */ 845 GFFB_WRITE_4(GFFB_PRAMIN + 0x2014, 0); 846 GFFB_WRITE_4(GFFB_PRAMIN + 0x2018, 0x12001200); 847 GFFB_WRITE_4(GFFB_PRAMIN + 0x201c, 0); 848 GFFB_WRITE_4(GFFB_PRAMIN + 0x2020, 0x01008043); 849 GFFB_WRITE_4(GFFB_PRAMIN + 0x2024, 0); 850 GFFB_WRITE_4(GFFB_PRAMIN + 0x2028, 0); 851 GFFB_WRITE_4(GFFB_PRAMIN + 0x202c, 0); 852 GFFB_WRITE_4(GFFB_PRAMIN + 0x2030, 0x01008044); 853 GFFB_WRITE_4(GFFB_PRAMIN + 0x2034, 0x00000002); 854 GFFB_WRITE_4(GFFB_PRAMIN + 0x2038, 0); 855 GFFB_WRITE_4(GFFB_PRAMIN + 0x203c, 0); 856 GFFB_WRITE_4(GFFB_PRAMIN + 0x2040, 0x01008019); 857 GFFB_WRITE_4(GFFB_PRAMIN + 0x2044, 0); 858 GFFB_WRITE_4(GFFB_PRAMIN + 0x2048, 0); 859 GFFB_WRITE_4(GFFB_PRAMIN + 0x204c, 0); 860 GFFB_WRITE_4(GFFB_PRAMIN + 0x2050, 0x0100a05c); 861 GFFB_WRITE_4(GFFB_PRAMIN + 0x2054, 0); 862 GFFB_WRITE_4(GFFB_PRAMIN + 0x2058, 0); 863 GFFB_WRITE_4(GFFB_PRAMIN + 0x205c, 0); 864 /* XXX 0x0100805f if !WaitVSynvPossible */ 865 GFFB_WRITE_4(GFFB_PRAMIN + 0x2060, 0x0100809f); 866 GFFB_WRITE_4(GFFB_PRAMIN + 0x2064, 0); 867 GFFB_WRITE_4(GFFB_PRAMIN + 0x2068, 0x12001200); 868 GFFB_WRITE_4(GFFB_PRAMIN + 0x206c, 0); 869 GFFB_WRITE_4(GFFB_PRAMIN + 0x2070, 0x0100804a); 870 GFFB_WRITE_4(GFFB_PRAMIN + 0x2074, 0x00000002); 871 GFFB_WRITE_4(GFFB_PRAMIN + 0x2078, 0); 872 GFFB_WRITE_4(GFFB_PRAMIN + 0x207c, 0); 873 GFFB_WRITE_4(GFFB_PRAMIN + 0x2080, 0x01018077); 874 GFFB_WRITE_4(GFFB_PRAMIN + 0x2084, 0); 875 GFFB_WRITE_4(GFFB_PRAMIN + 0x2088, 0x12001200); 876 GFFB_WRITE_4(GFFB_PRAMIN + 0x208c, 0); 877 GFFB_WRITE_4(GFFB_PRAMIN + 0x2090, 0x00003002); 878 GFFB_WRITE_4(GFFB_PRAMIN + 0x2094, 0x00007fff); 879 /* command buffer start with some flag in the lower bits */ 880 GFFB_WRITE_4(GFFB_PRAMIN + 0x2098, 0x00000002); 881 GFFB_WRITE_4(GFFB_PRAMIN + 0x209c, 0x00000002); 882 #if BYTE_ORDER == BIG_ENDIAN 883 GFFB_WRITE_4(GFFB_PRAMIN + 0x2010, 0x01088042); 884 GFFB_WRITE_4(GFFB_PRAMIN + 0x2020, 0x01088043); 885 GFFB_WRITE_4(GFFB_PRAMIN + 0x2030, 0x01088044); 886 GFFB_WRITE_4(GFFB_PRAMIN + 0x2040, 0x01088019); 887 GFFB_WRITE_4(GFFB_PRAMIN + 0x2050, 0x0108a05c); 888 GFFB_WRITE_4(GFFB_PRAMIN + 0x2060, 0x0108809f); 889 GFFB_WRITE_4(GFFB_PRAMIN + 0x2070, 0x0108804a); 890 GFFB_WRITE_4(GFFB_PRAMIN + 0x2080, 0x01098077); 891 GFFB_WRITE_4(GFFB_PRAMIN + 0x2034, 0x00000001); 892 GFFB_WRITE_4(GFFB_PRAMIN + 0x2074, 0x00000001); 893 #endif 894 895 /* PGRAPH setup */ 896 GFFB_WRITE_4(GFFB_PFIFO + 0x0500, 0); 897 GFFB_WRITE_4(GFFB_PFIFO + 0x0504, 0x00000001); 898 GFFB_WRITE_4(GFFB_PFIFO + 0x1200, 0); 899 GFFB_WRITE_4(GFFB_PFIFO + 0x1250, 0); 900 GFFB_WRITE_4(GFFB_PFIFO + 0x1204, 0x00000100); /* different on nv40 */ 901 GFFB_WRITE_4(GFFB_PFIFO + 0x1240, 0); 902 GFFB_WRITE_4(GFFB_PFIFO + 0x1244, 0); 903 GFFB_WRITE_4(GFFB_PFIFO + 0x122c, 0x00001209); /* different on nv40 */ 904 GFFB_WRITE_4(GFFB_PFIFO + 0x1000, 0); 905 GFFB_WRITE_4(GFFB_PFIFO + 0x1050, 0); 906 GFFB_WRITE_4(GFFB_PFIFO + 0x0210, 0x03000100); 907 GFFB_WRITE_4(GFFB_PFIFO + 0x0214, 0x00000110); 908 GFFB_WRITE_4(GFFB_PFIFO + 0x0218, 0x00000112); 909 GFFB_WRITE_4(GFFB_PFIFO + 0x050c, 0x0000ffff); 910 GFFB_WRITE_4(GFFB_PFIFO + 0x1258, 0x0000ffff); 911 GFFB_WRITE_4(GFFB_PFIFO + 0x0140, 0); 912 GFFB_WRITE_4(GFFB_PFIFO + 0x0100, 0xffffffff); 913 GFFB_WRITE_4(GFFB_PFIFO + 0x1054, 0x00000001); 914 GFFB_WRITE_4(GFFB_PFIFO + 0x1230, 0); 915 GFFB_WRITE_4(GFFB_PFIFO + 0x1280, 0); 916 #if BYTE_ORDER == BIG_ENDIAN 917 GFFB_WRITE_4(GFFB_PFIFO + 0x1224, 0x800f0078); 918 #else 919 GFFB_WRITE_4(GFFB_PFIFO + 0x1224, 0x000f0078); 920 #endif 921 GFFB_WRITE_4(GFFB_PFIFO + 0x1220, 0x00000001); 922 GFFB_WRITE_4(GFFB_PFIFO + 0x1200, 0x00000001); 923 GFFB_WRITE_4(GFFB_PFIFO + 0x1250, 0x00000001); 924 GFFB_WRITE_4(GFFB_PFIFO + 0x1254, 0x00000001); 925 GFFB_WRITE_4(GFFB_PFIFO + 0x0500, 0x00000001); 926 927 GFFB_WRITE_4(GFFB_PGRAPH + 0x0080, 0xFFFFFFFF); 928 GFFB_WRITE_4(GFFB_PGRAPH + 0x0080, 0x00000000); 929 930 GFFB_WRITE_4(GFFB_PGRAPH + 0x0140, 0x00000000); 931 GFFB_WRITE_4(GFFB_PGRAPH + 0x0100, 0xFFFFFFFF); 932 GFFB_WRITE_4(GFFB_PGRAPH + 0x0144, 0x10010100); 933 GFFB_WRITE_4(GFFB_PGRAPH + 0x0714, 0xFFFFFFFF); 934 GFFB_WRITE_4(GFFB_PGRAPH + 0x0720, 0x00000001); 935 /* 936 * xf86_video_nv does this in two writes, 937 * not sure if they can be combined 938 */ 939 foo = GFFB_READ_4(GFFB_PGRAPH + 0x0710); 940 GFFB_WRITE_4(GFFB_PGRAPH + 0x0710, foo & 0x0007ff00); 941 foo = GFFB_READ_4(GFFB_PGRAPH + 0x0710); 942 GFFB_WRITE_4(GFFB_PGRAPH + 0x0710, foo | 0x00020100); 943 944 /* NV_ARCH_10 */ 945 GFFB_WRITE_4(GFFB_PGRAPH + 0x0084, 0x00118700); 946 GFFB_WRITE_4(GFFB_PGRAPH + 0x0088, 0x24E00810); 947 GFFB_WRITE_4(GFFB_PGRAPH + 0x008C, 0x55DE0030); 948 949 for(i = 0; i < 128; i += 4) { 950 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B00 + i, 951 GFFB_READ_4(GFFB_PFB + 0x0240 + i)); 952 } 953 954 GFFB_WRITE_4(GFFB_PGRAPH + 0x640, 0); 955 GFFB_WRITE_4(GFFB_PGRAPH + 0x644, 0); 956 GFFB_WRITE_4(GFFB_PGRAPH + 0x684, sc->sc_vramsize - 1); 957 GFFB_WRITE_4(GFFB_PGRAPH + 0x688, sc->sc_vramsize - 1); 958 959 GFFB_WRITE_4(GFFB_PGRAPH + 0x0810, 0x00000000); 960 GFFB_WRITE_4(GFFB_PGRAPH + 0x0608, 0xFFFFFFFF); 961 962 GFFB_WRITE_4(GFFB_PGRAPH + 0x053C, 0); 963 GFFB_WRITE_4(GFFB_PGRAPH + 0x0540, 0); 964 GFFB_WRITE_4(GFFB_PGRAPH + 0x0544, 0x00007FFF); 965 GFFB_WRITE_4(GFFB_PGRAPH + 0x0548, 0x00007FFF); 966 967 GFFB_WRITE_4(GFFB_CMDSTART, 0x00000002); 968 GFFB_WRITE_4(GFFB_FIFO_GET, 0); 969 sc->sc_put = 0; 970 sc->sc_current = 0; 971 sc->sc_free = 0x2000; 972 973 for(i = 0; i < SKIPS; i++) 974 gffb_dmanext(sc, 0); 975 976 gffb_dmanext(sc, 0x00040000); 977 gffb_dmanext(sc, 0x80000010); 978 gffb_dmanext(sc, 0x00042000); 979 gffb_dmanext(sc, 0x80000011); 980 gffb_dmanext(sc, 0x00044000); 981 gffb_dmanext(sc, 0x80000012); 982 gffb_dmanext(sc, 0x00046000); 983 gffb_dmanext(sc, 0x80000013); 984 gffb_dmanext(sc, 0x00048000); 985 gffb_dmanext(sc, 0x80000014); 986 gffb_dmanext(sc, 0x0004A000); 987 gffb_dmanext(sc, 0x80000015); 988 gffb_dmanext(sc, 0x0004C000); 989 gffb_dmanext(sc, 0x80000016); 990 gffb_dmanext(sc, 0x0004E000); 991 gffb_dmanext(sc, 0x80000017); 992 sc->sc_free = 0x2000 - sc->sc_current; 993 994 gffb_dmastart(sc, SURFACE_FORMAT, 4); 995 gffb_dmanext(sc, SURFACE_FORMAT_DEPTH8); 996 gffb_dmanext(sc, sc->sc_stride | (sc->sc_stride << 16)); 997 gffb_dmanext(sc, 0x2000); /* src offset */ 998 gffb_dmanext(sc, 0x2000); /* dst offset */ 999 1000 gffb_dmastart(sc, RECT_FORMAT, 1); 1001 gffb_dmanext(sc, RECT_FORMAT_DEPTH8); 1002 1003 gffb_dmastart(sc, PATTERN_FORMAT, 1); 1004 gffb_dmanext(sc, PATTERN_FORMAT_DEPTH8); 1005 1006 gffb_dmastart(sc, PATTERN_COLOR_0, 4); 1007 gffb_dmanext(sc, 0xffffffff); 1008 gffb_dmanext(sc, 0xffffffff); 1009 gffb_dmanext(sc, 0xffffffff); 1010 gffb_dmanext(sc, 0xffffffff); 1011 1012 gffb_dmastart(sc, ROP_SET, 1); 1013 gffb_dmanext(sc, 0xcc); 1014 sc->sc_rop = 0xcc; 1015 1016 gffb_dma_kickoff(sc); 1017 gffb_sync(sc); 1018 DPRINTF("put %x current %x\n", sc->sc_put, sc->sc_current); 1019 1020 } 1021 1022 static void 1023 gffb_rop(struct gffb_softc *sc, int rop) 1024 { 1025 if (rop == sc->sc_rop) 1026 return; 1027 sc->sc_rop = rop; 1028 gffb_dmastart(sc, ROP_SET, 1); 1029 gffb_dmanext(sc, rop); 1030 } 1031 1032 static void 1033 gffb_rectfill(struct gffb_softc *sc, int x, int y, int wi, int he, 1034 uint32_t colour) 1035 { 1036 if (!sc->sc_accel) return; 1037 mutex_enter(&sc->sc_lock); 1038 gffb_rop(sc, 0xcc); 1039 1040 gffb_dmastart(sc, RECT_SOLID_COLOR, 1); 1041 gffb_dmanext(sc, colour); 1042 1043 gffb_dmastart(sc, RECT_SOLID_RECTS(0), 2); 1044 gffb_dmanext(sc, (x << 16) | y); 1045 gffb_dmanext(sc, (wi << 16) | he); 1046 gffb_dma_kickoff(sc); 1047 mutex_exit(&sc->sc_lock); 1048 } 1049 1050 static void 1051 gffb_bitblt(void *cookie, int xs, int ys, int xd, int yd, 1052 int wi, int he, int rop) 1053 { 1054 struct gffb_softc *sc = cookie; 1055 1056 if (!sc->sc_accel) return; 1057 mutex_enter(&sc->sc_lock); 1058 1059 gffb_rop(sc, rop); 1060 1061 gffb_dmastart(sc, BLIT_POINT_SRC, 3); 1062 gffb_dmanext(sc, (ys << 16) | xs); 1063 gffb_dmanext(sc, (yd << 16) | xd); 1064 gffb_dmanext(sc, (he << 16) | wi); 1065 gffb_dma_kickoff(sc); 1066 mutex_exit(&sc->sc_lock); 1067 } 1068 1069 static void 1070 gffb_cursor(void *cookie, int on, int row, int col) 1071 { 1072 struct rasops_info *ri = cookie; 1073 struct vcons_screen *scr = ri->ri_hw; 1074 struct gffb_softc *sc = scr->scr_cookie; 1075 int x, y, wi, he; 1076 1077 wi = ri->ri_font->fontwidth; 1078 he = ri->ri_font->fontheight; 1079 1080 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1081 x = ri->ri_ccol * wi + ri->ri_xorigin; 1082 y = ri->ri_crow * he + ri->ri_yorigin; 1083 if (ri->ri_flg & RI_CURSOR) { 1084 gffb_bitblt(sc, x, y, x, y, wi, he, 0x33); 1085 ri->ri_flg &= ~RI_CURSOR; 1086 } 1087 ri->ri_crow = row; 1088 ri->ri_ccol = col; 1089 if (on) { 1090 x = ri->ri_ccol * wi + ri->ri_xorigin; 1091 y = ri->ri_crow * he + ri->ri_yorigin; 1092 gffb_bitblt(sc, x, y, x, y, wi, he, 0x33); 1093 ri->ri_flg |= RI_CURSOR; 1094 } 1095 } else { 1096 scr->scr_ri.ri_crow = row; 1097 scr->scr_ri.ri_ccol = col; 1098 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1099 } 1100 1101 } 1102 1103 static void 1104 gffb_putchar(void *cookie, int row, int col, u_int c, long attr) 1105 { 1106 struct rasops_info *ri = cookie; 1107 struct wsdisplay_font *font = PICK_FONT(ri, c); 1108 struct vcons_screen *scr = ri->ri_hw; 1109 struct gffb_softc *sc = scr->scr_cookie; 1110 int x, y, wi, he, rv = GC_NOPE; 1111 uint32_t bg; 1112 1113 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1114 return; 1115 1116 if (!CHAR_IN_FONT(c, font)) 1117 return; 1118 1119 wi = font->fontwidth; 1120 he = font->fontheight; 1121 1122 x = ri->ri_xorigin + col * wi; 1123 y = ri->ri_yorigin + row * he; 1124 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1125 1126 if (c == 0x20) { 1127 gffb_rectfill(sc, x, y, wi, he, bg); 1128 return; 1129 } 1130 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1131 if (rv == GC_OK) 1132 return; 1133 1134 mutex_enter(&sc->sc_lock); 1135 gffb_sync(sc); 1136 sc->sc_putchar(cookie, row, col, c, attr); 1137 membar_sync(); 1138 mutex_exit(&sc->sc_lock); 1139 1140 if (rv == GC_ADD) { 1141 glyphcache_add(&sc->sc_gc, c, x, y); 1142 } 1143 } 1144 1145 static void 1146 gffb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1147 { 1148 struct rasops_info *ri = cookie; 1149 struct vcons_screen *scr = ri->ri_hw; 1150 struct gffb_softc *sc = scr->scr_cookie; 1151 int32_t xs, xd, y, width, height; 1152 1153 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1154 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1155 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1156 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1157 width = ri->ri_font->fontwidth * ncols; 1158 height = ri->ri_font->fontheight; 1159 gffb_bitblt(sc, xs, y, xd, y, width, height, 0xcc); 1160 } 1161 } 1162 1163 static void 1164 gffb_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1165 { 1166 struct rasops_info *ri = cookie; 1167 struct vcons_screen *scr = ri->ri_hw; 1168 struct gffb_softc *sc = scr->scr_cookie; 1169 int32_t x, y, width, height, fg, bg, ul; 1170 1171 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1172 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1173 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1174 width = ri->ri_font->fontwidth * ncols; 1175 height = ri->ri_font->fontheight; 1176 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1177 1178 gffb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1179 } 1180 } 1181 1182 static void 1183 gffb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1184 { 1185 struct rasops_info *ri = cookie; 1186 struct vcons_screen *scr = ri->ri_hw; 1187 struct gffb_softc *sc = scr->scr_cookie; 1188 int32_t x, ys, yd, width, height; 1189 1190 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1191 x = ri->ri_xorigin; 1192 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1193 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1194 width = ri->ri_emuwidth; 1195 height = ri->ri_font->fontheight * nrows; 1196 gffb_bitblt(sc, x, ys, x, yd, width, height, 0xcc); 1197 } 1198 } 1199 1200 static void 1201 gffb_eraserows(void *cookie, int row, int nrows, long fillattr) 1202 { 1203 struct rasops_info *ri = cookie; 1204 struct vcons_screen *scr = ri->ri_hw; 1205 struct gffb_softc *sc = scr->scr_cookie; 1206 int32_t x, y, width, height, fg, bg, ul; 1207 1208 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1209 x = ri->ri_xorigin; 1210 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1211 width = ri->ri_emuwidth; 1212 height = ri->ri_font->fontheight * nrows; 1213 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1214 1215 gffb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1216 } 1217 } 1218
Indexes created Mon Sep 29 21:09:56 GMT 2025