gffb.c revision 1.25
1 /* $NetBSD: gffb.c,v 1.25 2025/08/29 09:51:08 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * A console driver for nvidia geforce graphics controllers 30 * tested on macppc only so far, should work on other hardware as long as 31 * something sets up a usable graphics mode and sets the right device properties 32 * This driver should work with all NV1x hardware but so far it's been tested 33 * only on NV11 / GeForce2 MX. Needs testing with more hardware and if 34 * successful, PCI IDs need to be added to gffb_match() 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: gffb.c,v 1.25 2025/08/29 09:51:08 macallan Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/lwp.h> 45 #include <sys/kauth.h> 46 #include <sys/atomic.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcidevs.h> 51 #include <dev/pci/pciio.h> 52 #include <dev/pci/gffbreg.h> 53 54 #include <dev/wscons/wsdisplayvar.h> 55 #include <dev/wscons/wsconsio.h> 56 #include <dev/wsfont/wsfont.h> 57 #include <dev/rasops/rasops.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 #include <dev/pci/wsdisplay_pci.h> 60 #include <dev/wscons/wsdisplay_glyphcachevar.h> 61 62 #include "opt_gffb.h" 63 #include "opt_vcons.h" 64 65 #ifdef GFFB_DEBUG 66 #define DPRINTF printf 67 #else 68 #define DPRINTF while(0) printf 69 #endif 70 71 struct gffb_softc { 72 device_t sc_dev; 73 74 pci_chipset_tag_t sc_pc; 75 pcitag_t sc_pcitag; 76 77 bus_space_tag_t sc_memt; 78 bus_space_tag_t sc_iot; 79 80 bus_space_handle_t sc_regh, sc_fbh; 81 bus_addr_t sc_fb, sc_reg; 82 bus_size_t sc_fbsize, sc_regsize; 83 uint8_t *sc_fbaddr; 84 size_t sc_vramsize; 85 uint32_t sc_fboffset; 86 87 int sc_width, sc_height, sc_depth, sc_stride; 88 int sc_locked, sc_accel; 89 struct vcons_screen sc_console_screen; 90 struct wsscreen_descr sc_defaultscreen_descr; 91 const struct wsscreen_descr *sc_screens[1]; 92 struct wsscreen_list sc_screenlist; 93 struct vcons_data vd; 94 int sc_mode, sc_arch; 95 u_char sc_cmap_red[256]; 96 u_char sc_cmap_green[256]; 97 u_char sc_cmap_blue[256]; 98 int sc_put, sc_current, sc_free; 99 uint32_t sc_rop; 100 void (*sc_putchar)(void *, int, int, u_int, long); 101 kmutex_t sc_lock; 102 glyphcache sc_gc; 103 }; 104 105 static int gffb_match(device_t, cfdata_t, void *); 106 static void gffb_attach(device_t, device_t, void *); 107 108 CFATTACH_DECL_NEW(gffb, sizeof(struct gffb_softc), 109 gffb_match, gffb_attach, NULL, NULL); 110 111 static int gffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 112 static paddr_t gffb_mmap(void *, void *, off_t, int); 113 static void gffb_init_screen(void *, struct vcons_screen *, int, long *); 114 115 static int gffb_putcmap(struct gffb_softc *, struct wsdisplay_cmap *); 116 static int gffb_getcmap(struct gffb_softc *, struct wsdisplay_cmap *); 117 static void gffb_restore_palette(struct gffb_softc *); 118 static int gffb_putpalreg(struct gffb_softc *, uint8_t, uint8_t, 119 uint8_t, uint8_t); 120 121 void gffb_init(struct gffb_softc *); 122 123 static void gffb_make_room(struct gffb_softc *, int); 124 static void gffb_sync(struct gffb_softc *); 125 126 static void gffb_rectfill(struct gffb_softc *, int, int, int, int, 127 uint32_t); 128 static void gffb_bitblt(void *, int, int, int, int, int, int, int); 129 static void gffb_rop(struct gffb_softc *, int); 130 131 static void gffb_cursor(void *, int, int, int); 132 static void gffb_putchar(void *, int, int, u_int, long); 133 static void gffb_copycols(void *, int, int, int, int); 134 static void gffb_erasecols(void *, int, int, int, long); 135 static void gffb_copyrows(void *, int, int, int); 136 static void gffb_eraserows(void *, int, int, long); 137 138 #define GFFB_READ_4(o) bus_space_read_stream_4(sc->sc_memt, sc->sc_regh, (o)) 139 #define GFFB_WRITE_4(o, v) bus_space_write_stream_4(sc->sc_memt, sc->sc_regh, (o), (v)) 140 141 struct wsdisplay_accessops gffb_accessops = { 142 gffb_ioctl, 143 gffb_mmap, 144 NULL, /* alloc_screen */ 145 NULL, /* free_screen */ 146 NULL, /* show_screen */ 147 NULL, /* load_font */ 148 NULL, /* pollc */ 149 NULL /* scroll */ 150 }; 151 152 static int 153 gffb_match(device_t parent, cfdata_t match, void *aux) 154 { 155 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 156 157 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 158 return 0; 159 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_NVIDIA) 160 return 0; 161 162 /* only cards tested on so far - likely needs a list */ 163 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GEFORCE2MX) 164 return 100; 165 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GEFORCE_6800U) 166 return 100; 167 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GF_FXGO5200) 168 return 100; 169 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GF_FX5200U) 170 return 100; 171 return (0); 172 } 173 174 static void 175 gffb_attach(device_t parent, device_t self, void *aux) 176 { 177 struct gffb_softc *sc = device_private(self); 178 struct pci_attach_args *pa = aux; 179 struct rasops_info *ri; 180 bus_space_tag_t tag; 181 struct wsemuldisplaydev_attach_args aa; 182 prop_dictionary_t dict; 183 unsigned long defattr; 184 pcireg_t reg; 185 bool is_console = FALSE; 186 uint32_t addr; 187 int i, j, f; 188 uint8_t cmap[768]; 189 190 sc->sc_pc = pa->pa_pc; 191 sc->sc_pcitag = pa->pa_tag; 192 sc->sc_memt = pa->pa_memt; 193 sc->sc_iot = pa->pa_iot; 194 sc->sc_dev = self; 195 196 /* first, see what kind of chip we've got */ 197 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_ID_REG); 198 switch (PCI_PRODUCT(reg)) { 199 case PCI_PRODUCT_NVIDIA_GEFORCE2MX: 200 sc->sc_accel = true; 201 sc->sc_arch = 10; 202 break; 203 case PCI_PRODUCT_NVIDIA_GEFORCE_6800U: 204 sc->sc_accel = false; 205 sc->sc_arch = 40; 206 break; 207 case PCI_PRODUCT_NVIDIA_GF_FXGO5200: 208 case PCI_PRODUCT_NVIDIA_GF_FX5200U: 209 sc->sc_accel = true; 210 sc->sc_arch = 30; 211 break; 212 default: 213 sc->sc_accel = false; 214 sc->sc_arch = 0; 215 } 216 217 pci_aprint_devinfo(pa, NULL); 218 DPRINTF("%s accel %d arch %d\n", __func__, sc->sc_accel, sc->sc_arch); 219 /* fill in parameters from properties */ 220 dict = device_properties(self); 221 if (!prop_dictionary_get_uint32(dict, "width", &sc->sc_width)) { 222 aprint_error("%s: no width property\n", device_xname(self)); 223 return; 224 } 225 if (!prop_dictionary_get_uint32(dict, "height", &sc->sc_height)) { 226 aprint_error("%s: no height property\n", device_xname(self)); 227 return; 228 } 229 230 #ifdef GLYPHCACHE_DEBUG 231 /* leave some visible VRAM unused so we can see the glyph cache */ 232 sc->sc_height -= 300; 233 #endif 234 235 if (!prop_dictionary_get_uint32(dict, "depth", &sc->sc_depth)) { 236 aprint_error("%s: no depth property\n", device_xname(self)); 237 return; 238 } 239 if (!prop_dictionary_get_uint32(dict, "linebytes", &sc->sc_stride)) { 240 aprint_error("%s: no linebytes property\n", 241 device_xname(self)); 242 return; 243 } 244 245 /* 246 * on !2MX we need to use the firmware's offset - for some reason 247 * register writes to anything other than the DACs go wrong 248 */ 249 sc->sc_fboffset = 0; 250 if (prop_dictionary_get_uint32(dict, "address", &addr)) { 251 sc->sc_fboffset = addr & 0x000fffff; /* XXX */ 252 } 253 DPRINTF("%s: fboffset %8x\n", __func__, sc->sc_fboffset); 254 prop_dictionary_get_bool(dict, "is_console", &is_console); 255 256 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_MEM, 0, 257 &tag, &sc->sc_regh, &sc->sc_reg, &sc->sc_regsize)) { 258 aprint_error("%s: failed to map registers.\n", 259 device_xname(sc->sc_dev)); 260 } 261 /* 262 * first thing we need to make sure register access uses host byte order 263 * so we can recycle as much of xf86-video-nv as possible 264 */ 265 #if BYTE_ORDER == BIG_ENDIAN 266 uint32_t mreg = GFFB_READ_4(GFFB_PMC + 4); 267 if ((mreg & 0x01000001) == 0) { 268 GFFB_WRITE_4(GFFB_PMC + 4, 0x01000001); 269 } 270 #endif 271 sc->sc_vramsize = GFFB_READ_4(GFFB_VRAM) & 0xfff00000; 272 273 /* don't map more VRAM than we actually have */ 274 if (pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, 275 0x14, PCI_MAPREG_TYPE_MEM, &sc->sc_fb, &sc->sc_fbsize, &f)) { 276 aprint_error("%s: can't find the framebuffer?!\n", 277 device_xname(sc->sc_dev)); 278 } 279 if (sc->sc_vramsize == 0) sc->sc_vramsize = sc->sc_fbsize; 280 281 /* don't map (much) more than we actually need */ 282 if (bus_space_map(sc->sc_memt, sc->sc_fb, 0x1000000, 283 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, 284 &sc->sc_fbh)) { 285 aprint_error("%s: failed to map the framebuffer.\n", 286 device_xname(sc->sc_dev)); 287 } 288 sc->sc_fbaddr = bus_space_vaddr(tag, sc->sc_fbh); 289 290 aprint_normal("%s: %d MB aperture at 0x%08x\n", device_xname(self), 291 (int)(sc->sc_fbsize >> 20), (uint32_t)sc->sc_fb); 292 aprint_normal_dev(sc->sc_dev, "%d MB video memory\n", 293 (int)(sc->sc_vramsize >> 20)); 294 295 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 296 "default", 297 0, 0, 298 NULL, 299 8, 16, 300 WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_RESIZE, 301 NULL 302 }; 303 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 304 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 305 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 306 sc->sc_locked = 0; 307 308 #ifdef GFFB_DEBUG 309 printf("put: %08x\n", GFFB_READ_4(GFFB_FIFO_PUT)); 310 printf("get: %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 311 #endif 312 313 /* 314 * we don't have hardware synchronization so we need a lock to serialize 315 * access to the DMA buffer between normal and kernel output 316 * actually it might be enough to use atomic ops on sc_current, sc_free 317 * etc. but for now we'll play it safe 318 * XXX we will probably deadlock if we take an interrupt while sc_lock 319 * is held and then try to printf() 320 */ 321 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 322 323 /* init engine here */ 324 gffb_init(sc); 325 326 #ifdef GFFB_DEBUG 327 printf("put: %08x\n", GFFB_READ_4(GFFB_FIFO_PUT)); 328 printf("get: %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 329 #endif 330 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 331 &gffb_accessops); 332 sc->vd.init_screen = gffb_init_screen; 333 334 335 ri = &sc->sc_console_screen.scr_ri; 336 337 if (sc->sc_accel) { 338 sc->sc_gc.gc_bitblt = gffb_bitblt; 339 sc->sc_gc.gc_blitcookie = sc; 340 sc->sc_gc.gc_rop = 0xcc; 341 sc->vd.show_screen_cookie = &sc->sc_gc; 342 sc->vd.show_screen_cb = glyphcache_adapt; 343 } 344 345 if (is_console) { 346 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 347 &defattr); 348 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 349 350 if (sc->sc_accel) { 351 gffb_rectfill(sc, 0, 0, sc->sc_width, sc->sc_height, 352 ri->ri_devcmap[(defattr >> 16) & 0xf]); 353 } else { 354 memset(sc->sc_fbaddr + sc->sc_fboffset, 355 ri->ri_devcmap[(defattr >> 16) & 0xf], 356 sc->sc_stride * sc->sc_height); 357 } 358 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 359 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 360 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 361 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 362 363 if (sc->sc_accel) 364 glyphcache_init(&sc->sc_gc, sc->sc_height + 5, 365 (0x800000 / sc->sc_stride) - sc->sc_height - 5, 366 sc->sc_width, 367 ri->ri_font->fontwidth, 368 ri->ri_font->fontheight, 369 defattr); 370 371 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 372 defattr); 373 vcons_replay_msgbuf(&sc->sc_console_screen); 374 } else { 375 /* 376 * since we're not the console we can postpone the rest 377 * until someone actually allocates a screen for us 378 */ 379 if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 380 /* do some minimal setup to avoid weirdnesses later */ 381 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 382 &defattr); 383 } else 384 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 385 386 if (sc->sc_accel) 387 glyphcache_init(&sc->sc_gc, sc->sc_height + 5, 388 (0x800000 / sc->sc_stride) - sc->sc_height - 5, 389 sc->sc_width, 390 ri->ri_font->fontwidth, 391 ri->ri_font->fontheight, 392 defattr); 393 } 394 395 j = 0; 396 rasops_get_cmap(ri, cmap, sizeof(cmap)); 397 for (i = 0; i < 256; i++) { 398 sc->sc_cmap_red[i] = cmap[j]; 399 sc->sc_cmap_green[i] = cmap[j + 1]; 400 sc->sc_cmap_blue[i] = cmap[j + 2]; 401 gffb_putpalreg(sc, i, cmap[j], cmap[j + 1], cmap[j + 2]); 402 j += 3; 403 } 404 405 /* no suspend/resume support yet */ 406 if (!pmf_device_register(sc->sc_dev, NULL, NULL)) 407 aprint_error_dev(sc->sc_dev, 408 "couldn't establish power handler\n"); 409 410 aa.console = is_console; 411 aa.scrdata = &sc->sc_screenlist; 412 aa.accessops = &gffb_accessops; 413 aa.accesscookie = &sc->vd; 414 415 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint, CFARGS_NONE); 416 } 417 418 static int 419 gffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 420 { 421 struct vcons_data *vd = v; 422 struct gffb_softc *sc = vd->cookie; 423 struct wsdisplay_fbinfo *wdf; 424 struct vcons_screen *ms = vd->active; 425 426 switch (cmd) { 427 case WSDISPLAYIO_GTYPE: 428 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 429 return 0; 430 431 /* PCI config read/write passthrough. */ 432 case PCI_IOC_CFGREAD: 433 case PCI_IOC_CFGWRITE: 434 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 435 cmd, data, flag, l); 436 437 case WSDISPLAYIO_GET_BUSID: 438 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 439 sc->sc_pcitag, data); 440 441 case WSDISPLAYIO_GINFO: 442 if (ms == NULL) 443 return ENODEV; 444 wdf = (void *)data; 445 wdf->height = ms->scr_ri.ri_height; 446 wdf->width = ms->scr_ri.ri_width; 447 wdf->depth = ms->scr_ri.ri_depth; 448 wdf->cmsize = 256; 449 return 0; 450 451 case WSDISPLAYIO_GETCMAP: 452 return gffb_getcmap(sc, 453 (struct wsdisplay_cmap *)data); 454 455 case WSDISPLAYIO_PUTCMAP: 456 return gffb_putcmap(sc, 457 (struct wsdisplay_cmap *)data); 458 459 case WSDISPLAYIO_LINEBYTES: 460 *(u_int *)data = sc->sc_stride; 461 return 0; 462 463 case WSDISPLAYIO_SMODE: { 464 int new_mode = *(int*)data; 465 if (new_mode != sc->sc_mode) { 466 sc->sc_mode = new_mode; 467 if(new_mode == WSDISPLAYIO_MODE_EMUL) { 468 gffb_init(sc); 469 gffb_restore_palette(sc); 470 if (sc->sc_accel) { 471 glyphcache_wipe(&sc->sc_gc); 472 gffb_rectfill(sc, 0, 0, sc->sc_width, 473 sc->sc_height, ms->scr_ri.ri_devcmap[ 474 (ms->scr_defattr >> 16) & 0xf]); 475 } else { 476 memset(sc->sc_fbaddr + sc->sc_fboffset, 477 ms->scr_ri.ri_devcmap[ 478 (ms->scr_defattr >> 16) & 0xf], 479 sc->sc_stride * sc->sc_height); 480 } 481 vcons_redraw_screen(ms); 482 } 483 } 484 } 485 return 0; 486 487 case WSDISPLAYIO_GET_EDID: { 488 struct wsdisplayio_edid_info *d = data; 489 return wsdisplayio_get_edid(sc->sc_dev, d); 490 } 491 492 case WSDISPLAYIO_GET_FBINFO: { 493 struct wsdisplayio_fbinfo *fbi = data; 494 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 495 } 496 } 497 return EPASSTHROUGH; 498 } 499 500 static paddr_t 501 gffb_mmap(void *v, void *vs, off_t offset, int prot) 502 { 503 struct vcons_data *vd = v; 504 struct gffb_softc *sc = vd->cookie; 505 paddr_t pa; 506 507 /* 'regular' framebuffer mmap()ing */ 508 if (offset < sc->sc_vramsize) { 509 pa = bus_space_mmap(sc->sc_memt, sc->sc_fb + offset + 0x2000, 510 0, prot, BUS_SPACE_MAP_LINEAR); 511 return pa; 512 } 513 514 /* 515 * restrict all other mappings to processes with superuser privileges 516 * or the kernel itself 517 */ 518 if (kauth_authorize_machdep(kauth_cred_get(), 519 KAUTH_MACHDEP_UNMANAGEDMEM, 520 NULL, NULL, NULL, NULL) != 0) { 521 aprint_normal("%s: mmap() rejected.\n", 522 device_xname(sc->sc_dev)); 523 return -1; 524 } 525 526 if ((offset >= sc->sc_fb) && (offset < (sc->sc_fb + sc->sc_fbsize))) { 527 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 528 BUS_SPACE_MAP_LINEAR); 529 return pa; 530 } 531 532 if ((offset >= sc->sc_reg) && 533 (offset < (sc->sc_reg + sc->sc_regsize))) { 534 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 535 BUS_SPACE_MAP_LINEAR); 536 return pa; 537 } 538 539 #ifdef PCI_MAGIC_IO_RANGE 540 /* allow mapping of IO space */ 541 if ((offset >= PCI_MAGIC_IO_RANGE) && 542 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 543 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 544 0, prot, BUS_SPACE_MAP_LINEAR); 545 return pa; 546 } 547 #endif 548 549 return -1; 550 } 551 552 static void 553 gffb_init_screen(void *cookie, struct vcons_screen *scr, 554 int existing, long *defattr) 555 { 556 struct gffb_softc *sc = cookie; 557 struct rasops_info *ri = &scr->scr_ri; 558 559 ri->ri_depth = sc->sc_depth; 560 ri->ri_width = sc->sc_width; 561 ri->ri_height = sc->sc_height; 562 ri->ri_stride = sc->sc_stride; 563 if (sc->sc_depth == 8) 564 ri->ri_bits = sc->sc_fbaddr + sc->sc_fboffset; 565 ri->ri_flg = RI_CENTER; 566 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA; 567 568 rasops_init(ri, 0, 0); 569 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_RESIZE; 570 scr->scr_flags |= VCONS_LOADFONT; 571 572 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 573 sc->sc_width / ri->ri_font->fontwidth); 574 575 ri->ri_hw = scr; 576 577 if (sc->sc_accel) { 578 sc->sc_putchar = ri->ri_ops.putchar; 579 ri->ri_ops.copyrows = gffb_copyrows; 580 ri->ri_ops.copycols = gffb_copycols; 581 ri->ri_ops.eraserows = gffb_eraserows; 582 ri->ri_ops.erasecols = gffb_erasecols; 583 ri->ri_ops.cursor = gffb_cursor; 584 ri->ri_ops.putchar = gffb_putchar; 585 } else { 586 scr->scr_flags |= VCONS_DONT_READ; 587 } 588 } 589 590 static int 591 gffb_putcmap(struct gffb_softc *sc, struct wsdisplay_cmap *cm) 592 { 593 u_char *r, *g, *b; 594 u_int index = cm->index; 595 u_int count = cm->count; 596 int i, error; 597 u_char rbuf[256], gbuf[256], bbuf[256]; 598 599 #ifdef GFFB_DEBUG 600 aprint_debug("putcmap: %d %d\n",index, count); 601 #endif 602 if (cm->index >= 256 || cm->count > 256 || 603 (cm->index + cm->count) > 256) 604 return EINVAL; 605 error = copyin(cm->red, &rbuf[index], count); 606 if (error) 607 return error; 608 error = copyin(cm->green, &gbuf[index], count); 609 if (error) 610 return error; 611 error = copyin(cm->blue, &bbuf[index], count); 612 if (error) 613 return error; 614 615 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 616 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 617 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 618 619 r = &sc->sc_cmap_red[index]; 620 g = &sc->sc_cmap_green[index]; 621 b = &sc->sc_cmap_blue[index]; 622 623 for (i = 0; i < count; i++) { 624 gffb_putpalreg(sc, index, *r, *g, *b); 625 index++; 626 r++, g++, b++; 627 } 628 return 0; 629 } 630 631 static int 632 gffb_getcmap(struct gffb_softc *sc, struct wsdisplay_cmap *cm) 633 { 634 u_int index = cm->index; 635 u_int count = cm->count; 636 int error; 637 638 if (index >= 255 || count > 256 || index + count > 256) 639 return EINVAL; 640 641 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 642 if (error) 643 return error; 644 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 645 if (error) 646 return error; 647 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 648 if (error) 649 return error; 650 651 return 0; 652 } 653 654 static void 655 gffb_restore_palette(struct gffb_softc *sc) 656 { 657 int i; 658 659 for (i = 0; i < (1 << sc->sc_depth); i++) { 660 gffb_putpalreg(sc, i, sc->sc_cmap_red[i], 661 sc->sc_cmap_green[i], sc->sc_cmap_blue[i]); 662 } 663 } 664 665 static int 666 gffb_putpalreg(struct gffb_softc *sc, uint8_t idx, uint8_t r, uint8_t g, 667 uint8_t b) 668 { 669 /* port 0 */ 670 bus_space_write_1(sc->sc_memt, sc->sc_regh, 671 GFFB_PDIO0 + GFFB_PEL_IW, idx); 672 bus_space_write_1(sc->sc_memt, sc->sc_regh, 673 GFFB_PDIO0 + GFFB_PEL_D, r); 674 bus_space_write_1(sc->sc_memt, sc->sc_regh, 675 GFFB_PDIO0 + GFFB_PEL_D, g); 676 bus_space_write_1(sc->sc_memt, sc->sc_regh, 677 GFFB_PDIO0 + GFFB_PEL_D, b); 678 679 /* port 1 */ 680 bus_space_write_1(sc->sc_memt, sc->sc_regh, 681 GFFB_PDIO1 + GFFB_PEL_IW, idx); 682 bus_space_write_1(sc->sc_memt, sc->sc_regh, 683 GFFB_PDIO1 + GFFB_PEL_D, r); 684 bus_space_write_1(sc->sc_memt, sc->sc_regh, 685 GFFB_PDIO1 + GFFB_PEL_D, g); 686 bus_space_write_1(sc->sc_memt, sc->sc_regh, 687 GFFB_PDIO1 + GFFB_PEL_D, b); 688 689 return 0; 690 } 691 692 693 static void 694 gffb_dma_kickoff(struct gffb_softc *sc) 695 { 696 volatile uint32_t junk; 697 if (sc->sc_current != sc->sc_put) { 698 sc->sc_put = sc->sc_current; 699 bus_space_barrier(sc->sc_memt, sc->sc_fbh, 0, 0x1000000, 700 BUS_SPACE_BARRIER_WRITE); 701 junk = *sc->sc_fbaddr; 702 __USE(junk); 703 GFFB_WRITE_4(GFFB_FIFO_PUT, sc->sc_put); 704 bus_space_barrier(sc->sc_memt, sc->sc_regh, GFFB_FIFO_PUT, 4, 705 BUS_SPACE_BARRIER_WRITE); 706 } 707 } 708 709 static void 710 gffb_dmanext(struct gffb_softc *sc, uint32_t data) 711 { 712 bus_space_write_stream_4(sc->sc_memt, sc->sc_fbh, sc->sc_current, data); 713 sc->sc_current += 4; 714 } 715 716 static void 717 gffb_dmastart(struct gffb_softc *sc, uint32_t tag, int size) 718 { 719 if(sc->sc_free <= (size << 2)) 720 gffb_make_room(sc, size); 721 gffb_dmanext(sc, ((size) << 18) | (tag)); 722 sc->sc_free -= ((size + 1) << 2); 723 } 724 725 /* 726 * from xf86_video_nv/nv_xaa.c: 727 * There is a HW race condition with videoram command buffers. 728 * You can't jump to the location of your put offset. We write put 729 * at the jump offset + SKIPS dwords with noop padding in between 730 * to solve this problem 731 */ 732 733 #define SKIPS 8 734 735 static void 736 gffb_make_room(struct gffb_softc *sc, int size) 737 { 738 uint32_t get; 739 740 size = (size + 1) << 2; /* slots -> offset */ 741 742 while (sc->sc_free < size) { 743 get = GFFB_READ_4(GFFB_FIFO_GET); 744 745 if (sc->sc_put >= get) { 746 sc->sc_free = 0x2000 - sc->sc_current; 747 if (sc->sc_free < size) { 748 gffb_dmanext(sc, 0x20000000); 749 if(get <= (SKIPS << 2)) { 750 if (sc->sc_put <= (SKIPS << 2)) { 751 /* corner case - will be idle */ 752 GFFB_WRITE_4(GFFB_FIFO_PUT, 753 (SKIPS + 1) << 2); 754 } 755 do { 756 get =GFFB_READ_4(GFFB_FIFO_GET); 757 } while (get <= (SKIPS << 2)); 758 } 759 GFFB_WRITE_4(GFFB_FIFO_PUT, SKIPS << 2); 760 sc->sc_current = sc->sc_put = (SKIPS << 2); 761 sc->sc_free = get - ((SKIPS + 1) << 2); 762 } 763 } else 764 sc->sc_free = get - sc->sc_current - 4; 765 } 766 } 767 768 static void 769 gffb_sync(struct gffb_softc *sc) 770 { 771 int bail; 772 int i; 773 774 /* 775 * if there are commands in the buffer make sure the chip is actually 776 * trying to run them 777 */ 778 gffb_dma_kickoff(sc); 779 780 /* now wait for the command buffer to drain... */ 781 bail = 100000000; 782 while ((GFFB_READ_4(GFFB_FIFO_GET) != sc->sc_put) && (bail > 0)) { 783 bail--; 784 } 785 if (bail == 0) { 786 printf("FIFO isn't moving\n"); 787 goto crap; 788 } 789 790 /* ... and for the engine to go idle */ 791 bail = 100000000; 792 while((GFFB_READ_4(GFFB_BUSY) != 0) && (bail > 0)) { 793 bail--; 794 } 795 if (bail == 0) goto crap; 796 return; 797 crap: 798 /* if we time out fill the buffer with NOPs and cross fingers */ 799 DPRINTF("GET %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 800 sc->sc_put = 0; 801 sc->sc_current = 0; 802 for (i = 0; i < 0x2000; i += 4) 803 bus_space_write_stream_4(sc->sc_memt, sc->sc_fbh, i, 0); 804 aprint_error_dev(sc->sc_dev, "DMA lockup\n"); 805 } 806 807 void 808 gffb_init(struct gffb_softc *sc) 809 { 810 int i; 811 uint32_t foo; 812 813 if (!sc->sc_accel) return; 814 DPRINTF("%s offset %08x %08x\n", __func__, 815 GFFB_READ_4(GFFB_CRTC0 + GFFB_DISPLAYSTART), 816 GFFB_READ_4(GFFB_CRTC1 + GFFB_DISPLAYSTART)); 817 818 sc->sc_fboffset = 0x2000; 819 820 /* init display start */ 821 GFFB_WRITE_4(GFFB_CRTC0 + GFFB_DISPLAYSTART, sc->sc_fboffset); 822 GFFB_WRITE_4(GFFB_CRTC1 + GFFB_DISPLAYSTART, sc->sc_fboffset); 823 824 /* DMA stuff. A whole lot of magic number voodoo from xf86-video-nv */ 825 GFFB_WRITE_4(GFFB_PMC + 0x140, 0); 826 GFFB_WRITE_4(GFFB_PMC + 0x200, 0xffff00ff); 827 GFFB_WRITE_4(GFFB_PMC + 0x200, 0xffffffff); 828 GFFB_WRITE_4(GFFB_PTIMER + 0x800, 8); 829 GFFB_WRITE_4(GFFB_PTIMER + 0x840, 3); 830 GFFB_WRITE_4(GFFB_PTIMER + 0x500, 0); 831 GFFB_WRITE_4(GFFB_PTIMER + 0x400, 0xffffffff); 832 for (i = 0; i < 8; i++) { 833 GFFB_WRITE_4(GFFB_PFB + 0x0240 + (i * 0x10), 0); 834 GFFB_WRITE_4(GFFB_PFB + 0x0244 + (i * 0x10), 835 sc->sc_vramsize - 1); 836 } 837 838 GFFB_WRITE_4(GFFB_PRAMIN, 0x80000010); 839 GFFB_WRITE_4(GFFB_PRAMIN + 0x04, 0x80011201); 840 GFFB_WRITE_4(GFFB_PRAMIN + 0x08, 0x80000011); 841 GFFB_WRITE_4(GFFB_PRAMIN + 0x0c, 0x80011202); 842 GFFB_WRITE_4(GFFB_PRAMIN + 0x10, 0x80000012); 843 GFFB_WRITE_4(GFFB_PRAMIN + 0x14, 0x80011203); 844 GFFB_WRITE_4(GFFB_PRAMIN + 0x18, 0x80000013); 845 GFFB_WRITE_4(GFFB_PRAMIN + 0x1c, 0x80011204); 846 GFFB_WRITE_4(GFFB_PRAMIN + 0x20, 0x80000014); 847 GFFB_WRITE_4(GFFB_PRAMIN + 0x24, 0x80011205); 848 GFFB_WRITE_4(GFFB_PRAMIN + 0x28, 0x80000015); 849 GFFB_WRITE_4(GFFB_PRAMIN + 0x2c, 0x80011206); 850 GFFB_WRITE_4(GFFB_PRAMIN + 0x30, 0x80000016); 851 GFFB_WRITE_4(GFFB_PRAMIN + 0x34, 0x80011207); 852 GFFB_WRITE_4(GFFB_PRAMIN + 0x38, 0x80000017); 853 GFFB_WRITE_4(GFFB_PRAMIN + 0x3c, 0x80011208); 854 GFFB_WRITE_4(GFFB_PRAMIN + 0x2000, 0x00003000); 855 GFFB_WRITE_4(GFFB_PRAMIN + 0x2004, sc->sc_vramsize - 1); 856 GFFB_WRITE_4(GFFB_PRAMIN + 0x2008, 0x00000002); 857 GFFB_WRITE_4(GFFB_PRAMIN + 0x200c, 0x00000002); 858 GFFB_WRITE_4(GFFB_PRAMIN + 0x2010, 0x01008062); /* nv10+ */ 859 GFFB_WRITE_4(GFFB_PRAMIN + 0x2014, 0); 860 GFFB_WRITE_4(GFFB_PRAMIN + 0x2018, 0x12001200); 861 GFFB_WRITE_4(GFFB_PRAMIN + 0x201c, 0); 862 GFFB_WRITE_4(GFFB_PRAMIN + 0x2020, 0x01008043); 863 GFFB_WRITE_4(GFFB_PRAMIN + 0x2024, 0); 864 GFFB_WRITE_4(GFFB_PRAMIN + 0x2028, 0); 865 GFFB_WRITE_4(GFFB_PRAMIN + 0x202c, 0); 866 GFFB_WRITE_4(GFFB_PRAMIN + 0x2030, 0x01008044); 867 GFFB_WRITE_4(GFFB_PRAMIN + 0x2034, 0x00000002); 868 GFFB_WRITE_4(GFFB_PRAMIN + 0x2038, 0); 869 GFFB_WRITE_4(GFFB_PRAMIN + 0x203c, 0); 870 GFFB_WRITE_4(GFFB_PRAMIN + 0x2040, 0x01008019); 871 GFFB_WRITE_4(GFFB_PRAMIN + 0x2044, 0); 872 GFFB_WRITE_4(GFFB_PRAMIN + 0x2048, 0); 873 GFFB_WRITE_4(GFFB_PRAMIN + 0x204c, 0); 874 GFFB_WRITE_4(GFFB_PRAMIN + 0x2050, 0x0100a05c); 875 GFFB_WRITE_4(GFFB_PRAMIN + 0x2054, 0); 876 GFFB_WRITE_4(GFFB_PRAMIN + 0x2058, 0); 877 GFFB_WRITE_4(GFFB_PRAMIN + 0x205c, 0); 878 /* XXX 0x0100805f if !WaitVSynvPossible */ 879 GFFB_WRITE_4(GFFB_PRAMIN + 0x2060, 0x0100805f); 880 GFFB_WRITE_4(GFFB_PRAMIN + 0x2064, 0); 881 GFFB_WRITE_4(GFFB_PRAMIN + 0x2068, 0x12001200); 882 GFFB_WRITE_4(GFFB_PRAMIN + 0x206c, 0); 883 GFFB_WRITE_4(GFFB_PRAMIN + 0x2070, 0x0100804a); 884 GFFB_WRITE_4(GFFB_PRAMIN + 0x2074, 0x00000002); 885 GFFB_WRITE_4(GFFB_PRAMIN + 0x2078, 0); 886 GFFB_WRITE_4(GFFB_PRAMIN + 0x207c, 0); 887 GFFB_WRITE_4(GFFB_PRAMIN + 0x2080, 0x01018077); 888 GFFB_WRITE_4(GFFB_PRAMIN + 0x2084, 0); 889 GFFB_WRITE_4(GFFB_PRAMIN + 0x2088, 0x12001200); 890 GFFB_WRITE_4(GFFB_PRAMIN + 0x208c, 0); 891 GFFB_WRITE_4(GFFB_PRAMIN + 0x2090, 0x00003002); 892 GFFB_WRITE_4(GFFB_PRAMIN + 0x2094, 0x00007fff); 893 /* command buffer start with some flag in the lower bits */ 894 GFFB_WRITE_4(GFFB_PRAMIN + 0x2098, sc->sc_vramsize | 0x00000002); 895 GFFB_WRITE_4(GFFB_PRAMIN + 0x209c, 0x00000002); 896 #if BYTE_ORDER == BIG_ENDIAN 897 GFFB_WRITE_4(GFFB_PRAMIN + 0x2010, 0x01088062); 898 GFFB_WRITE_4(GFFB_PRAMIN + 0x2020, 0x01088043); 899 GFFB_WRITE_4(GFFB_PRAMIN + 0x2030, 0x01088044); 900 GFFB_WRITE_4(GFFB_PRAMIN + 0x2040, 0x01088019); 901 GFFB_WRITE_4(GFFB_PRAMIN + 0x2050, 0x0108a05c); 902 GFFB_WRITE_4(GFFB_PRAMIN + 0x2060, 0x0108805f); 903 GFFB_WRITE_4(GFFB_PRAMIN + 0x2070, 0x0108804a); 904 GFFB_WRITE_4(GFFB_PRAMIN + 0x2080, 0x01098077); 905 GFFB_WRITE_4(GFFB_PRAMIN + 0x2034, 0x00000001); 906 GFFB_WRITE_4(GFFB_PRAMIN + 0x2074, 0x00000001); 907 #endif 908 /* PGRAPH setup */ 909 GFFB_WRITE_4(GFFB_PGRAPH + 0x0080, 0xFFFFFFFF); 910 GFFB_WRITE_4(GFFB_PGRAPH + 0x0080, 0x00000000); 911 912 GFFB_WRITE_4(GFFB_PGRAPH + 0x0140, 0x00000000); 913 GFFB_WRITE_4(GFFB_PGRAPH + 0x0100, 0xFFFFFFFF); 914 GFFB_WRITE_4(GFFB_PGRAPH + 0x0144, 0x10010100); 915 GFFB_WRITE_4(GFFB_PGRAPH + 0x0714, 0xFFFFFFFF); 916 GFFB_WRITE_4(GFFB_PGRAPH + 0x0720, 0x00000001); 917 /* 918 * xf86_video_nv does this in two writes, 919 * not sure if they can be combined 920 */ 921 foo = GFFB_READ_4(GFFB_PGRAPH + 0x0710); 922 foo &= 0x0007ff00; 923 foo |= 0x00020100; 924 GFFB_WRITE_4(GFFB_PGRAPH + 0x0710, foo); 925 926 /* NV_ARCH_10 */ 927 if(sc->sc_arch == 10) { 928 GFFB_WRITE_4(GFFB_PGRAPH + 0x0084, 0x00118700); 929 GFFB_WRITE_4(GFFB_PGRAPH + 0x0088, 0x24E00810); 930 GFFB_WRITE_4(GFFB_PGRAPH + 0x008C, 0x55DE0030); 931 932 for(i = 0; i < 128; i += 4) { 933 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B00 + i, 934 GFFB_READ_4(GFFB_PFB + 0x0240 + i)); 935 } 936 937 GFFB_WRITE_4(GFFB_PGRAPH + 0x640, 0); 938 GFFB_WRITE_4(GFFB_PGRAPH + 0x644, 0); 939 GFFB_WRITE_4(GFFB_PGRAPH + 0x684, sc->sc_vramsize - 1); 940 GFFB_WRITE_4(GFFB_PGRAPH + 0x688, sc->sc_vramsize - 1); 941 942 GFFB_WRITE_4(GFFB_PGRAPH + 0x0810, 0x00000000); 943 GFFB_WRITE_4(GFFB_PGRAPH + 0x0608, 0xFFFFFFFF); 944 } else { 945 /* nv30 */ 946 GFFB_WRITE_4(GFFB_PGRAPH + 0x0084, 0x40108700); 947 GFFB_WRITE_4(GFFB_PGRAPH + 0x0890, 0x00140000); 948 GFFB_WRITE_4(GFFB_PGRAPH + 0x008C, 0xf00e0431); 949 GFFB_WRITE_4(GFFB_PGRAPH + 0x0090, 0x00008000); 950 GFFB_WRITE_4(GFFB_PGRAPH + 0x0610, 0xf04b1f36); 951 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B80, 0x1002d888); 952 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B88, 0x62ff007f); 953 954 for (i = 0; i < 128; i += 4) { 955 GFFB_WRITE_4(GFFB_PGRAPH + 0x0900 + i, 956 GFFB_READ_4(GFFB_PFB + 0x0240 + i)); 957 GFFB_WRITE_4(GFFB_PGRAPH + 0x6900 + i, 958 GFFB_READ_4(GFFB_PFB + 0x0240 + i)); 959 } 960 961 GFFB_WRITE_4(GFFB_PGRAPH + 0x09A4, 962 GFFB_READ_4(GFFB_PFB + 0x0200)); 963 GFFB_WRITE_4(GFFB_PGRAPH + 0x09A8, 964 GFFB_READ_4(GFFB_PFB + 0x0204)); 965 GFFB_WRITE_4(GFFB_PGRAPH + 0x0750, 0x00EA0000); 966 GFFB_WRITE_4(GFFB_PGRAPH + 0x0754, 967 GFFB_READ_4(GFFB_PFB + 0x0200)); 968 GFFB_WRITE_4(GFFB_PGRAPH + 0x0750, 0x00EA0004); 969 GFFB_WRITE_4(GFFB_PGRAPH + 0x0754, 970 GFFB_READ_4(GFFB_PFB + 0x0204)); 971 972 GFFB_WRITE_4(GFFB_PGRAPH + 0x0820, 0); 973 GFFB_WRITE_4(GFFB_PGRAPH + 0x0824, 0); 974 GFFB_WRITE_4(GFFB_PGRAPH + 0x0864, sc->sc_vramsize - 1); 975 GFFB_WRITE_4(GFFB_PGRAPH + 0x0868, sc->sc_vramsize - 1); 976 977 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B20, 0x00000000); 978 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B04, 0xFFFFFFFF); 979 } 980 981 /* PFIFO setup */ 982 GFFB_WRITE_4(GFFB_PGRAPH + 0x053C, 0); 983 GFFB_WRITE_4(GFFB_PGRAPH + 0x0540, 0); 984 GFFB_WRITE_4(GFFB_PGRAPH + 0x0544, 0x00007FFF); 985 GFFB_WRITE_4(GFFB_PGRAPH + 0x0548, 0x00007FFF); 986 987 GFFB_WRITE_4(GFFB_PFIFO + 0x0500, 0); 988 GFFB_WRITE_4(GFFB_PFIFO + 0x0504, 0x00000001); 989 GFFB_WRITE_4(GFFB_PFIFO + 0x1200, 0); 990 GFFB_WRITE_4(GFFB_PFIFO + 0x1250, 0); 991 GFFB_WRITE_4(GFFB_PFIFO + 0x1204, 0x00000100); /* different on nv40 */ 992 GFFB_WRITE_4(GFFB_PFIFO + 0x1240, 0); 993 GFFB_WRITE_4(GFFB_PFIFO + 0x1244, 0); 994 GFFB_WRITE_4(GFFB_PFIFO + 0x122c, 0x00001209); /* different on nv40 */ 995 GFFB_WRITE_4(GFFB_PFIFO + 0x1000, 0); 996 GFFB_WRITE_4(GFFB_PFIFO + 0x1050, 0); 997 GFFB_WRITE_4(GFFB_PFIFO + 0x0210, 0x03000100); 998 GFFB_WRITE_4(GFFB_PFIFO + 0x0214, 0x00000110); 999 GFFB_WRITE_4(GFFB_PFIFO + 0x0218, 0x00000112); 1000 GFFB_WRITE_4(GFFB_PFIFO + 0x050c, 0x0000ffff); 1001 GFFB_WRITE_4(GFFB_PFIFO + 0x1258, 0x0000ffff); 1002 GFFB_WRITE_4(GFFB_PFIFO + 0x0140, 0); 1003 GFFB_WRITE_4(GFFB_PFIFO + 0x0100, 0xffffffff); 1004 GFFB_WRITE_4(GFFB_PFIFO + 0x1054, 0x00000001); 1005 GFFB_WRITE_4(GFFB_PFIFO + 0x1230, 0); 1006 GFFB_WRITE_4(GFFB_PFIFO + 0x1280, 0); 1007 #if BYTE_ORDER == BIG_ENDIAN 1008 GFFB_WRITE_4(GFFB_PFIFO + 0x1224, 0x800f0078); 1009 #else 1010 GFFB_WRITE_4(GFFB_PFIFO + 0x1224, 0x000f0078); 1011 #endif 1012 GFFB_WRITE_4(GFFB_PFIFO + 0x1220, 0x00000001); 1013 GFFB_WRITE_4(GFFB_PFIFO + 0x1200, 0x00000001); 1014 GFFB_WRITE_4(GFFB_PFIFO + 0x1250, 0x00000001); 1015 GFFB_WRITE_4(GFFB_PFIFO + 0x1254, 0x00000001); 1016 GFFB_WRITE_4(GFFB_PFIFO + 0x0500, 0x00000001); 1017 1018 GFFB_WRITE_4(GFFB_PMC + 0x8704, 1); 1019 GFFB_WRITE_4(GFFB_PMC + 0x8140, 0); 1020 GFFB_WRITE_4(GFFB_PMC + 0x8920, 0); 1021 GFFB_WRITE_4(GFFB_PMC + 0x8924, 0); 1022 GFFB_WRITE_4(GFFB_PMC + 0x8908, sc->sc_vramsize - 1); 1023 GFFB_WRITE_4(GFFB_PMC + 0x890C, sc->sc_vramsize - 1); 1024 GFFB_WRITE_4(GFFB_PMC + 0x1588, 0); 1025 1026 __asm("eieio; sync;"); 1027 GFFB_WRITE_4(GFFB_FIFO_GET, 0); 1028 GFFB_WRITE_4(GFFB_CMDSTART, 0x00000002); 1029 sc->sc_put = 0; 1030 sc->sc_current = 0; 1031 sc->sc_free = 0x2000; 1032 1033 for(i = 0; i < SKIPS; i++) 1034 gffb_dmanext(sc, 0); 1035 1036 gffb_dmanext(sc, 0x00040000); 1037 gffb_dmanext(sc, 0x80000010); 1038 gffb_dmanext(sc, 0x00042000); 1039 gffb_dmanext(sc, 0x80000011); 1040 gffb_dmanext(sc, 0x00044000); 1041 gffb_dmanext(sc, 0x80000012); 1042 gffb_dmanext(sc, 0x00046000); 1043 gffb_dmanext(sc, 0x80000013); 1044 gffb_dmanext(sc, 0x00048000); 1045 gffb_dmanext(sc, 0x80000014); 1046 gffb_dmanext(sc, 0x0004A000); 1047 gffb_dmanext(sc, 0x80000015); 1048 gffb_dmanext(sc, 0x0004C000); 1049 gffb_dmanext(sc, 0x80000016); 1050 gffb_dmanext(sc, 0x0004E000); 1051 gffb_dmanext(sc, 0x80000017); 1052 sc->sc_free = 0x2000 - sc->sc_current; 1053 1054 gffb_dmastart(sc, SURFACE_FORMAT, 4); 1055 gffb_dmanext(sc, SURFACE_FORMAT_DEPTH8); 1056 gffb_dmanext(sc, sc->sc_stride | (sc->sc_stride << 16)); 1057 gffb_dmanext(sc, sc->sc_fboffset); /* src offset */ 1058 gffb_dmanext(sc, sc->sc_fboffset); /* dst offset */ 1059 1060 gffb_dmastart(sc, RECT_FORMAT, 1); 1061 gffb_dmanext(sc, RECT_FORMAT_DEPTH8); 1062 1063 gffb_dmastart(sc, PATTERN_FORMAT, 1); 1064 gffb_dmanext(sc, PATTERN_FORMAT_DEPTH8); 1065 1066 gffb_dmastart(sc, PATTERN_COLOR_0, 4); 1067 gffb_dmanext(sc, 0xffffffff); 1068 gffb_dmanext(sc, 0xffffffff); 1069 gffb_dmanext(sc, 0xffffffff); 1070 gffb_dmanext(sc, 0xffffffff); 1071 1072 gffb_dmastart(sc, ROP_SET, 1); 1073 gffb_dmanext(sc, 0xcc); 1074 sc->sc_rop = 0xcc; 1075 DPRINTF("put %x current %x\n", sc->sc_put, sc->sc_current); 1076 1077 gffb_dma_kickoff(sc); 1078 DPRINTF("put %x current %x\n", sc->sc_put, sc->sc_current); 1079 #ifdef GFFB_DEBUG 1080 printf("put: %08x\n", GFFB_READ_4(GFFB_FIFO_PUT)); 1081 printf("get: %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 1082 #endif 1083 gffb_sync(sc); 1084 DPRINTF("put %x current %x\n", sc->sc_put, sc->sc_current); 1085 } 1086 1087 static void 1088 gffb_rop(struct gffb_softc *sc, int rop) 1089 { 1090 if (rop == sc->sc_rop) 1091 return; 1092 sc->sc_rop = rop; 1093 gffb_dmastart(sc, ROP_SET, 1); 1094 gffb_dmanext(sc, rop); 1095 } 1096 1097 static void 1098 gffb_rectfill(struct gffb_softc *sc, int x, int y, int wi, int he, 1099 uint32_t colour) 1100 { 1101 if (!sc->sc_accel) return; 1102 mutex_enter(&sc->sc_lock); 1103 gffb_rop(sc, 0xcc); 1104 1105 gffb_dmastart(sc, RECT_SOLID_COLOR, 1); 1106 gffb_dmanext(sc, colour); 1107 1108 gffb_dmastart(sc, RECT_SOLID_RECTS(0), 2); 1109 gffb_dmanext(sc, (x << 16) | y); 1110 gffb_dmanext(sc, (wi << 16) | he); 1111 gffb_dma_kickoff(sc); 1112 mutex_exit(&sc->sc_lock); 1113 } 1114 1115 static void 1116 gffb_bitblt(void *cookie, int xs, int ys, int xd, int yd, 1117 int wi, int he, int rop) 1118 { 1119 struct gffb_softc *sc = cookie; 1120 1121 if (!sc->sc_accel) return; 1122 mutex_enter(&sc->sc_lock); 1123 1124 gffb_rop(sc, rop); 1125 1126 gffb_dmastart(sc, BLIT_POINT_SRC, 3); 1127 gffb_dmanext(sc, (ys << 16) | xs); 1128 gffb_dmanext(sc, (yd << 16) | xd); 1129 gffb_dmanext(sc, (he << 16) | wi); 1130 gffb_dma_kickoff(sc); 1131 mutex_exit(&sc->sc_lock); 1132 } 1133 1134 static void 1135 gffb_cursor(void *cookie, int on, int row, int col) 1136 { 1137 struct rasops_info *ri = cookie; 1138 struct vcons_screen *scr = ri->ri_hw; 1139 struct gffb_softc *sc = scr->scr_cookie; 1140 int x, y, wi, he; 1141 1142 wi = ri->ri_font->fontwidth; 1143 he = ri->ri_font->fontheight; 1144 1145 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1146 x = ri->ri_ccol * wi + ri->ri_xorigin; 1147 y = ri->ri_crow * he + ri->ri_yorigin; 1148 if (ri->ri_flg & RI_CURSOR) { 1149 gffb_bitblt(sc, x, y, x, y, wi, he, 0x33); 1150 ri->ri_flg &= ~RI_CURSOR; 1151 } 1152 ri->ri_crow = row; 1153 ri->ri_ccol = col; 1154 if (on) { 1155 x = ri->ri_ccol * wi + ri->ri_xorigin; 1156 y = ri->ri_crow * he + ri->ri_yorigin; 1157 gffb_bitblt(sc, x, y, x, y, wi, he, 0x33); 1158 ri->ri_flg |= RI_CURSOR; 1159 } 1160 } else { 1161 scr->scr_ri.ri_crow = row; 1162 scr->scr_ri.ri_ccol = col; 1163 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1164 } 1165 1166 } 1167 1168 static void 1169 gffb_putchar(void *cookie, int row, int col, u_int c, long attr) 1170 { 1171 struct rasops_info *ri = cookie; 1172 struct wsdisplay_font *font = PICK_FONT(ri, c); 1173 struct vcons_screen *scr = ri->ri_hw; 1174 struct gffb_softc *sc = scr->scr_cookie; 1175 int x, y, wi, he, rv = GC_NOPE; 1176 uint32_t bg; 1177 1178 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1179 return; 1180 1181 if (!CHAR_IN_FONT(c, font)) 1182 return; 1183 1184 wi = font->fontwidth; 1185 he = font->fontheight; 1186 1187 x = ri->ri_xorigin + col * wi; 1188 y = ri->ri_yorigin + row * he; 1189 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1190 1191 if (c == 0x20) { 1192 gffb_rectfill(sc, x, y, wi, he, bg); 1193 return; 1194 } 1195 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1196 if (rv == GC_OK) 1197 return; 1198 1199 /* 1200 * Use gffb_sync to wait for the engine to become idle before 1201 * we start scribbling into VRAM -- we wouldn't want to stomp on 1202 * a scroll in progress or a prior glyphcache_add that hasn't 1203 * completed yet on the GPU. 1204 */ 1205 mutex_enter(&sc->sc_lock); 1206 gffb_sync(sc); 1207 sc->sc_putchar(cookie, row, col, c, attr); 1208 mutex_exit(&sc->sc_lock); 1209 1210 /* 1211 * If glyphcache_try asked us to, cache the newly written 1212 * character. This will issue a gffb_bitblt which will wait 1213 * for our CPU writes to the framebuffer in VRAM to complete 1214 * before triggering GPU reads from the framebuffer in VRAM. 1215 */ 1216 if (rv == GC_ADD) { 1217 glyphcache_add(&sc->sc_gc, c, x, y); 1218 } 1219 } 1220 1221 static void 1222 gffb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1223 { 1224 struct rasops_info *ri = cookie; 1225 struct vcons_screen *scr = ri->ri_hw; 1226 struct gffb_softc *sc = scr->scr_cookie; 1227 int32_t xs, xd, y, width, height; 1228 1229 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1230 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1231 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1232 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1233 width = ri->ri_font->fontwidth * ncols; 1234 height = ri->ri_font->fontheight; 1235 gffb_bitblt(sc, xs, y, xd, y, width, height, 0xcc); 1236 } 1237 } 1238 1239 static void 1240 gffb_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1241 { 1242 struct rasops_info *ri = cookie; 1243 struct vcons_screen *scr = ri->ri_hw; 1244 struct gffb_softc *sc = scr->scr_cookie; 1245 int32_t x, y, width, height, fg, bg, ul; 1246 1247 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1248 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1249 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1250 width = ri->ri_font->fontwidth * ncols; 1251 height = ri->ri_font->fontheight; 1252 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1253 1254 gffb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1255 } 1256 } 1257 1258 static void 1259 gffb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1260 { 1261 struct rasops_info *ri = cookie; 1262 struct vcons_screen *scr = ri->ri_hw; 1263 struct gffb_softc *sc = scr->scr_cookie; 1264 int32_t x, ys, yd, width, height; 1265 1266 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1267 x = ri->ri_xorigin; 1268 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1269 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1270 width = ri->ri_emuwidth; 1271 height = ri->ri_font->fontheight * nrows; 1272 gffb_bitblt(sc, x, ys, x, yd, width, height, 0xcc); 1273 } 1274 } 1275 1276 static void 1277 gffb_eraserows(void *cookie, int row, int nrows, long fillattr) 1278 { 1279 struct rasops_info *ri = cookie; 1280 struct vcons_screen *scr = ri->ri_hw; 1281 struct gffb_softc *sc = scr->scr_cookie; 1282 int32_t x, y, width, height, fg, bg, ul; 1283 1284 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1285 x = ri->ri_xorigin; 1286 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1287 width = ri->ri_emuwidth; 1288 height = ri->ri_font->fontheight * nrows; 1289 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1290 1291 gffb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1292 } 1293 } 1294
Indexes created Mon Sep 29 21:09:56 GMT 2025