gffb.c revision 1.26
1 /* $NetBSD: gffb.c,v 1.26 2025/08/30 07:25:10 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * A console driver for nvidia geforce graphics controllers 30 * tested on macppc only so far, should work on other hardware as long as 31 * something sets up a usable graphics mode and sets the right device properties 32 * This driver should work with all NV1x hardware but so far it's been tested 33 * only on NV11 / GeForce2 MX. Needs testing with more hardware and if 34 * successful, PCI IDs need to be added to gffb_match() 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: gffb.c,v 1.26 2025/08/30 07:25:10 macallan Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <sys/lwp.h> 45 #include <sys/kauth.h> 46 #include <sys/atomic.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcidevs.h> 51 #include <dev/pci/pciio.h> 52 #include <dev/pci/gffbreg.h> 53 54 #include <dev/wscons/wsdisplayvar.h> 55 #include <dev/wscons/wsconsio.h> 56 #include <dev/wsfont/wsfont.h> 57 #include <dev/rasops/rasops.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 #include <dev/pci/wsdisplay_pci.h> 60 #include <dev/wscons/wsdisplay_glyphcachevar.h> 61 62 #include "opt_gffb.h" 63 #include "opt_vcons.h" 64 65 #ifdef GFFB_DEBUG 66 #define DPRINTF printf 67 #else 68 #define DPRINTF while(0) printf 69 #endif 70 71 struct gffb_softc { 72 device_t sc_dev; 73 74 pci_chipset_tag_t sc_pc; 75 pcitag_t sc_pcitag; 76 77 bus_space_tag_t sc_memt; 78 bus_space_tag_t sc_iot; 79 80 bus_space_handle_t sc_regh, sc_fbh; 81 bus_addr_t sc_fb, sc_reg; 82 bus_size_t sc_fbsize, sc_regsize; 83 uint8_t *sc_fbaddr; 84 size_t sc_vramsize; 85 uint32_t sc_fboffset; 86 87 int sc_width, sc_height, sc_depth, sc_stride; 88 int sc_locked, sc_accel; 89 struct vcons_screen sc_console_screen; 90 struct wsscreen_descr sc_defaultscreen_descr; 91 const struct wsscreen_descr *sc_screens[1]; 92 struct wsscreen_list sc_screenlist; 93 struct vcons_data vd; 94 int sc_mode, sc_arch; 95 u_char sc_cmap_red[256]; 96 u_char sc_cmap_green[256]; 97 u_char sc_cmap_blue[256]; 98 int sc_put, sc_current, sc_free; 99 uint32_t sc_rop; 100 void (*sc_putchar)(void *, int, int, u_int, long); 101 kmutex_t sc_lock; 102 glyphcache sc_gc; 103 }; 104 105 static int gffb_match(device_t, cfdata_t, void *); 106 static void gffb_attach(device_t, device_t, void *); 107 108 CFATTACH_DECL_NEW(gffb, sizeof(struct gffb_softc), 109 gffb_match, gffb_attach, NULL, NULL); 110 111 static int gffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 112 static paddr_t gffb_mmap(void *, void *, off_t, int); 113 static void gffb_init_screen(void *, struct vcons_screen *, int, long *); 114 115 static int gffb_putcmap(struct gffb_softc *, struct wsdisplay_cmap *); 116 static int gffb_getcmap(struct gffb_softc *, struct wsdisplay_cmap *); 117 static void gffb_restore_palette(struct gffb_softc *); 118 static int gffb_putpalreg(struct gffb_softc *, uint8_t, uint8_t, 119 uint8_t, uint8_t); 120 121 void gffb_init(struct gffb_softc *); 122 123 static void gffb_make_room(struct gffb_softc *, int); 124 static void gffb_sync(struct gffb_softc *); 125 126 static void gffb_rectfill(struct gffb_softc *, int, int, int, int, 127 uint32_t); 128 static void gffb_bitblt(void *, int, int, int, int, int, int, int); 129 static void gffb_rop(struct gffb_softc *, int); 130 131 static void gffb_cursor(void *, int, int, int); 132 static void gffb_putchar(void *, int, int, u_int, long); 133 static void gffb_copycols(void *, int, int, int, int); 134 static void gffb_erasecols(void *, int, int, int, long); 135 static void gffb_copyrows(void *, int, int, int); 136 static void gffb_eraserows(void *, int, int, long); 137 138 #define GFFB_READ_4(o) bus_space_read_stream_4(sc->sc_memt, sc->sc_regh, (o)) 139 #define GFFB_WRITE_4(o, v) bus_space_write_stream_4(sc->sc_memt, sc->sc_regh, (o), (v)) 140 #define GFFB_WRITE_1(o, v) bus_space_write_1(sc->sc_memt, sc->sc_regh, (o), (v)) 141 142 struct wsdisplay_accessops gffb_accessops = { 143 gffb_ioctl, 144 gffb_mmap, 145 NULL, /* alloc_screen */ 146 NULL, /* free_screen */ 147 NULL, /* show_screen */ 148 NULL, /* load_font */ 149 NULL, /* pollc */ 150 NULL /* scroll */ 151 }; 152 153 static int 154 gffb_match(device_t parent, cfdata_t match, void *aux) 155 { 156 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 157 158 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 159 return 0; 160 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_NVIDIA) 161 return 0; 162 163 /* only cards tested on so far - likely needs a list */ 164 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GEFORCE2MX) 165 return 100; 166 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GEFORCE_6800U) 167 return 100; 168 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GF_FXGO5200) 169 return 100; 170 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NVIDIA_GF_FX5200U) 171 return 100; 172 return (0); 173 } 174 175 static void 176 gffb_attach(device_t parent, device_t self, void *aux) 177 { 178 struct gffb_softc *sc = device_private(self); 179 struct pci_attach_args *pa = aux; 180 struct rasops_info *ri; 181 bus_space_tag_t tag; 182 struct wsemuldisplaydev_attach_args aa; 183 prop_dictionary_t dict; 184 unsigned long defattr; 185 pcireg_t reg; 186 bool is_console = FALSE; 187 uint32_t addr; 188 int i, j, f; 189 uint8_t cmap[768]; 190 191 sc->sc_pc = pa->pa_pc; 192 sc->sc_pcitag = pa->pa_tag; 193 sc->sc_memt = pa->pa_memt; 194 sc->sc_iot = pa->pa_iot; 195 sc->sc_dev = self; 196 197 /* first, see what kind of chip we've got */ 198 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PCI_ID_REG); 199 switch (PCI_PRODUCT(reg)) { 200 case PCI_PRODUCT_NVIDIA_GEFORCE2MX: 201 sc->sc_accel = true; 202 sc->sc_arch = 10; 203 break; 204 case PCI_PRODUCT_NVIDIA_GEFORCE_6800U: 205 sc->sc_accel = false; 206 sc->sc_arch = 40; 207 break; 208 case PCI_PRODUCT_NVIDIA_GF_FXGO5200: 209 case PCI_PRODUCT_NVIDIA_GF_FX5200U: 210 sc->sc_accel = true; 211 sc->sc_arch = 30; 212 break; 213 default: 214 sc->sc_accel = false; 215 sc->sc_arch = 0; 216 } 217 218 pci_aprint_devinfo(pa, NULL); 219 DPRINTF("%s accel %d arch %d\n", __func__, sc->sc_accel, sc->sc_arch); 220 /* fill in parameters from properties */ 221 dict = device_properties(self); 222 if (!prop_dictionary_get_uint32(dict, "width", &sc->sc_width)) { 223 aprint_error("%s: no width property\n", device_xname(self)); 224 return; 225 } 226 if (!prop_dictionary_get_uint32(dict, "height", &sc->sc_height)) { 227 aprint_error("%s: no height property\n", device_xname(self)); 228 return; 229 } 230 231 #ifdef GLYPHCACHE_DEBUG 232 /* leave some visible VRAM unused so we can see the glyph cache */ 233 sc->sc_height -= 300; 234 #endif 235 236 if (!prop_dictionary_get_uint32(dict, "depth", &sc->sc_depth)) { 237 aprint_error("%s: no depth property\n", device_xname(self)); 238 return; 239 } 240 if (!prop_dictionary_get_uint32(dict, "linebytes", &sc->sc_stride)) { 241 aprint_error("%s: no linebytes property\n", 242 device_xname(self)); 243 return; 244 } 245 246 /* 247 * on !2MX we need to use the firmware's offset - for some reason 248 * register writes to anything other than the DACs go wrong 249 */ 250 sc->sc_fboffset = 0; 251 if (prop_dictionary_get_uint32(dict, "address", &addr)) { 252 sc->sc_fboffset = addr & 0x000fffff; /* XXX */ 253 } 254 DPRINTF("%s: fboffset %8x\n", __func__, sc->sc_fboffset); 255 prop_dictionary_get_bool(dict, "is_console", &is_console); 256 257 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_MEM, 0, 258 &tag, &sc->sc_regh, &sc->sc_reg, &sc->sc_regsize)) { 259 aprint_error("%s: failed to map registers.\n", 260 device_xname(sc->sc_dev)); 261 } 262 /* 263 * first thing we need to make sure register access uses host byte order 264 * so we can recycle as much of xf86-video-nv as possible 265 */ 266 #if BYTE_ORDER == BIG_ENDIAN 267 uint32_t mreg = GFFB_READ_4(GFFB_PMC + 4); 268 if ((mreg & 0x01000001) == 0) { 269 GFFB_WRITE_4(GFFB_PMC + 4, 0x01000001); 270 } 271 #endif 272 sc->sc_vramsize = GFFB_READ_4(GFFB_VRAM) & 0xfff00000; 273 274 /* don't map more VRAM than we actually have */ 275 if (pci_mapreg_info(sc->sc_pc, sc->sc_pcitag, 276 0x14, PCI_MAPREG_TYPE_MEM, &sc->sc_fb, &sc->sc_fbsize, &f)) { 277 aprint_error("%s: can't find the framebuffer?!\n", 278 device_xname(sc->sc_dev)); 279 } 280 if (sc->sc_vramsize == 0) sc->sc_vramsize = sc->sc_fbsize; 281 282 /* don't map (much) more than we actually need */ 283 if (bus_space_map(sc->sc_memt, sc->sc_fb, 0x1000000, 284 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, 285 &sc->sc_fbh)) { 286 aprint_error("%s: failed to map the framebuffer.\n", 287 device_xname(sc->sc_dev)); 288 } 289 sc->sc_fbaddr = bus_space_vaddr(tag, sc->sc_fbh); 290 291 aprint_normal("%s: %d MB aperture at 0x%08x\n", device_xname(self), 292 (int)(sc->sc_fbsize >> 20), (uint32_t)sc->sc_fb); 293 aprint_normal_dev(sc->sc_dev, "%d MB video memory\n", 294 (int)(sc->sc_vramsize >> 20)); 295 296 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 297 "default", 298 0, 0, 299 NULL, 300 8, 16, 301 WSSCREEN_WSCOLORS | WSSCREEN_HILIT | WSSCREEN_RESIZE, 302 NULL 303 }; 304 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 305 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 306 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 307 sc->sc_locked = 0; 308 309 #ifdef GFFB_DEBUG 310 printf("put: %08x\n", GFFB_READ_4(GFFB_FIFO_PUT)); 311 printf("get: %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 312 #endif 313 314 /* 315 * we don't have hardware synchronization so we need a lock to serialize 316 * access to the DMA buffer between normal and kernel output 317 * actually it might be enough to use atomic ops on sc_current, sc_free 318 * etc. but for now we'll play it safe 319 * XXX we will probably deadlock if we take an interrupt while sc_lock 320 * is held and then try to printf() 321 */ 322 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 323 324 /* init engine here */ 325 gffb_init(sc); 326 327 #ifdef GFFB_DEBUG 328 printf("put: %08x\n", GFFB_READ_4(GFFB_FIFO_PUT)); 329 printf("get: %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 330 #endif 331 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 332 &gffb_accessops); 333 sc->vd.init_screen = gffb_init_screen; 334 335 336 ri = &sc->sc_console_screen.scr_ri; 337 338 if (sc->sc_accel) { 339 sc->sc_gc.gc_bitblt = gffb_bitblt; 340 sc->sc_gc.gc_blitcookie = sc; 341 sc->sc_gc.gc_rop = 0xcc; 342 sc->vd.show_screen_cookie = &sc->sc_gc; 343 sc->vd.show_screen_cb = glyphcache_adapt; 344 } 345 346 if (is_console) { 347 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 348 &defattr); 349 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 350 351 if (sc->sc_accel) { 352 gffb_rectfill(sc, 0, 0, sc->sc_width, sc->sc_height, 353 ri->ri_devcmap[(defattr >> 16) & 0xf]); 354 } else { 355 memset(sc->sc_fbaddr + sc->sc_fboffset, 356 ri->ri_devcmap[(defattr >> 16) & 0xf], 357 sc->sc_stride * sc->sc_height); 358 } 359 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 360 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 361 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 362 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 363 364 if (sc->sc_accel) 365 glyphcache_init(&sc->sc_gc, sc->sc_height + 5, 366 (0x800000 / sc->sc_stride) - sc->sc_height - 5, 367 sc->sc_width, 368 ri->ri_font->fontwidth, 369 ri->ri_font->fontheight, 370 defattr); 371 372 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 373 defattr); 374 vcons_replay_msgbuf(&sc->sc_console_screen); 375 } else { 376 /* 377 * since we're not the console we can postpone the rest 378 * until someone actually allocates a screen for us 379 */ 380 if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 381 /* do some minimal setup to avoid weirdnesses later */ 382 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 383 &defattr); 384 } else 385 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 386 387 if (sc->sc_accel) 388 glyphcache_init(&sc->sc_gc, sc->sc_height + 5, 389 (0x800000 / sc->sc_stride) - sc->sc_height - 5, 390 sc->sc_width, 391 ri->ri_font->fontwidth, 392 ri->ri_font->fontheight, 393 defattr); 394 } 395 396 j = 0; 397 rasops_get_cmap(ri, cmap, sizeof(cmap)); 398 for (i = 0; i < 256; i++) { 399 sc->sc_cmap_red[i] = cmap[j]; 400 sc->sc_cmap_green[i] = cmap[j + 1]; 401 sc->sc_cmap_blue[i] = cmap[j + 2]; 402 gffb_putpalreg(sc, i, cmap[j], cmap[j + 1], cmap[j + 2]); 403 j += 3; 404 } 405 406 /* no suspend/resume support yet */ 407 if (!pmf_device_register(sc->sc_dev, NULL, NULL)) 408 aprint_error_dev(sc->sc_dev, 409 "couldn't establish power handler\n"); 410 411 aa.console = is_console; 412 aa.scrdata = &sc->sc_screenlist; 413 aa.accessops = &gffb_accessops; 414 aa.accesscookie = &sc->vd; 415 416 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint, CFARGS_NONE); 417 } 418 419 static int 420 gffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 421 { 422 struct vcons_data *vd = v; 423 struct gffb_softc *sc = vd->cookie; 424 struct wsdisplay_fbinfo *wdf; 425 struct vcons_screen *ms = vd->active; 426 427 switch (cmd) { 428 case WSDISPLAYIO_GTYPE: 429 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 430 return 0; 431 432 /* PCI config read/write passthrough. */ 433 case PCI_IOC_CFGREAD: 434 case PCI_IOC_CFGWRITE: 435 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 436 cmd, data, flag, l); 437 438 case WSDISPLAYIO_GET_BUSID: 439 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 440 sc->sc_pcitag, data); 441 442 case WSDISPLAYIO_GINFO: 443 if (ms == NULL) 444 return ENODEV; 445 wdf = (void *)data; 446 wdf->height = ms->scr_ri.ri_height; 447 wdf->width = ms->scr_ri.ri_width; 448 wdf->depth = ms->scr_ri.ri_depth; 449 wdf->cmsize = 256; 450 return 0; 451 452 case WSDISPLAYIO_GETCMAP: 453 return gffb_getcmap(sc, 454 (struct wsdisplay_cmap *)data); 455 456 case WSDISPLAYIO_PUTCMAP: 457 return gffb_putcmap(sc, 458 (struct wsdisplay_cmap *)data); 459 460 case WSDISPLAYIO_LINEBYTES: 461 *(u_int *)data = sc->sc_stride; 462 return 0; 463 464 case WSDISPLAYIO_SMODE: { 465 int new_mode = *(int*)data; 466 if (new_mode != sc->sc_mode) { 467 sc->sc_mode = new_mode; 468 if(new_mode == WSDISPLAYIO_MODE_EMUL) { 469 gffb_init(sc); 470 gffb_restore_palette(sc); 471 if (sc->sc_accel) { 472 glyphcache_wipe(&sc->sc_gc); 473 gffb_rectfill(sc, 0, 0, sc->sc_width, 474 sc->sc_height, ms->scr_ri.ri_devcmap[ 475 (ms->scr_defattr >> 16) & 0xf]); 476 } else { 477 memset(sc->sc_fbaddr + sc->sc_fboffset, 478 ms->scr_ri.ri_devcmap[ 479 (ms->scr_defattr >> 16) & 0xf], 480 sc->sc_stride * sc->sc_height); 481 } 482 vcons_redraw_screen(ms); 483 } 484 } 485 } 486 return 0; 487 488 case WSDISPLAYIO_GET_EDID: { 489 struct wsdisplayio_edid_info *d = data; 490 return wsdisplayio_get_edid(sc->sc_dev, d); 491 } 492 493 case WSDISPLAYIO_GET_FBINFO: { 494 struct wsdisplayio_fbinfo *fbi = data; 495 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 496 } 497 } 498 return EPASSTHROUGH; 499 } 500 501 static paddr_t 502 gffb_mmap(void *v, void *vs, off_t offset, int prot) 503 { 504 struct vcons_data *vd = v; 505 struct gffb_softc *sc = vd->cookie; 506 paddr_t pa; 507 508 /* 'regular' framebuffer mmap()ing */ 509 if (offset < sc->sc_vramsize) { 510 pa = bus_space_mmap(sc->sc_memt, sc->sc_fb + offset + 0x2000, 511 0, prot, BUS_SPACE_MAP_LINEAR); 512 return pa; 513 } 514 515 /* 516 * restrict all other mappings to processes with superuser privileges 517 * or the kernel itself 518 */ 519 if (kauth_authorize_machdep(kauth_cred_get(), 520 KAUTH_MACHDEP_UNMANAGEDMEM, 521 NULL, NULL, NULL, NULL) != 0) { 522 aprint_normal("%s: mmap() rejected.\n", 523 device_xname(sc->sc_dev)); 524 return -1; 525 } 526 527 if ((offset >= sc->sc_fb) && (offset < (sc->sc_fb + sc->sc_fbsize))) { 528 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 529 BUS_SPACE_MAP_LINEAR); 530 return pa; 531 } 532 533 if ((offset >= sc->sc_reg) && 534 (offset < (sc->sc_reg + sc->sc_regsize))) { 535 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 536 BUS_SPACE_MAP_LINEAR); 537 return pa; 538 } 539 540 #ifdef PCI_MAGIC_IO_RANGE 541 /* allow mapping of IO space */ 542 if ((offset >= PCI_MAGIC_IO_RANGE) && 543 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 544 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 545 0, prot, BUS_SPACE_MAP_LINEAR); 546 return pa; 547 } 548 #endif 549 550 return -1; 551 } 552 553 static void 554 gffb_init_screen(void *cookie, struct vcons_screen *scr, 555 int existing, long *defattr) 556 { 557 struct gffb_softc *sc = cookie; 558 struct rasops_info *ri = &scr->scr_ri; 559 560 ri->ri_depth = sc->sc_depth; 561 ri->ri_width = sc->sc_width; 562 ri->ri_height = sc->sc_height; 563 ri->ri_stride = sc->sc_stride; 564 if (sc->sc_depth == 8) 565 ri->ri_bits = sc->sc_fbaddr + sc->sc_fboffset; 566 ri->ri_flg = RI_CENTER; 567 ri->ri_flg |= RI_8BIT_IS_RGB | RI_ENABLE_ALPHA; 568 569 rasops_init(ri, 0, 0); 570 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_RESIZE; 571 scr->scr_flags |= VCONS_LOADFONT; 572 573 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 574 sc->sc_width / ri->ri_font->fontwidth); 575 576 ri->ri_hw = scr; 577 578 if (sc->sc_accel) { 579 sc->sc_putchar = ri->ri_ops.putchar; 580 ri->ri_ops.copyrows = gffb_copyrows; 581 ri->ri_ops.copycols = gffb_copycols; 582 ri->ri_ops.eraserows = gffb_eraserows; 583 ri->ri_ops.erasecols = gffb_erasecols; 584 ri->ri_ops.cursor = gffb_cursor; 585 ri->ri_ops.putchar = gffb_putchar; 586 } else { 587 scr->scr_flags |= VCONS_DONT_READ; 588 } 589 } 590 591 static int 592 gffb_putcmap(struct gffb_softc *sc, struct wsdisplay_cmap *cm) 593 { 594 u_char *r, *g, *b; 595 u_int index = cm->index; 596 u_int count = cm->count; 597 int i, error; 598 u_char rbuf[256], gbuf[256], bbuf[256]; 599 600 #ifdef GFFB_DEBUG 601 aprint_debug("putcmap: %d %d\n",index, count); 602 #endif 603 if (cm->index >= 256 || cm->count > 256 || 604 (cm->index + cm->count) > 256) 605 return EINVAL; 606 error = copyin(cm->red, &rbuf[index], count); 607 if (error) 608 return error; 609 error = copyin(cm->green, &gbuf[index], count); 610 if (error) 611 return error; 612 error = copyin(cm->blue, &bbuf[index], count); 613 if (error) 614 return error; 615 616 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 617 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 618 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 619 620 r = &sc->sc_cmap_red[index]; 621 g = &sc->sc_cmap_green[index]; 622 b = &sc->sc_cmap_blue[index]; 623 624 for (i = 0; i < count; i++) { 625 gffb_putpalreg(sc, index, *r, *g, *b); 626 index++; 627 r++, g++, b++; 628 } 629 return 0; 630 } 631 632 static int 633 gffb_getcmap(struct gffb_softc *sc, struct wsdisplay_cmap *cm) 634 { 635 u_int index = cm->index; 636 u_int count = cm->count; 637 int error; 638 639 if (index >= 255 || count > 256 || index + count > 256) 640 return EINVAL; 641 642 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 643 if (error) 644 return error; 645 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 646 if (error) 647 return error; 648 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 649 if (error) 650 return error; 651 652 return 0; 653 } 654 655 static void 656 gffb_restore_palette(struct gffb_softc *sc) 657 { 658 int i; 659 660 for (i = 0; i < (1 << sc->sc_depth); i++) { 661 gffb_putpalreg(sc, i, sc->sc_cmap_red[i], 662 sc->sc_cmap_green[i], sc->sc_cmap_blue[i]); 663 } 664 } 665 666 static int 667 gffb_putpalreg(struct gffb_softc *sc, uint8_t idx, uint8_t r, uint8_t g, 668 uint8_t b) 669 { 670 /* port 0 */ 671 GFFB_WRITE_1(GFFB_PDIO0 + GFFB_PEL_IW, idx); 672 GFFB_WRITE_1(GFFB_PDIO0 + GFFB_PEL_D, r); 673 GFFB_WRITE_1(GFFB_PDIO0 + GFFB_PEL_D, g); 674 GFFB_WRITE_1(GFFB_PDIO0 + GFFB_PEL_D, b); 675 676 /* port 1 */ 677 GFFB_WRITE_1(GFFB_PDIO1 + GFFB_PEL_IW, idx); 678 GFFB_WRITE_1(GFFB_PDIO1 + GFFB_PEL_D, r); 679 GFFB_WRITE_1(GFFB_PDIO1 + GFFB_PEL_D, g); 680 GFFB_WRITE_1(GFFB_PDIO1 + GFFB_PEL_D, b); 681 682 return 0; 683 } 684 685 686 static void 687 gffb_dma_kickoff(struct gffb_softc *sc) 688 { 689 volatile uint32_t junk; 690 if (sc->sc_current != sc->sc_put) { 691 sc->sc_put = sc->sc_current; 692 bus_space_barrier(sc->sc_memt, sc->sc_fbh, 0, 0x1000000, 693 BUS_SPACE_BARRIER_WRITE); 694 junk = *sc->sc_fbaddr; 695 __USE(junk); 696 GFFB_WRITE_4(GFFB_FIFO_PUT, sc->sc_put); 697 bus_space_barrier(sc->sc_memt, sc->sc_regh, GFFB_FIFO_PUT, 4, 698 BUS_SPACE_BARRIER_WRITE); 699 } 700 } 701 702 static void 703 gffb_dmanext(struct gffb_softc *sc, uint32_t data) 704 { 705 bus_space_write_stream_4(sc->sc_memt, sc->sc_fbh, sc->sc_current, data); 706 sc->sc_current += 4; 707 } 708 709 static void 710 gffb_dmastart(struct gffb_softc *sc, uint32_t tag, int size) 711 { 712 if(sc->sc_free <= (size << 2)) 713 gffb_make_room(sc, size); 714 gffb_dmanext(sc, ((size) << 18) | (tag)); 715 sc->sc_free -= ((size + 1) << 2); 716 } 717 718 /* 719 * from xf86_video_nv/nv_xaa.c: 720 * There is a HW race condition with videoram command buffers. 721 * You can't jump to the location of your put offset. We write put 722 * at the jump offset + SKIPS dwords with noop padding in between 723 * to solve this problem 724 */ 725 726 #define SKIPS 8 727 728 static void 729 gffb_make_room(struct gffb_softc *sc, int size) 730 { 731 uint32_t get; 732 733 size = (size + 1) << 2; /* slots -> offset */ 734 735 while (sc->sc_free < size) { 736 get = GFFB_READ_4(GFFB_FIFO_GET); 737 738 if (sc->sc_put >= get) { 739 sc->sc_free = 0x2000 - sc->sc_current; 740 if (sc->sc_free < size) { 741 gffb_dmanext(sc, 0x20000000); 742 if(get <= (SKIPS << 2)) { 743 if (sc->sc_put <= (SKIPS << 2)) { 744 /* corner case - will be idle */ 745 GFFB_WRITE_4(GFFB_FIFO_PUT, 746 (SKIPS + 1) << 2); 747 } 748 do { 749 get =GFFB_READ_4(GFFB_FIFO_GET); 750 } while (get <= (SKIPS << 2)); 751 } 752 GFFB_WRITE_4(GFFB_FIFO_PUT, SKIPS << 2); 753 sc->sc_current = sc->sc_put = (SKIPS << 2); 754 sc->sc_free = get - ((SKIPS + 1) << 2); 755 } 756 } else 757 sc->sc_free = get - sc->sc_current - 4; 758 } 759 } 760 761 static void 762 gffb_sync(struct gffb_softc *sc) 763 { 764 int bail; 765 int i; 766 767 /* 768 * if there are commands in the buffer make sure the chip is actually 769 * trying to run them 770 */ 771 gffb_dma_kickoff(sc); 772 773 /* now wait for the command buffer to drain... */ 774 bail = 100000000; 775 while ((GFFB_READ_4(GFFB_FIFO_GET) != sc->sc_put) && (bail > 0)) { 776 bail--; 777 } 778 if (bail == 0) { 779 printf("FIFO isn't moving\n"); 780 goto crap; 781 } 782 783 /* ... and for the engine to go idle */ 784 bail = 100000000; 785 while((GFFB_READ_4(GFFB_BUSY) != 0) && (bail > 0)) { 786 bail--; 787 } 788 if (bail == 0) goto crap; 789 return; 790 crap: 791 /* if we time out fill the buffer with NOPs and cross fingers */ 792 DPRINTF("GET %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 793 sc->sc_put = 0; 794 sc->sc_current = 0; 795 for (i = 0; i < 0x2000; i += 4) 796 bus_space_write_stream_4(sc->sc_memt, sc->sc_fbh, i, 0); 797 aprint_error_dev(sc->sc_dev, "DMA lockup\n"); 798 } 799 800 void 801 gffb_init(struct gffb_softc *sc) 802 { 803 int i; 804 uint32_t foo; 805 806 if (!sc->sc_accel) return; 807 DPRINTF("%s offset %08x %08x\n", __func__, 808 GFFB_READ_4(GFFB_CRTC0 + GFFB_DISPLAYSTART), 809 GFFB_READ_4(GFFB_CRTC1 + GFFB_DISPLAYSTART)); 810 811 sc->sc_fboffset = 0x2000; 812 813 /* init display start */ 814 GFFB_WRITE_4(GFFB_CRTC0 + GFFB_DISPLAYSTART, sc->sc_fboffset); 815 GFFB_WRITE_4(GFFB_CRTC1 + GFFB_DISPLAYSTART, sc->sc_fboffset); 816 817 /* make sure we do 8bit per channel */ 818 GFFB_WRITE_1(GFFB_PDIO0 + GFFB_PEL_MASK, 0xff); 819 GFFB_WRITE_1(GFFB_PDIO1 + GFFB_PEL_MASK, 0xff); 820 821 /* DMA stuff. A whole lot of magic number voodoo from xf86-video-nv */ 822 GFFB_WRITE_4(GFFB_PMC + 0x140, 0); 823 GFFB_WRITE_4(GFFB_PMC + 0x200, 0xffff00ff); 824 GFFB_WRITE_4(GFFB_PMC + 0x200, 0xffffffff); 825 GFFB_WRITE_4(GFFB_PTIMER + 0x800, 8); 826 GFFB_WRITE_4(GFFB_PTIMER + 0x840, 3); 827 GFFB_WRITE_4(GFFB_PTIMER + 0x500, 0); 828 GFFB_WRITE_4(GFFB_PTIMER + 0x400, 0xffffffff); 829 for (i = 0; i < 8; i++) { 830 GFFB_WRITE_4(GFFB_PFB + 0x0240 + (i * 0x10), 0); 831 GFFB_WRITE_4(GFFB_PFB + 0x0244 + (i * 0x10), 832 sc->sc_vramsize - 1); 833 } 834 835 GFFB_WRITE_4(GFFB_PRAMIN, 0x80000010); 836 GFFB_WRITE_4(GFFB_PRAMIN + 0x04, 0x80011201); 837 GFFB_WRITE_4(GFFB_PRAMIN + 0x08, 0x80000011); 838 GFFB_WRITE_4(GFFB_PRAMIN + 0x0c, 0x80011202); 839 GFFB_WRITE_4(GFFB_PRAMIN + 0x10, 0x80000012); 840 GFFB_WRITE_4(GFFB_PRAMIN + 0x14, 0x80011203); 841 GFFB_WRITE_4(GFFB_PRAMIN + 0x18, 0x80000013); 842 GFFB_WRITE_4(GFFB_PRAMIN + 0x1c, 0x80011204); 843 GFFB_WRITE_4(GFFB_PRAMIN + 0x20, 0x80000014); 844 GFFB_WRITE_4(GFFB_PRAMIN + 0x24, 0x80011205); 845 GFFB_WRITE_4(GFFB_PRAMIN + 0x28, 0x80000015); 846 GFFB_WRITE_4(GFFB_PRAMIN + 0x2c, 0x80011206); 847 GFFB_WRITE_4(GFFB_PRAMIN + 0x30, 0x80000016); 848 GFFB_WRITE_4(GFFB_PRAMIN + 0x34, 0x80011207); 849 GFFB_WRITE_4(GFFB_PRAMIN + 0x38, 0x80000017); 850 GFFB_WRITE_4(GFFB_PRAMIN + 0x3c, 0x80011208); 851 GFFB_WRITE_4(GFFB_PRAMIN + 0x2000, 0x00003000); 852 GFFB_WRITE_4(GFFB_PRAMIN + 0x2004, sc->sc_vramsize - 1); 853 GFFB_WRITE_4(GFFB_PRAMIN + 0x2008, 0x00000002); 854 GFFB_WRITE_4(GFFB_PRAMIN + 0x200c, 0x00000002); 855 GFFB_WRITE_4(GFFB_PRAMIN + 0x2010, 0x01008062); /* nv10+ */ 856 GFFB_WRITE_4(GFFB_PRAMIN + 0x2014, 0); 857 GFFB_WRITE_4(GFFB_PRAMIN + 0x2018, 0x12001200); 858 GFFB_WRITE_4(GFFB_PRAMIN + 0x201c, 0); 859 GFFB_WRITE_4(GFFB_PRAMIN + 0x2020, 0x01008043); 860 GFFB_WRITE_4(GFFB_PRAMIN + 0x2024, 0); 861 GFFB_WRITE_4(GFFB_PRAMIN + 0x2028, 0); 862 GFFB_WRITE_4(GFFB_PRAMIN + 0x202c, 0); 863 GFFB_WRITE_4(GFFB_PRAMIN + 0x2030, 0x01008044); 864 GFFB_WRITE_4(GFFB_PRAMIN + 0x2034, 0x00000002); 865 GFFB_WRITE_4(GFFB_PRAMIN + 0x2038, 0); 866 GFFB_WRITE_4(GFFB_PRAMIN + 0x203c, 0); 867 GFFB_WRITE_4(GFFB_PRAMIN + 0x2040, 0x01008019); 868 GFFB_WRITE_4(GFFB_PRAMIN + 0x2044, 0); 869 GFFB_WRITE_4(GFFB_PRAMIN + 0x2048, 0); 870 GFFB_WRITE_4(GFFB_PRAMIN + 0x204c, 0); 871 GFFB_WRITE_4(GFFB_PRAMIN + 0x2050, 0x0100a05c); 872 GFFB_WRITE_4(GFFB_PRAMIN + 0x2054, 0); 873 GFFB_WRITE_4(GFFB_PRAMIN + 0x2058, 0); 874 GFFB_WRITE_4(GFFB_PRAMIN + 0x205c, 0); 875 /* XXX 0x0100805f if !WaitVSynvPossible */ 876 GFFB_WRITE_4(GFFB_PRAMIN + 0x2060, 0x0100805f); 877 GFFB_WRITE_4(GFFB_PRAMIN + 0x2064, 0); 878 GFFB_WRITE_4(GFFB_PRAMIN + 0x2068, 0x12001200); 879 GFFB_WRITE_4(GFFB_PRAMIN + 0x206c, 0); 880 GFFB_WRITE_4(GFFB_PRAMIN + 0x2070, 0x0100804a); 881 GFFB_WRITE_4(GFFB_PRAMIN + 0x2074, 0x00000002); 882 GFFB_WRITE_4(GFFB_PRAMIN + 0x2078, 0); 883 GFFB_WRITE_4(GFFB_PRAMIN + 0x207c, 0); 884 GFFB_WRITE_4(GFFB_PRAMIN + 0x2080, 0x01018077); 885 GFFB_WRITE_4(GFFB_PRAMIN + 0x2084, 0); 886 GFFB_WRITE_4(GFFB_PRAMIN + 0x2088, 0x12001200); 887 GFFB_WRITE_4(GFFB_PRAMIN + 0x208c, 0); 888 GFFB_WRITE_4(GFFB_PRAMIN + 0x2090, 0x00003002); 889 GFFB_WRITE_4(GFFB_PRAMIN + 0x2094, 0x00007fff); 890 /* command buffer start with some flag in the lower bits */ 891 GFFB_WRITE_4(GFFB_PRAMIN + 0x2098, sc->sc_vramsize | 0x00000002); 892 GFFB_WRITE_4(GFFB_PRAMIN + 0x209c, 0x00000002); 893 #if BYTE_ORDER == BIG_ENDIAN 894 GFFB_WRITE_4(GFFB_PRAMIN + 0x2010, 0x01088062); 895 GFFB_WRITE_4(GFFB_PRAMIN + 0x2020, 0x01088043); 896 GFFB_WRITE_4(GFFB_PRAMIN + 0x2030, 0x01088044); 897 GFFB_WRITE_4(GFFB_PRAMIN + 0x2040, 0x01088019); 898 GFFB_WRITE_4(GFFB_PRAMIN + 0x2050, 0x0108a05c); 899 GFFB_WRITE_4(GFFB_PRAMIN + 0x2060, 0x0108805f); 900 GFFB_WRITE_4(GFFB_PRAMIN + 0x2070, 0x0108804a); 901 GFFB_WRITE_4(GFFB_PRAMIN + 0x2080, 0x01098077); 902 GFFB_WRITE_4(GFFB_PRAMIN + 0x2034, 0x00000001); 903 GFFB_WRITE_4(GFFB_PRAMIN + 0x2074, 0x00000001); 904 #endif 905 /* PGRAPH setup */ 906 GFFB_WRITE_4(GFFB_PGRAPH + 0x0080, 0xFFFFFFFF); 907 GFFB_WRITE_4(GFFB_PGRAPH + 0x0080, 0x00000000); 908 909 GFFB_WRITE_4(GFFB_PGRAPH + 0x0140, 0x00000000); 910 GFFB_WRITE_4(GFFB_PGRAPH + 0x0100, 0xFFFFFFFF); 911 GFFB_WRITE_4(GFFB_PGRAPH + 0x0144, 0x10010100); 912 GFFB_WRITE_4(GFFB_PGRAPH + 0x0714, 0xFFFFFFFF); 913 GFFB_WRITE_4(GFFB_PGRAPH + 0x0720, 0x00000001); 914 /* 915 * xf86_video_nv does this in two writes, 916 * not sure if they can be combined 917 */ 918 foo = GFFB_READ_4(GFFB_PGRAPH + 0x0710); 919 foo &= 0x0007ff00; 920 foo |= 0x00020100; 921 GFFB_WRITE_4(GFFB_PGRAPH + 0x0710, foo); 922 923 /* NV_ARCH_10 */ 924 if(sc->sc_arch == 10) { 925 GFFB_WRITE_4(GFFB_PGRAPH + 0x0084, 0x00118700); 926 GFFB_WRITE_4(GFFB_PGRAPH + 0x0088, 0x24E00810); 927 GFFB_WRITE_4(GFFB_PGRAPH + 0x008C, 0x55DE0030); 928 929 for(i = 0; i < 128; i += 4) { 930 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B00 + i, 931 GFFB_READ_4(GFFB_PFB + 0x0240 + i)); 932 } 933 934 GFFB_WRITE_4(GFFB_PGRAPH + 0x640, 0); 935 GFFB_WRITE_4(GFFB_PGRAPH + 0x644, 0); 936 GFFB_WRITE_4(GFFB_PGRAPH + 0x684, sc->sc_vramsize - 1); 937 GFFB_WRITE_4(GFFB_PGRAPH + 0x688, sc->sc_vramsize - 1); 938 939 GFFB_WRITE_4(GFFB_PGRAPH + 0x0810, 0x00000000); 940 GFFB_WRITE_4(GFFB_PGRAPH + 0x0608, 0xFFFFFFFF); 941 } else { 942 /* nv30 */ 943 GFFB_WRITE_4(GFFB_PGRAPH + 0x0084, 0x40108700); 944 GFFB_WRITE_4(GFFB_PGRAPH + 0x0890, 0x00140000); 945 GFFB_WRITE_4(GFFB_PGRAPH + 0x008C, 0xf00e0431); 946 GFFB_WRITE_4(GFFB_PGRAPH + 0x0090, 0x00008000); 947 GFFB_WRITE_4(GFFB_PGRAPH + 0x0610, 0xf04b1f36); 948 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B80, 0x1002d888); 949 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B88, 0x62ff007f); 950 951 for (i = 0; i < 128; i += 4) { 952 GFFB_WRITE_4(GFFB_PGRAPH + 0x0900 + i, 953 GFFB_READ_4(GFFB_PFB + 0x0240 + i)); 954 GFFB_WRITE_4(GFFB_PGRAPH + 0x6900 + i, 955 GFFB_READ_4(GFFB_PFB + 0x0240 + i)); 956 } 957 958 GFFB_WRITE_4(GFFB_PGRAPH + 0x09A4, 959 GFFB_READ_4(GFFB_PFB + 0x0200)); 960 GFFB_WRITE_4(GFFB_PGRAPH + 0x09A8, 961 GFFB_READ_4(GFFB_PFB + 0x0204)); 962 GFFB_WRITE_4(GFFB_PGRAPH + 0x0750, 0x00EA0000); 963 GFFB_WRITE_4(GFFB_PGRAPH + 0x0754, 964 GFFB_READ_4(GFFB_PFB + 0x0200)); 965 GFFB_WRITE_4(GFFB_PGRAPH + 0x0750, 0x00EA0004); 966 GFFB_WRITE_4(GFFB_PGRAPH + 0x0754, 967 GFFB_READ_4(GFFB_PFB + 0x0204)); 968 969 GFFB_WRITE_4(GFFB_PGRAPH + 0x0820, 0); 970 GFFB_WRITE_4(GFFB_PGRAPH + 0x0824, 0); 971 GFFB_WRITE_4(GFFB_PGRAPH + 0x0864, sc->sc_vramsize - 1); 972 GFFB_WRITE_4(GFFB_PGRAPH + 0x0868, sc->sc_vramsize - 1); 973 974 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B20, 0x00000000); 975 GFFB_WRITE_4(GFFB_PGRAPH + 0x0B04, 0xFFFFFFFF); 976 } 977 978 /* PFIFO setup */ 979 GFFB_WRITE_4(GFFB_PGRAPH + 0x053C, 0); 980 GFFB_WRITE_4(GFFB_PGRAPH + 0x0540, 0); 981 GFFB_WRITE_4(GFFB_PGRAPH + 0x0544, 0x00007FFF); 982 GFFB_WRITE_4(GFFB_PGRAPH + 0x0548, 0x00007FFF); 983 984 GFFB_WRITE_4(GFFB_PFIFO + 0x0500, 0); 985 GFFB_WRITE_4(GFFB_PFIFO + 0x0504, 0x00000001); 986 GFFB_WRITE_4(GFFB_PFIFO + 0x1200, 0); 987 GFFB_WRITE_4(GFFB_PFIFO + 0x1250, 0); 988 GFFB_WRITE_4(GFFB_PFIFO + 0x1204, 0x00000100); /* different on nv40 */ 989 GFFB_WRITE_4(GFFB_PFIFO + 0x1240, 0); 990 GFFB_WRITE_4(GFFB_PFIFO + 0x1244, 0); 991 GFFB_WRITE_4(GFFB_PFIFO + 0x122c, 0x00001209); /* different on nv40 */ 992 GFFB_WRITE_4(GFFB_PFIFO + 0x1000, 0); 993 GFFB_WRITE_4(GFFB_PFIFO + 0x1050, 0); 994 GFFB_WRITE_4(GFFB_PFIFO + 0x0210, 0x03000100); 995 GFFB_WRITE_4(GFFB_PFIFO + 0x0214, 0x00000110); 996 GFFB_WRITE_4(GFFB_PFIFO + 0x0218, 0x00000112); 997 GFFB_WRITE_4(GFFB_PFIFO + 0x050c, 0x0000ffff); 998 GFFB_WRITE_4(GFFB_PFIFO + 0x1258, 0x0000ffff); 999 GFFB_WRITE_4(GFFB_PFIFO + 0x0140, 0); 1000 GFFB_WRITE_4(GFFB_PFIFO + 0x0100, 0xffffffff); 1001 GFFB_WRITE_4(GFFB_PFIFO + 0x1054, 0x00000001); 1002 GFFB_WRITE_4(GFFB_PFIFO + 0x1230, 0); 1003 GFFB_WRITE_4(GFFB_PFIFO + 0x1280, 0); 1004 #if BYTE_ORDER == BIG_ENDIAN 1005 GFFB_WRITE_4(GFFB_PFIFO + 0x1224, 0x800f0078); 1006 #else 1007 GFFB_WRITE_4(GFFB_PFIFO + 0x1224, 0x000f0078); 1008 #endif 1009 GFFB_WRITE_4(GFFB_PFIFO + 0x1220, 0x00000001); 1010 GFFB_WRITE_4(GFFB_PFIFO + 0x1200, 0x00000001); 1011 GFFB_WRITE_4(GFFB_PFIFO + 0x1250, 0x00000001); 1012 GFFB_WRITE_4(GFFB_PFIFO + 0x1254, 0x00000001); 1013 GFFB_WRITE_4(GFFB_PFIFO + 0x0500, 0x00000001); 1014 1015 GFFB_WRITE_4(GFFB_PMC + 0x8704, 1); 1016 GFFB_WRITE_4(GFFB_PMC + 0x8140, 0); 1017 GFFB_WRITE_4(GFFB_PMC + 0x8920, 0); 1018 GFFB_WRITE_4(GFFB_PMC + 0x8924, 0); 1019 GFFB_WRITE_4(GFFB_PMC + 0x8908, sc->sc_vramsize - 1); 1020 GFFB_WRITE_4(GFFB_PMC + 0x890C, sc->sc_vramsize - 1); 1021 GFFB_WRITE_4(GFFB_PMC + 0x1588, 0); 1022 1023 __asm("eieio; sync;"); 1024 GFFB_WRITE_4(GFFB_FIFO_GET, 0); 1025 GFFB_WRITE_4(GFFB_CMDSTART, 0x00000002); 1026 sc->sc_put = 0; 1027 sc->sc_current = 0; 1028 sc->sc_free = 0x2000; 1029 1030 for(i = 0; i < SKIPS; i++) 1031 gffb_dmanext(sc, 0); 1032 1033 gffb_dmanext(sc, 0x00040000); 1034 gffb_dmanext(sc, 0x80000010); 1035 gffb_dmanext(sc, 0x00042000); 1036 gffb_dmanext(sc, 0x80000011); 1037 gffb_dmanext(sc, 0x00044000); 1038 gffb_dmanext(sc, 0x80000012); 1039 gffb_dmanext(sc, 0x00046000); 1040 gffb_dmanext(sc, 0x80000013); 1041 gffb_dmanext(sc, 0x00048000); 1042 gffb_dmanext(sc, 0x80000014); 1043 gffb_dmanext(sc, 0x0004A000); 1044 gffb_dmanext(sc, 0x80000015); 1045 gffb_dmanext(sc, 0x0004C000); 1046 gffb_dmanext(sc, 0x80000016); 1047 gffb_dmanext(sc, 0x0004E000); 1048 gffb_dmanext(sc, 0x80000017); 1049 sc->sc_free = 0x2000 - sc->sc_current; 1050 1051 gffb_dmastart(sc, SURFACE_FORMAT, 4); 1052 gffb_dmanext(sc, SURFACE_FORMAT_DEPTH8); 1053 gffb_dmanext(sc, sc->sc_stride | (sc->sc_stride << 16)); 1054 gffb_dmanext(sc, sc->sc_fboffset); /* src offset */ 1055 gffb_dmanext(sc, sc->sc_fboffset); /* dst offset */ 1056 1057 gffb_dmastart(sc, RECT_FORMAT, 1); 1058 gffb_dmanext(sc, RECT_FORMAT_DEPTH8); 1059 1060 gffb_dmastart(sc, PATTERN_FORMAT, 1); 1061 gffb_dmanext(sc, PATTERN_FORMAT_DEPTH8); 1062 1063 gffb_dmastart(sc, PATTERN_COLOR_0, 4); 1064 gffb_dmanext(sc, 0xffffffff); 1065 gffb_dmanext(sc, 0xffffffff); 1066 gffb_dmanext(sc, 0xffffffff); 1067 gffb_dmanext(sc, 0xffffffff); 1068 1069 gffb_dmastart(sc, ROP_SET, 1); 1070 gffb_dmanext(sc, 0xcc); 1071 sc->sc_rop = 0xcc; 1072 DPRINTF("put %x current %x\n", sc->sc_put, sc->sc_current); 1073 1074 gffb_dma_kickoff(sc); 1075 DPRINTF("put %x current %x\n", sc->sc_put, sc->sc_current); 1076 #ifdef GFFB_DEBUG 1077 printf("put: %08x\n", GFFB_READ_4(GFFB_FIFO_PUT)); 1078 printf("get: %08x\n", GFFB_READ_4(GFFB_FIFO_GET)); 1079 #endif 1080 gffb_sync(sc); 1081 DPRINTF("put %x current %x\n", sc->sc_put, sc->sc_current); 1082 } 1083 1084 static void 1085 gffb_rop(struct gffb_softc *sc, int rop) 1086 { 1087 if (rop == sc->sc_rop) 1088 return; 1089 sc->sc_rop = rop; 1090 gffb_dmastart(sc, ROP_SET, 1); 1091 gffb_dmanext(sc, rop); 1092 } 1093 1094 static void 1095 gffb_rectfill(struct gffb_softc *sc, int x, int y, int wi, int he, 1096 uint32_t colour) 1097 { 1098 if (!sc->sc_accel) return; 1099 mutex_enter(&sc->sc_lock); 1100 gffb_rop(sc, 0xcc); 1101 1102 gffb_dmastart(sc, RECT_SOLID_COLOR, 1); 1103 gffb_dmanext(sc, colour); 1104 1105 gffb_dmastart(sc, RECT_SOLID_RECTS(0), 2); 1106 gffb_dmanext(sc, (x << 16) | y); 1107 gffb_dmanext(sc, (wi << 16) | he); 1108 gffb_dma_kickoff(sc); 1109 mutex_exit(&sc->sc_lock); 1110 } 1111 1112 static void 1113 gffb_bitblt(void *cookie, int xs, int ys, int xd, int yd, 1114 int wi, int he, int rop) 1115 { 1116 struct gffb_softc *sc = cookie; 1117 1118 if (!sc->sc_accel) return; 1119 mutex_enter(&sc->sc_lock); 1120 1121 gffb_rop(sc, rop); 1122 1123 gffb_dmastart(sc, BLIT_POINT_SRC, 3); 1124 gffb_dmanext(sc, (ys << 16) | xs); 1125 gffb_dmanext(sc, (yd << 16) | xd); 1126 gffb_dmanext(sc, (he << 16) | wi); 1127 gffb_dma_kickoff(sc); 1128 mutex_exit(&sc->sc_lock); 1129 } 1130 1131 static void 1132 gffb_cursor(void *cookie, int on, int row, int col) 1133 { 1134 struct rasops_info *ri = cookie; 1135 struct vcons_screen *scr = ri->ri_hw; 1136 struct gffb_softc *sc = scr->scr_cookie; 1137 int x, y, wi, he; 1138 1139 wi = ri->ri_font->fontwidth; 1140 he = ri->ri_font->fontheight; 1141 1142 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1143 x = ri->ri_ccol * wi + ri->ri_xorigin; 1144 y = ri->ri_crow * he + ri->ri_yorigin; 1145 if (ri->ri_flg & RI_CURSOR) { 1146 gffb_bitblt(sc, x, y, x, y, wi, he, 0x33); 1147 ri->ri_flg &= ~RI_CURSOR; 1148 } 1149 ri->ri_crow = row; 1150 ri->ri_ccol = col; 1151 if (on) { 1152 x = ri->ri_ccol * wi + ri->ri_xorigin; 1153 y = ri->ri_crow * he + ri->ri_yorigin; 1154 gffb_bitblt(sc, x, y, x, y, wi, he, 0x33); 1155 ri->ri_flg |= RI_CURSOR; 1156 } 1157 } else { 1158 scr->scr_ri.ri_crow = row; 1159 scr->scr_ri.ri_ccol = col; 1160 scr->scr_ri.ri_flg &= ~RI_CURSOR; 1161 } 1162 1163 } 1164 1165 static void 1166 gffb_putchar(void *cookie, int row, int col, u_int c, long attr) 1167 { 1168 struct rasops_info *ri = cookie; 1169 struct wsdisplay_font *font = PICK_FONT(ri, c); 1170 struct vcons_screen *scr = ri->ri_hw; 1171 struct gffb_softc *sc = scr->scr_cookie; 1172 int x, y, wi, he, rv = GC_NOPE; 1173 uint32_t bg; 1174 1175 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1176 return; 1177 1178 if (!CHAR_IN_FONT(c, font)) 1179 return; 1180 1181 wi = font->fontwidth; 1182 he = font->fontheight; 1183 1184 x = ri->ri_xorigin + col * wi; 1185 y = ri->ri_yorigin + row * he; 1186 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1187 1188 if (c == 0x20) { 1189 gffb_rectfill(sc, x, y, wi, he, bg); 1190 return; 1191 } 1192 rv = glyphcache_try(&sc->sc_gc, c, x, y, attr); 1193 if (rv == GC_OK) 1194 return; 1195 1196 /* 1197 * Use gffb_sync to wait for the engine to become idle before 1198 * we start scribbling into VRAM -- we wouldn't want to stomp on 1199 * a scroll in progress or a prior glyphcache_add that hasn't 1200 * completed yet on the GPU. 1201 */ 1202 mutex_enter(&sc->sc_lock); 1203 gffb_sync(sc); 1204 sc->sc_putchar(cookie, row, col, c, attr); 1205 mutex_exit(&sc->sc_lock); 1206 1207 /* 1208 * If glyphcache_try asked us to, cache the newly written 1209 * character. This will issue a gffb_bitblt which will wait 1210 * for our CPU writes to the framebuffer in VRAM to complete 1211 * before triggering GPU reads from the framebuffer in VRAM. 1212 */ 1213 if (rv == GC_ADD) { 1214 glyphcache_add(&sc->sc_gc, c, x, y); 1215 } 1216 } 1217 1218 static void 1219 gffb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 1220 { 1221 struct rasops_info *ri = cookie; 1222 struct vcons_screen *scr = ri->ri_hw; 1223 struct gffb_softc *sc = scr->scr_cookie; 1224 int32_t xs, xd, y, width, height; 1225 1226 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1227 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 1228 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 1229 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1230 width = ri->ri_font->fontwidth * ncols; 1231 height = ri->ri_font->fontheight; 1232 gffb_bitblt(sc, xs, y, xd, y, width, height, 0xcc); 1233 } 1234 } 1235 1236 static void 1237 gffb_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 1238 { 1239 struct rasops_info *ri = cookie; 1240 struct vcons_screen *scr = ri->ri_hw; 1241 struct gffb_softc *sc = scr->scr_cookie; 1242 int32_t x, y, width, height, fg, bg, ul; 1243 1244 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1245 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 1246 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1247 width = ri->ri_font->fontwidth * ncols; 1248 height = ri->ri_font->fontheight; 1249 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1250 1251 gffb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1252 } 1253 } 1254 1255 static void 1256 gffb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 1257 { 1258 struct rasops_info *ri = cookie; 1259 struct vcons_screen *scr = ri->ri_hw; 1260 struct gffb_softc *sc = scr->scr_cookie; 1261 int32_t x, ys, yd, width, height; 1262 1263 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1264 x = ri->ri_xorigin; 1265 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 1266 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 1267 width = ri->ri_emuwidth; 1268 height = ri->ri_font->fontheight * nrows; 1269 gffb_bitblt(sc, x, ys, x, yd, width, height, 0xcc); 1270 } 1271 } 1272 1273 static void 1274 gffb_eraserows(void *cookie, int row, int nrows, long fillattr) 1275 { 1276 struct rasops_info *ri = cookie; 1277 struct vcons_screen *scr = ri->ri_hw; 1278 struct gffb_softc *sc = scr->scr_cookie; 1279 int32_t x, y, width, height, fg, bg, ul; 1280 1281 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 1282 x = ri->ri_xorigin; 1283 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 1284 width = ri->ri_emuwidth; 1285 height = ri->ri_font->fontheight * nrows; 1286 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 1287 1288 gffb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 1289 } 1290 } 1291
Indexes created Mon Sep 29 21:09:56 GMT 2025