hptide.c revision 1.10.2.7
1 1.10.2.7 skrll /* $NetBSD: hptide.c,v 1.10.2.7 2005/11/10 14:06:01 skrll Exp $ */ 2 1.10.2.2 skrll 3 1.10.2.2 skrll /* 4 1.10.2.2 skrll * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 1.10.2.2 skrll * 6 1.10.2.2 skrll * Redistribution and use in source and binary forms, with or without 7 1.10.2.2 skrll * modification, are permitted provided that the following conditions 8 1.10.2.2 skrll * are met: 9 1.10.2.2 skrll * 1. Redistributions of source code must retain the above copyright 10 1.10.2.2 skrll * notice, this list of conditions and the following disclaimer. 11 1.10.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.10.2.2 skrll * notice, this list of conditions and the following disclaimer in the 13 1.10.2.2 skrll * documentation and/or other materials provided with the distribution. 14 1.10.2.2 skrll * 3. All advertising materials mentioning features or use of this software 15 1.10.2.2 skrll * must display the following acknowledgement: 16 1.10.2.2 skrll * This product includes software developed by Manuel Bouyer. 17 1.10.2.2 skrll * 4. The name of the author may not be used to endorse or promote products 18 1.10.2.2 skrll * derived from this software without specific prior written permission. 19 1.10.2.2 skrll * 20 1.10.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 1.10.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 1.10.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 1.10.2.6 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 1.10.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 1.10.2.2 skrll * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.10.2.2 skrll * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 1.10.2.2 skrll * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 1.10.2.2 skrll * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 1.10.2.2 skrll * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 1.10.2.2 skrll */ 31 1.10.2.2 skrll 32 1.10.2.7 skrll #include <sys/cdefs.h> 33 1.10.2.7 skrll __KERNEL_RCSID(0, "$NetBSD: hptide.c,v 1.10.2.7 2005/11/10 14:06:01 skrll Exp $"); 34 1.10.2.7 skrll 35 1.10.2.2 skrll #include <sys/param.h> 36 1.10.2.2 skrll #include <sys/systm.h> 37 1.10.2.2 skrll 38 1.10.2.2 skrll #include <dev/pci/pcivar.h> 39 1.10.2.2 skrll #include <dev/pci/pcidevs.h> 40 1.10.2.2 skrll #include <dev/pci/pciidereg.h> 41 1.10.2.2 skrll #include <dev/pci/pciidevar.h> 42 1.10.2.2 skrll #include <dev/pci/pciide_hpt_reg.h> 43 1.10.2.2 skrll 44 1.10.2.2 skrll static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*); 45 1.10.2.3 skrll static void hpt_setup_channel(struct ata_channel*); 46 1.10.2.2 skrll static int hpt_pci_intr(void *); 47 1.10.2.2 skrll 48 1.10.2.2 skrll static int hptide_match(struct device *, struct cfdata *, void *); 49 1.10.2.2 skrll static void hptide_attach(struct device *, struct device *, void *); 50 1.10.2.2 skrll 51 1.10.2.2 skrll CFATTACH_DECL(hptide, sizeof(struct pciide_softc), 52 1.10.2.2 skrll hptide_match, hptide_attach, NULL, NULL); 53 1.10.2.2 skrll 54 1.10.2.2 skrll static const struct pciide_product_desc pciide_triones_products[] = { 55 1.10.2.2 skrll { PCI_PRODUCT_TRIONES_HPT302, 56 1.10.2.2 skrll 0, 57 1.10.2.2 skrll NULL, 58 1.10.2.2 skrll hpt_chip_map 59 1.10.2.2 skrll }, 60 1.10.2.2 skrll { PCI_PRODUCT_TRIONES_HPT366, 61 1.10.2.2 skrll 0, 62 1.10.2.2 skrll NULL, 63 1.10.2.2 skrll hpt_chip_map, 64 1.10.2.2 skrll }, 65 1.10.2.2 skrll { PCI_PRODUCT_TRIONES_HPT371, 66 1.10.2.2 skrll 0, 67 1.10.2.2 skrll NULL, 68 1.10.2.2 skrll hpt_chip_map, 69 1.10.2.2 skrll }, 70 1.10.2.2 skrll { PCI_PRODUCT_TRIONES_HPT372A, 71 1.10.2.2 skrll 0, 72 1.10.2.2 skrll NULL, 73 1.10.2.2 skrll hpt_chip_map 74 1.10.2.2 skrll }, 75 1.10.2.2 skrll { PCI_PRODUCT_TRIONES_HPT374, 76 1.10.2.2 skrll 0, 77 1.10.2.2 skrll NULL, 78 1.10.2.2 skrll hpt_chip_map 79 1.10.2.2 skrll }, 80 1.10.2.2 skrll { 0, 81 1.10.2.2 skrll 0, 82 1.10.2.2 skrll NULL, 83 1.10.2.2 skrll NULL 84 1.10.2.2 skrll } 85 1.10.2.2 skrll }; 86 1.10.2.2 skrll 87 1.10.2.2 skrll static int 88 1.10.2.2 skrll hptide_match(struct device *parent, struct cfdata *match, void *aux) 89 1.10.2.2 skrll { 90 1.10.2.2 skrll struct pci_attach_args *pa = aux; 91 1.10.2.2 skrll 92 1.10.2.2 skrll if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) { 93 1.10.2.2 skrll if (pciide_lookup_product(pa->pa_id, pciide_triones_products)) 94 1.10.2.2 skrll return (2); 95 1.10.2.2 skrll } 96 1.10.2.2 skrll return (0); 97 1.10.2.2 skrll } 98 1.10.2.2 skrll 99 1.10.2.2 skrll static void 100 1.10.2.2 skrll hptide_attach(struct device *parent, struct device *self, void *aux) 101 1.10.2.2 skrll { 102 1.10.2.2 skrll struct pci_attach_args *pa = aux; 103 1.10.2.2 skrll struct pciide_softc *sc = (struct pciide_softc *)self; 104 1.10.2.2 skrll 105 1.10.2.2 skrll pciide_common_attach(sc, pa, 106 1.10.2.2 skrll pciide_lookup_product(pa->pa_id, pciide_triones_products)); 107 1.10.2.2 skrll 108 1.10.2.2 skrll } 109 1.10.2.2 skrll 110 1.10.2.2 skrll static void 111 1.10.2.2 skrll hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 112 1.10.2.2 skrll { 113 1.10.2.2 skrll struct pciide_channel *cp; 114 1.10.2.2 skrll int i, compatchan, revision; 115 1.10.2.2 skrll pcireg_t interface; 116 1.10.2.2 skrll bus_size_t cmdsize, ctlsize; 117 1.10.2.2 skrll 118 1.10.2.2 skrll if (pciide_chipen(sc, pa) == 0) 119 1.10.2.2 skrll return; 120 1.10.2.2 skrll 121 1.10.2.2 skrll revision = PCI_REVISION(pa->pa_class); 122 1.10.2.2 skrll aprint_normal("%s: Triones/Highpoint ", 123 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 124 1.10.2.2 skrll switch (sc->sc_pp->ide_product) { 125 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT302: 126 1.10.2.2 skrll aprint_normal("HPT302 IDE Controller\n"); 127 1.10.2.2 skrll break; 128 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT371: 129 1.10.2.2 skrll aprint_normal("HPT371 IDE Controller\n"); 130 1.10.2.2 skrll break; 131 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT374: 132 1.10.2.2 skrll aprint_normal("HPT374 IDE Controller\n"); 133 1.10.2.2 skrll break; 134 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT372A: 135 1.10.2.2 skrll aprint_normal("HPT372A IDE Controller\n"); 136 1.10.2.2 skrll break; 137 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT366: 138 1.10.2.2 skrll if (revision == HPT372_REV) 139 1.10.2.2 skrll aprint_normal("HPT372 IDE Controller\n"); 140 1.10.2.2 skrll else if (revision == HPT370_REV) 141 1.10.2.2 skrll aprint_normal("HPT370 IDE Controller\n"); 142 1.10.2.2 skrll else if (revision == HPT370A_REV) 143 1.10.2.2 skrll aprint_normal("HPT370A IDE Controller\n"); 144 1.10.2.2 skrll else if (revision == HPT366_REV) 145 1.10.2.2 skrll aprint_normal("HPT366 IDE Controller\n"); 146 1.10.2.2 skrll else 147 1.10.2.2 skrll aprint_normal("unknown HPT IDE controller rev %d\n", 148 1.10.2.2 skrll revision); 149 1.10.2.2 skrll break; 150 1.10.2.2 skrll default: 151 1.10.2.2 skrll aprint_normal("unknown HPT IDE controller 0x%x\n", 152 1.10.2.2 skrll sc->sc_pp->ide_product); 153 1.10.2.2 skrll } 154 1.10.2.2 skrll 155 1.10.2.6 skrll /* 156 1.10.2.2 skrll * when the chip is in native mode it identifies itself as a 157 1.10.2.2 skrll * 'misc mass storage'. Fake interface in this case. 158 1.10.2.2 skrll */ 159 1.10.2.2 skrll if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 160 1.10.2.2 skrll interface = PCI_INTERFACE(pa->pa_class); 161 1.10.2.2 skrll } else { 162 1.10.2.2 skrll interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 163 1.10.2.2 skrll PCIIDE_INTERFACE_PCI(0); 164 1.10.2.2 skrll if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 165 1.10.2.2 skrll (revision == HPT370_REV || revision == HPT370A_REV || 166 1.10.2.2 skrll revision == HPT372_REV)) || 167 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 168 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 169 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 170 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 171 1.10.2.2 skrll interface |= PCIIDE_INTERFACE_PCI(1); 172 1.10.2.2 skrll } 173 1.10.2.2 skrll 174 1.10.2.2 skrll aprint_normal("%s: bus-master DMA support present", 175 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 176 1.10.2.2 skrll pciide_mapreg_dma(sc, pa); 177 1.10.2.2 skrll aprint_normal("\n"); 178 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 179 1.10.2.2 skrll if (sc->sc_dma_ok) { 180 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 181 1.10.2.2 skrll sc->sc_wdcdev.irqack = pciide_irqack; 182 1.10.2.2 skrll } 183 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 184 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 185 1.10.2.2 skrll 186 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel; 187 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 188 1.10.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 189 1.10.2.2 skrll revision == HPT366_REV) { 190 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 191 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 192 1.10.2.2 skrll } else { 193 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 194 1.10.2.2 skrll if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 195 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 196 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 197 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 198 1.10.2.2 skrll (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 199 1.10.2.2 skrll revision == HPT372_REV)) 200 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 201 1.10.2.2 skrll else 202 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 203 1.10.2.2 skrll } 204 1.10.2.3 skrll 205 1.10.2.3 skrll wdc_allocate_regs(&sc->sc_wdcdev); 206 1.10.2.3 skrll 207 1.10.2.3 skrll for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 208 1.10.2.2 skrll cp = &sc->pciide_channels[i]; 209 1.10.2.3 skrll if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) { 210 1.10.2.2 skrll compatchan = i; 211 1.10.2.2 skrll if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 212 1.10.2.2 skrll HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 213 1.10.2.2 skrll aprint_normal( 214 1.10.2.2 skrll "%s: %s channel ignored (disabled)\n", 215 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 216 1.10.2.3 skrll cp->ata_channel.ch_flags |= ATACH_DISABLED; 217 1.10.2.2 skrll continue; 218 1.10.2.2 skrll } 219 1.10.2.2 skrll } else { 220 1.10.2.2 skrll /* 221 1.10.2.2 skrll * The 366 has 2 PCI IDE functions, one for primary and 222 1.10.2.2 skrll * one for secondary. So we need to call 223 1.10.2.2 skrll * pciide_mapregs_compat() with the real channel. 224 1.10.2.2 skrll */ 225 1.10.2.2 skrll if (pa->pa_function == 0) 226 1.10.2.2 skrll compatchan = 0; 227 1.10.2.2 skrll else if (pa->pa_function == 1) 228 1.10.2.2 skrll compatchan = 1; 229 1.10.2.2 skrll else { 230 1.10.2.2 skrll aprint_error("%s: unexpected PCI function %d\n", 231 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, pa->pa_function); 232 1.10.2.2 skrll return; 233 1.10.2.2 skrll } 234 1.10.2.2 skrll } 235 1.10.2.2 skrll if (pciide_chansetup(sc, i, interface) == 0) 236 1.10.2.2 skrll continue; 237 1.10.2.2 skrll if (interface & PCIIDE_INTERFACE_PCI(i)) { 238 1.10.2.2 skrll pciide_mapregs_native(pa, cp, &cmdsize, 239 1.10.2.2 skrll &ctlsize, hpt_pci_intr); 240 1.10.2.2 skrll } else { 241 1.10.2.2 skrll pciide_mapregs_compat(pa, cp, compatchan, 242 1.10.2.2 skrll &cmdsize, &ctlsize); 243 1.10.2.3 skrll if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 244 1.10.2.2 skrll pciide_map_compat_intr(pa, cp, 245 1.10.2.2 skrll sc->sc_cy_compatchan); 246 1.10.2.2 skrll } 247 1.10.2.3 skrll wdcattach(&cp->ata_channel); 248 1.10.2.2 skrll } 249 1.10.2.2 skrll if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 250 1.10.2.2 skrll (revision == HPT370_REV || revision == HPT370A_REV || 251 1.10.2.6 skrll revision == HPT372_REV)) || 252 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 253 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 254 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 255 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 256 1.10.2.2 skrll /* 257 1.10.2.2 skrll * HPT370_REV and highter has a bit to disable interrupts, 258 1.10.2.2 skrll * make sure to clear it 259 1.10.2.2 skrll */ 260 1.10.2.2 skrll pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 261 1.10.2.2 skrll pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 262 1.10.2.2 skrll ~HPT_CSEL_IRQDIS); 263 1.10.2.2 skrll } 264 1.10.2.2 skrll /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 265 1.10.2.2 skrll if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 266 1.10.2.2 skrll revision == HPT372_REV ) || 267 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 268 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 269 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 270 1.10.2.2 skrll sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 271 1.10.2.2 skrll pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 272 1.10.2.2 skrll (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 273 1.10.2.2 skrll HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 274 1.10.2.2 skrll return; 275 1.10.2.2 skrll } 276 1.10.2.2 skrll 277 1.10.2.2 skrll static void 278 1.10.2.3 skrll hpt_setup_channel(struct ata_channel *chp) 279 1.10.2.2 skrll { 280 1.10.2.2 skrll struct ata_drive_datas *drvp; 281 1.10.2.3 skrll int drive, s; 282 1.10.2.2 skrll int cable; 283 1.10.2.2 skrll u_int32_t before, after; 284 1.10.2.2 skrll u_int32_t idedma_ctl; 285 1.10.2.3 skrll struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 286 1.10.2.3 skrll struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 287 1.10.2.2 skrll int revision = 288 1.10.2.2 skrll PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 289 1.10.2.2 skrll const u_int32_t *tim_pio, *tim_dma, *tim_udma; 290 1.10.2.2 skrll 291 1.10.2.2 skrll cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 292 1.10.2.2 skrll 293 1.10.2.2 skrll /* setup DMA if needed */ 294 1.10.2.2 skrll pciide_channel_dma_setup(cp); 295 1.10.2.2 skrll 296 1.10.2.2 skrll idedma_ctl = 0; 297 1.10.2.2 skrll 298 1.10.2.2 skrll /* select the timing arrays for the chip */ 299 1.10.2.2 skrll switch (sc->sc_pp->ide_product) { 300 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT374: 301 1.10.2.2 skrll tim_udma = hpt374_udma; 302 1.10.2.2 skrll tim_dma = hpt374_dma; 303 1.10.2.2 skrll tim_pio = hpt374_pio; 304 1.10.2.2 skrll break; 305 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT302: 306 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT371: 307 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT372A: 308 1.10.2.2 skrll tim_udma = hpt372_udma; 309 1.10.2.2 skrll tim_dma = hpt372_dma; 310 1.10.2.2 skrll tim_pio = hpt372_pio; 311 1.10.2.2 skrll break; 312 1.10.2.2 skrll case PCI_PRODUCT_TRIONES_HPT366: 313 1.10.2.2 skrll default: 314 1.10.2.2 skrll switch (revision) { 315 1.10.2.2 skrll case HPT372_REV: 316 1.10.2.2 skrll tim_udma = hpt372_udma; 317 1.10.2.2 skrll tim_dma = hpt372_dma; 318 1.10.2.2 skrll tim_pio = hpt372_pio; 319 1.10.2.2 skrll break; 320 1.10.2.2 skrll case HPT370_REV: 321 1.10.2.2 skrll case HPT370A_REV: 322 1.10.2.2 skrll tim_udma = hpt370_udma; 323 1.10.2.2 skrll tim_dma = hpt370_dma; 324 1.10.2.2 skrll tim_pio = hpt370_pio; 325 1.10.2.2 skrll break; 326 1.10.2.2 skrll case HPT366_REV: 327 1.10.2.2 skrll default: 328 1.10.2.2 skrll tim_udma = hpt366_udma; 329 1.10.2.2 skrll tim_dma = hpt366_dma; 330 1.10.2.2 skrll tim_pio = hpt366_pio; 331 1.10.2.2 skrll break; 332 1.10.2.2 skrll } 333 1.10.2.2 skrll } 334 1.10.2.2 skrll 335 1.10.2.2 skrll /* Per drive settings */ 336 1.10.2.2 skrll for (drive = 0; drive < 2; drive++) { 337 1.10.2.2 skrll drvp = &chp->ch_drive[drive]; 338 1.10.2.2 skrll /* If no drive, skip */ 339 1.10.2.2 skrll if ((drvp->drive_flags & DRIVE) == 0) 340 1.10.2.2 skrll continue; 341 1.10.2.2 skrll before = pci_conf_read(sc->sc_pc, sc->sc_tag, 342 1.10.2.2 skrll HPT_IDETIM(chp->ch_channel, drive)); 343 1.10.2.2 skrll 344 1.10.2.2 skrll /* add timing values, setup DMA if needed */ 345 1.10.2.2 skrll if (drvp->drive_flags & DRIVE_UDMA) { 346 1.10.2.2 skrll /* use Ultra/DMA */ 347 1.10.2.3 skrll s = splbio(); 348 1.10.2.2 skrll drvp->drive_flags &= ~DRIVE_DMA; 349 1.10.2.3 skrll splx(s); 350 1.10.2.2 skrll if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 && 351 1.10.2.2 skrll drvp->UDMA_mode > 2) 352 1.10.2.2 skrll drvp->UDMA_mode = 2; 353 1.10.2.2 skrll after = tim_udma[drvp->UDMA_mode]; 354 1.10.2.2 skrll idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 355 1.10.2.2 skrll } else if (drvp->drive_flags & DRIVE_DMA) { 356 1.10.2.2 skrll /* 357 1.10.2.2 skrll * use Multiword DMA. 358 1.10.2.2 skrll * Timings will be used for both PIO and DMA, so adjust 359 1.10.2.2 skrll * DMA mode if needed 360 1.10.2.2 skrll */ 361 1.10.2.2 skrll if (drvp->PIO_mode >= 3 && 362 1.10.2.2 skrll (drvp->DMA_mode + 2) > drvp->PIO_mode) { 363 1.10.2.2 skrll drvp->DMA_mode = drvp->PIO_mode - 2; 364 1.10.2.2 skrll } 365 1.10.2.2 skrll after = tim_dma[drvp->DMA_mode]; 366 1.10.2.2 skrll idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 367 1.10.2.2 skrll } else { 368 1.10.2.2 skrll /* PIO only */ 369 1.10.2.2 skrll after = tim_pio[drvp->PIO_mode]; 370 1.10.2.2 skrll } 371 1.10.2.2 skrll pci_conf_write(sc->sc_pc, sc->sc_tag, 372 1.10.2.2 skrll HPT_IDETIM(chp->ch_channel, drive), after); 373 1.10.2.3 skrll ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x " 374 1.10.2.2 skrll "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 375 1.10.2.2 skrll after, before), DEBUG_PROBE); 376 1.10.2.2 skrll } 377 1.10.2.2 skrll if (idedma_ctl != 0) { 378 1.10.2.2 skrll /* Add software bits in status register */ 379 1.10.2.2 skrll bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 380 1.10.2.2 skrll idedma_ctl); 381 1.10.2.2 skrll } 382 1.10.2.2 skrll } 383 1.10.2.2 skrll 384 1.10.2.2 skrll static int 385 1.10.2.2 skrll hpt_pci_intr(void *arg) 386 1.10.2.2 skrll { 387 1.10.2.2 skrll struct pciide_softc *sc = arg; 388 1.10.2.2 skrll struct pciide_channel *cp; 389 1.10.2.3 skrll struct ata_channel *wdc_cp; 390 1.10.2.2 skrll int rv = 0; 391 1.10.2.2 skrll int dmastat, i, crv; 392 1.10.2.2 skrll 393 1.10.2.3 skrll for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 394 1.10.2.2 skrll cp = &sc->pciide_channels[i]; 395 1.10.2.2 skrll dmastat = bus_space_read_1(sc->sc_dma_iot, 396 1.10.2.2 skrll cp->dma_iohs[IDEDMA_CTL], 0); 397 1.10.2.2 skrll if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 398 1.10.2.2 skrll IDEDMA_CTL_INTR) 399 1.10.2.2 skrll continue; 400 1.10.2.3 skrll wdc_cp = &cp->ata_channel; 401 1.10.2.2 skrll crv = wdcintr(wdc_cp); 402 1.10.2.2 skrll if (crv == 0) { 403 1.10.2.2 skrll printf("%s:%d: bogus intr\n", 404 1.10.2.3 skrll sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 405 1.10.2.2 skrll bus_space_write_1(sc->sc_dma_iot, 406 1.10.2.2 skrll cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 407 1.10.2.2 skrll } else 408 1.10.2.2 skrll rv = 1; 409 1.10.2.2 skrll } 410 1.10.2.2 skrll return rv; 411 1.10.2.2 skrll } 412
Indexes created Tue Oct 21 12:09:54 GMT 2025