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hptide.c revision 1.17.2.1
      1  1.17.2.1     ghen /*	$NetBSD: hptide.c,v 1.17.2.1 2006/08/06 08:44:07 ghen Exp $	*/
      2       1.1   bouyer 
      3       1.1   bouyer /*
      4       1.1   bouyer  * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
      5       1.1   bouyer  *
      6       1.1   bouyer  * Redistribution and use in source and binary forms, with or without
      7       1.1   bouyer  * modification, are permitted provided that the following conditions
      8       1.1   bouyer  * are met:
      9       1.1   bouyer  * 1. Redistributions of source code must retain the above copyright
     10       1.1   bouyer  *    notice, this list of conditions and the following disclaimer.
     11       1.1   bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     12       1.1   bouyer  *    notice, this list of conditions and the following disclaimer in the
     13       1.1   bouyer  *    documentation and/or other materials provided with the distribution.
     14       1.1   bouyer  * 3. All advertising materials mentioning features or use of this software
     15       1.1   bouyer  *    must display the following acknowledgement:
     16       1.1   bouyer  *	This product includes software developed by Manuel Bouyer.
     17       1.1   bouyer  * 4. The name of the author may not be used to endorse or promote products
     18       1.1   bouyer  *    derived from this software without specific prior written permission.
     19       1.1   bouyer  *
     20       1.1   bouyer  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21       1.1   bouyer  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22       1.1   bouyer  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23      1.17    perry  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24       1.1   bouyer  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25       1.1   bouyer  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26       1.1   bouyer  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27       1.1   bouyer  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28       1.1   bouyer  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29       1.1   bouyer  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30       1.1   bouyer  */
     31       1.1   bouyer 
     32       1.1   bouyer #include <sys/param.h>
     33       1.1   bouyer #include <sys/systm.h>
     34       1.1   bouyer 
     35       1.1   bouyer #include <dev/pci/pcivar.h>
     36       1.1   bouyer #include <dev/pci/pcidevs.h>
     37       1.1   bouyer #include <dev/pci/pciidereg.h>
     38       1.1   bouyer #include <dev/pci/pciidevar.h>
     39       1.1   bouyer #include <dev/pci/pciide_hpt_reg.h>
     40       1.1   bouyer 
     41       1.2  thorpej static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*);
     42      1.13  thorpej static void hpt_setup_channel(struct ata_channel*);
     43       1.2  thorpej static int  hpt_pci_intr(void *);
     44       1.1   bouyer 
     45       1.2  thorpej static int  hptide_match(struct device *, struct cfdata *, void *);
     46       1.2  thorpej static void hptide_attach(struct device *, struct device *, void *);
     47       1.1   bouyer 
     48       1.1   bouyer CFATTACH_DECL(hptide, sizeof(struct pciide_softc),
     49       1.1   bouyer     hptide_match, hptide_attach, NULL, NULL);
     50       1.1   bouyer 
     51       1.2  thorpej static const struct pciide_product_desc pciide_triones_products[] =  {
     52       1.7      chs 	{ PCI_PRODUCT_TRIONES_HPT302,
     53       1.7      chs 	  0,
     54       1.7      chs 	  NULL,
     55       1.7      chs 	  hpt_chip_map
     56       1.7      chs 	},
     57       1.1   bouyer 	{ PCI_PRODUCT_TRIONES_HPT366,
     58       1.3  mycroft 	  0,
     59       1.1   bouyer 	  NULL,
     60       1.1   bouyer 	  hpt_chip_map,
     61       1.1   bouyer 	},
     62       1.7      chs 	{ PCI_PRODUCT_TRIONES_HPT371,
     63       1.7      chs 	  0,
     64       1.7      chs 	  NULL,
     65       1.7      chs 	  hpt_chip_map,
     66       1.7      chs 	},
     67       1.7      chs 	{ PCI_PRODUCT_TRIONES_HPT372A,
     68       1.3  mycroft 	  0,
     69       1.1   bouyer 	  NULL,
     70       1.1   bouyer 	  hpt_chip_map
     71       1.1   bouyer 	},
     72       1.1   bouyer 	{ PCI_PRODUCT_TRIONES_HPT374,
     73       1.3  mycroft 	  0,
     74       1.1   bouyer 	  NULL,
     75       1.1   bouyer 	  hpt_chip_map
     76       1.1   bouyer 	},
     77       1.1   bouyer 	{ 0,
     78       1.1   bouyer 	  0,
     79       1.1   bouyer 	  NULL,
     80       1.1   bouyer 	  NULL
     81       1.1   bouyer 	}
     82       1.1   bouyer };
     83       1.1   bouyer 
     84       1.2  thorpej static int
     85       1.2  thorpej hptide_match(struct device *parent, struct cfdata *match, void *aux)
     86       1.1   bouyer {
     87       1.1   bouyer 	struct pci_attach_args *pa = aux;
     88       1.1   bouyer 
     89       1.1   bouyer 	if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) {
     90       1.1   bouyer 		if (pciide_lookup_product(pa->pa_id, pciide_triones_products))
     91       1.1   bouyer 			return (2);
     92       1.1   bouyer 	}
     93       1.1   bouyer 	return (0);
     94       1.1   bouyer }
     95       1.1   bouyer 
     96       1.2  thorpej static void
     97       1.2  thorpej hptide_attach(struct device *parent, struct device *self, void *aux)
     98       1.1   bouyer {
     99       1.1   bouyer 	struct pci_attach_args *pa = aux;
    100       1.1   bouyer 	struct pciide_softc *sc = (struct pciide_softc *)self;
    101       1.1   bouyer 
    102       1.1   bouyer 	pciide_common_attach(sc, pa,
    103       1.1   bouyer 	    pciide_lookup_product(pa->pa_id, pciide_triones_products));
    104       1.1   bouyer 
    105       1.1   bouyer }
    106       1.1   bouyer 
    107       1.2  thorpej static void
    108       1.2  thorpej hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
    109       1.1   bouyer {
    110       1.1   bouyer 	struct pciide_channel *cp;
    111       1.5  mycroft 	int i, compatchan, revision;
    112       1.1   bouyer 	pcireg_t interface;
    113       1.1   bouyer 	bus_size_t cmdsize, ctlsize;
    114       1.1   bouyer 
    115       1.1   bouyer 	if (pciide_chipen(sc, pa) == 0)
    116       1.1   bouyer 		return;
    117       1.1   bouyer 
    118       1.1   bouyer 	revision = PCI_REVISION(pa->pa_class);
    119       1.1   bouyer 	aprint_normal("%s: Triones/Highpoint ",
    120      1.15  thorpej 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    121       1.7      chs 	switch (sc->sc_pp->ide_product) {
    122       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT302:
    123       1.7      chs 		aprint_normal("HPT302 IDE Controller\n");
    124       1.7      chs 		break;
    125       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT371:
    126       1.7      chs 		aprint_normal("HPT371 IDE Controller\n");
    127       1.7      chs 		break;
    128       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT374:
    129       1.1   bouyer 		aprint_normal("HPT374 IDE Controller\n");
    130       1.7      chs 		break;
    131       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT372A:
    132       1.7      chs 		aprint_normal("HPT372A IDE Controller\n");
    133       1.7      chs 		break;
    134       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT366:
    135       1.1   bouyer 		if (revision == HPT372_REV)
    136       1.1   bouyer 			aprint_normal("HPT372 IDE Controller\n");
    137       1.1   bouyer 		else if (revision == HPT370_REV)
    138       1.1   bouyer 			aprint_normal("HPT370 IDE Controller\n");
    139       1.1   bouyer 		else if (revision == HPT370A_REV)
    140       1.1   bouyer 			aprint_normal("HPT370A IDE Controller\n");
    141  1.17.2.1     ghen 		else if (revision == HPT368_REV)
    142  1.17.2.1     ghen 			aprint_normal("HPT368 IDE Controller\n");
    143       1.1   bouyer 		else if (revision == HPT366_REV)
    144       1.1   bouyer 			aprint_normal("HPT366 IDE Controller\n");
    145       1.1   bouyer 		else
    146       1.1   bouyer 			aprint_normal("unknown HPT IDE controller rev %d\n",
    147       1.1   bouyer 			    revision);
    148       1.7      chs 		break;
    149       1.7      chs 	default:
    150       1.1   bouyer 		aprint_normal("unknown HPT IDE controller 0x%x\n",
    151       1.1   bouyer 		    sc->sc_pp->ide_product);
    152       1.7      chs 	}
    153       1.1   bouyer 
    154      1.17    perry 	/*
    155       1.1   bouyer 	 * when the chip is in native mode it identifies itself as a
    156       1.1   bouyer 	 * 'misc mass storage'. Fake interface in this case.
    157       1.1   bouyer 	 */
    158       1.1   bouyer 	if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
    159       1.1   bouyer 		interface = PCI_INTERFACE(pa->pa_class);
    160       1.1   bouyer 	} else {
    161       1.1   bouyer 		interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
    162       1.1   bouyer 		    PCIIDE_INTERFACE_PCI(0);
    163       1.1   bouyer 		if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
    164  1.17.2.1     ghen 		    (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV ||
    165       1.1   bouyer 		     revision == HPT372_REV)) ||
    166       1.7      chs 		    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
    167       1.7      chs 		    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
    168       1.7      chs 		    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
    169       1.1   bouyer 		    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
    170       1.1   bouyer 			interface |= PCIIDE_INTERFACE_PCI(1);
    171       1.1   bouyer 	}
    172       1.1   bouyer 
    173       1.1   bouyer 	aprint_normal("%s: bus-master DMA support present",
    174      1.15  thorpej 	    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
    175       1.1   bouyer 	pciide_mapreg_dma(sc, pa);
    176       1.1   bouyer 	aprint_normal("\n");
    177      1.15  thorpej 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
    178       1.1   bouyer 	if (sc->sc_dma_ok) {
    179      1.15  thorpej 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
    180       1.1   bouyer 		sc->sc_wdcdev.irqack = pciide_irqack;
    181       1.1   bouyer 	}
    182      1.15  thorpej 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
    183      1.15  thorpej 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
    184       1.1   bouyer 
    185      1.15  thorpej 	sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel;
    186      1.15  thorpej 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
    187       1.1   bouyer 	if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
    188  1.17.2.1     ghen 	    (revision == HPT366_REV || revision == HPT368_REV)) {
    189      1.15  thorpej 		sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
    190      1.15  thorpej 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
    191       1.1   bouyer 	} else {
    192      1.15  thorpej 		sc->sc_wdcdev.sc_atac.atac_nchannels = 2;
    193       1.1   bouyer 		if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 ||
    194       1.7      chs 		    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
    195       1.7      chs 		    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
    196       1.7      chs 		    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
    197       1.1   bouyer 		    (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
    198       1.1   bouyer 		    revision == HPT372_REV))
    199      1.15  thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
    200       1.1   bouyer 		else
    201      1.15  thorpej 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
    202       1.1   bouyer 	}
    203      1.13  thorpej 
    204      1.13  thorpej 	wdc_allocate_regs(&sc->sc_wdcdev);
    205      1.13  thorpej 
    206      1.15  thorpej 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
    207       1.1   bouyer 		cp = &sc->pciide_channels[i];
    208      1.15  thorpej 		if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) {
    209       1.1   bouyer 			compatchan = i;
    210       1.1   bouyer 			if((pciide_pci_read(sc->sc_pc, sc->sc_tag,
    211       1.1   bouyer 			   HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) {
    212       1.1   bouyer 				aprint_normal(
    213       1.1   bouyer 				    "%s: %s channel ignored (disabled)\n",
    214      1.15  thorpej 				    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
    215      1.13  thorpej 				cp->ata_channel.ch_flags |= ATACH_DISABLED;
    216       1.1   bouyer 				continue;
    217       1.5  mycroft 			}
    218       1.5  mycroft 		} else {
    219       1.5  mycroft 			/*
    220       1.5  mycroft 			 * The 366 has 2 PCI IDE functions, one for primary and
    221       1.5  mycroft 			 * one for secondary. So we need to call
    222       1.5  mycroft 			 * pciide_mapregs_compat() with the real channel.
    223       1.5  mycroft 			 */
    224       1.5  mycroft 			if (pa->pa_function == 0)
    225       1.5  mycroft 				compatchan = 0;
    226       1.5  mycroft 			else if (pa->pa_function == 1)
    227       1.5  mycroft 				compatchan = 1;
    228       1.5  mycroft 			else {
    229       1.5  mycroft 				aprint_error("%s: unexpected PCI function %d\n",
    230      1.15  thorpej 				    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, pa->pa_function);
    231       1.5  mycroft 				return;
    232       1.1   bouyer 			}
    233       1.1   bouyer 		}
    234       1.1   bouyer 		if (pciide_chansetup(sc, i, interface) == 0)
    235       1.1   bouyer 			continue;
    236       1.1   bouyer 		if (interface & PCIIDE_INTERFACE_PCI(i)) {
    237       1.1   bouyer 			pciide_mapregs_native(pa, cp, &cmdsize,
    238       1.1   bouyer 			    &ctlsize, hpt_pci_intr);
    239       1.1   bouyer 		} else {
    240       1.1   bouyer 			pciide_mapregs_compat(pa, cp, compatchan,
    241       1.1   bouyer 			    &cmdsize, &ctlsize);
    242      1.13  thorpej 			if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
    243      1.10   bouyer 				pciide_map_compat_intr(pa, cp,
    244      1.10   bouyer 				    sc->sc_cy_compatchan);
    245       1.1   bouyer 		}
    246      1.13  thorpej 		wdcattach(&cp->ata_channel);
    247       1.1   bouyer 	}
    248       1.1   bouyer 	if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
    249  1.17.2.1     ghen 	    (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV ||
    250      1.17    perry 	     revision == HPT372_REV)) ||
    251       1.7      chs 	    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
    252       1.7      chs 	    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
    253       1.7      chs 	    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
    254       1.1   bouyer 	    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) {
    255       1.1   bouyer 		/*
    256       1.1   bouyer 		 * HPT370_REV and highter has a bit to disable interrupts,
    257       1.1   bouyer 		 * make sure to clear it
    258       1.1   bouyer 		 */
    259       1.1   bouyer 		pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL,
    260       1.1   bouyer 		    pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) &
    261       1.1   bouyer 		    ~HPT_CSEL_IRQDIS);
    262       1.1   bouyer 	}
    263       1.1   bouyer 	/* set clocks, etc (mandatory on 372/4, optional otherwise) */
    264       1.1   bouyer 	if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
    265       1.1   bouyer 	     revision == HPT372_REV ) ||
    266       1.7      chs 	    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
    267       1.7      chs 	    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
    268       1.7      chs 	    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
    269       1.1   bouyer 	    sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
    270       1.1   bouyer 		pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2,
    271       1.1   bouyer 		    (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) &
    272       1.1   bouyer 		     HPT_SC2_MAEN) | HPT_SC2_OSC_EN);
    273       1.1   bouyer 	return;
    274       1.1   bouyer }
    275       1.1   bouyer 
    276       1.2  thorpej static void
    277      1.13  thorpej hpt_setup_channel(struct ata_channel *chp)
    278       1.1   bouyer {
    279       1.1   bouyer 	struct ata_drive_datas *drvp;
    280      1.16  thorpej 	int drive, s;
    281       1.1   bouyer 	int cable;
    282       1.1   bouyer 	u_int32_t before, after;
    283       1.1   bouyer 	u_int32_t idedma_ctl;
    284      1.14  thorpej 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
    285      1.14  thorpej 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
    286       1.1   bouyer 	int revision =
    287       1.1   bouyer 	     PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
    288       1.7      chs 	const u_int32_t *tim_pio, *tim_dma, *tim_udma;
    289       1.1   bouyer 
    290       1.1   bouyer 	cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL);
    291       1.1   bouyer 
    292       1.1   bouyer 	/* setup DMA if needed */
    293       1.1   bouyer 	pciide_channel_dma_setup(cp);
    294       1.1   bouyer 
    295       1.1   bouyer 	idedma_ctl = 0;
    296       1.1   bouyer 
    297       1.7      chs 	/* select the timing arrays for the chip */
    298       1.7      chs 	switch (sc->sc_pp->ide_product) {
    299       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT374:
    300       1.7      chs 		tim_udma = hpt374_udma;
    301       1.7      chs 		tim_dma = hpt374_dma;
    302       1.7      chs 		tim_pio = hpt374_pio;
    303       1.7      chs 		break;
    304       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT302:
    305       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT371:
    306       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT372A:
    307       1.7      chs 		tim_udma = hpt372_udma;
    308       1.7      chs 		tim_dma = hpt372_dma;
    309       1.7      chs 		tim_pio = hpt372_pio;
    310       1.7      chs 		break;
    311       1.7      chs 	case PCI_PRODUCT_TRIONES_HPT366:
    312       1.7      chs 	default:
    313       1.7      chs 		switch (revision) {
    314       1.7      chs 		case HPT372_REV:
    315       1.7      chs 			tim_udma = hpt372_udma;
    316       1.7      chs 			tim_dma = hpt372_dma;
    317       1.7      chs 			tim_pio = hpt372_pio;
    318       1.7      chs 			break;
    319       1.7      chs 		case HPT370_REV:
    320       1.7      chs 		case HPT370A_REV:
    321       1.7      chs 			tim_udma = hpt370_udma;
    322       1.7      chs 			tim_dma = hpt370_dma;
    323       1.7      chs 			tim_pio = hpt370_pio;
    324       1.7      chs 			break;
    325  1.17.2.1     ghen 		case HPT368_REV:
    326       1.7      chs 		case HPT366_REV:
    327       1.7      chs 		default:
    328       1.7      chs 			tim_udma = hpt366_udma;
    329       1.7      chs 			tim_dma = hpt366_dma;
    330       1.7      chs 			tim_pio = hpt366_pio;
    331       1.7      chs 			break;
    332       1.7      chs 		}
    333       1.7      chs 	}
    334       1.7      chs 
    335       1.1   bouyer 	/* Per drive settings */
    336       1.1   bouyer 	for (drive = 0; drive < 2; drive++) {
    337       1.1   bouyer 		drvp = &chp->ch_drive[drive];
    338       1.1   bouyer 		/* If no drive, skip */
    339       1.1   bouyer 		if ((drvp->drive_flags & DRIVE) == 0)
    340       1.1   bouyer 			continue;
    341       1.1   bouyer 		before = pci_conf_read(sc->sc_pc, sc->sc_tag,
    342       1.9  thorpej 					HPT_IDETIM(chp->ch_channel, drive));
    343       1.1   bouyer 
    344       1.1   bouyer 		/* add timing values, setup DMA if needed */
    345       1.1   bouyer 		if (drvp->drive_flags & DRIVE_UDMA) {
    346       1.1   bouyer 			/* use Ultra/DMA */
    347      1.16  thorpej 			s = splbio();
    348       1.1   bouyer 			drvp->drive_flags &= ~DRIVE_DMA;
    349      1.16  thorpej 			splx(s);
    350       1.9  thorpej 			if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 &&
    351       1.1   bouyer 			    drvp->UDMA_mode > 2)
    352       1.1   bouyer 				drvp->UDMA_mode = 2;
    353       1.7      chs 			after = tim_udma[drvp->UDMA_mode];
    354       1.1   bouyer 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    355       1.1   bouyer 		} else if (drvp->drive_flags & DRIVE_DMA) {
    356       1.1   bouyer 			/*
    357       1.1   bouyer 			 * use Multiword DMA.
    358       1.1   bouyer 			 * Timings will be used for both PIO and DMA, so adjust
    359       1.1   bouyer 			 * DMA mode if needed
    360       1.1   bouyer 			 */
    361       1.1   bouyer 			if (drvp->PIO_mode >= 3 &&
    362       1.1   bouyer 			    (drvp->DMA_mode + 2) > drvp->PIO_mode) {
    363       1.1   bouyer 				drvp->DMA_mode = drvp->PIO_mode - 2;
    364       1.1   bouyer 			}
    365       1.7      chs 			after = tim_dma[drvp->DMA_mode];
    366       1.1   bouyer 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
    367       1.1   bouyer 		} else {
    368       1.1   bouyer 			/* PIO only */
    369       1.7      chs 			after = tim_pio[drvp->PIO_mode];
    370       1.1   bouyer 		}
    371       1.1   bouyer 		pci_conf_write(sc->sc_pc, sc->sc_tag,
    372       1.9  thorpej 		    HPT_IDETIM(chp->ch_channel, drive), after);
    373      1.12  thorpej 		ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x "
    374       1.1   bouyer 		    "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname,
    375       1.1   bouyer 		    after, before), DEBUG_PROBE);
    376       1.1   bouyer 	}
    377       1.1   bouyer 	if (idedma_ctl != 0) {
    378       1.1   bouyer 		/* Add software bits in status register */
    379       1.6     fvdl 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
    380       1.1   bouyer 		    idedma_ctl);
    381       1.1   bouyer 	}
    382       1.1   bouyer }
    383       1.1   bouyer 
    384       1.2  thorpej static int
    385       1.2  thorpej hpt_pci_intr(void *arg)
    386       1.1   bouyer {
    387       1.1   bouyer 	struct pciide_softc *sc = arg;
    388       1.1   bouyer 	struct pciide_channel *cp;
    389      1.13  thorpej 	struct ata_channel *wdc_cp;
    390       1.1   bouyer 	int rv = 0;
    391       1.1   bouyer 	int dmastat, i, crv;
    392       1.1   bouyer 
    393      1.15  thorpej 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
    394       1.6     fvdl 		cp = &sc->pciide_channels[i];
    395       1.6     fvdl 		dmastat = bus_space_read_1(sc->sc_dma_iot,
    396       1.6     fvdl 		    cp->dma_iohs[IDEDMA_CTL], 0);
    397       1.1   bouyer 		if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
    398       1.1   bouyer 		    IDEDMA_CTL_INTR)
    399       1.1   bouyer 			continue;
    400      1.13  thorpej 		wdc_cp = &cp->ata_channel;
    401       1.1   bouyer 		crv = wdcintr(wdc_cp);
    402       1.1   bouyer 		if (crv == 0) {
    403       1.1   bouyer 			printf("%s:%d: bogus intr\n",
    404      1.15  thorpej 			    sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i);
    405       1.6     fvdl 			bus_space_write_1(sc->sc_dma_iot,
    406       1.6     fvdl 			    cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
    407       1.1   bouyer 		} else
    408       1.1   bouyer 			rv = 1;
    409       1.1   bouyer 	}
    410       1.1   bouyer 	return rv;
    411       1.1   bouyer }
    412