hptide.c revision 1.2 1 1.2 thorpej /* $NetBSD: hptide.c,v 1.2 2003/10/11 17:40:15 thorpej Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*
4 1.1 bouyer * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 1.1 bouyer *
6 1.1 bouyer * Redistribution and use in source and binary forms, with or without
7 1.1 bouyer * modification, are permitted provided that the following conditions
8 1.1 bouyer * are met:
9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.1 bouyer * notice, this list of conditions and the following disclaimer.
11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.1 bouyer * documentation and/or other materials provided with the distribution.
14 1.1 bouyer * 3. All advertising materials mentioning features or use of this software
15 1.1 bouyer * must display the following acknowledgement:
16 1.1 bouyer * This product includes software developed by Manuel Bouyer.
17 1.1 bouyer * 4. The name of the author may not be used to endorse or promote products
18 1.1 bouyer * derived from this software without specific prior written permission.
19 1.1 bouyer *
20 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.1 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 bouyer */
31 1.1 bouyer
32 1.1 bouyer #include <sys/param.h>
33 1.1 bouyer #include <sys/systm.h>
34 1.1 bouyer
35 1.1 bouyer #include <dev/pci/pcivar.h>
36 1.1 bouyer #include <dev/pci/pcidevs.h>
37 1.1 bouyer #include <dev/pci/pciidereg.h>
38 1.1 bouyer #include <dev/pci/pciidevar.h>
39 1.1 bouyer #include <dev/pci/pciide_hpt_reg.h>
40 1.1 bouyer
41 1.2 thorpej static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*);
42 1.2 thorpej static void hpt_setup_channel(struct channel_softc*);
43 1.2 thorpej static int hpt_pci_intr(void *);
44 1.1 bouyer
45 1.2 thorpej static int hptide_match(struct device *, struct cfdata *, void *);
46 1.2 thorpej static void hptide_attach(struct device *, struct device *, void *);
47 1.1 bouyer
48 1.1 bouyer CFATTACH_DECL(hptide, sizeof(struct pciide_softc),
49 1.1 bouyer hptide_match, hptide_attach, NULL, NULL);
50 1.1 bouyer
51 1.2 thorpej static const struct pciide_product_desc pciide_triones_products[] = {
52 1.1 bouyer { PCI_PRODUCT_TRIONES_HPT366,
53 1.1 bouyer IDE_PCI_CLASS_OVERRIDE,
54 1.1 bouyer NULL,
55 1.1 bouyer hpt_chip_map,
56 1.1 bouyer },
57 1.1 bouyer { PCI_PRODUCT_TRIONES_HPT372,
58 1.1 bouyer IDE_PCI_CLASS_OVERRIDE,
59 1.1 bouyer NULL,
60 1.1 bouyer hpt_chip_map
61 1.1 bouyer },
62 1.1 bouyer { PCI_PRODUCT_TRIONES_HPT374,
63 1.1 bouyer IDE_PCI_CLASS_OVERRIDE,
64 1.1 bouyer NULL,
65 1.1 bouyer hpt_chip_map
66 1.1 bouyer },
67 1.1 bouyer { 0,
68 1.1 bouyer 0,
69 1.1 bouyer NULL,
70 1.1 bouyer NULL
71 1.1 bouyer }
72 1.1 bouyer };
73 1.1 bouyer
74 1.2 thorpej static int
75 1.2 thorpej hptide_match(struct device *parent, struct cfdata *match, void *aux)
76 1.1 bouyer {
77 1.1 bouyer struct pci_attach_args *pa = aux;
78 1.1 bouyer
79 1.1 bouyer if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) {
80 1.1 bouyer if (pciide_lookup_product(pa->pa_id, pciide_triones_products))
81 1.1 bouyer return (2);
82 1.1 bouyer }
83 1.1 bouyer return (0);
84 1.1 bouyer }
85 1.1 bouyer
86 1.2 thorpej static void
87 1.2 thorpej hptide_attach(struct device *parent, struct device *self, void *aux)
88 1.1 bouyer {
89 1.1 bouyer struct pci_attach_args *pa = aux;
90 1.1 bouyer struct pciide_softc *sc = (struct pciide_softc *)self;
91 1.1 bouyer
92 1.1 bouyer pciide_common_attach(sc, pa,
93 1.1 bouyer pciide_lookup_product(pa->pa_id, pciide_triones_products));
94 1.1 bouyer
95 1.1 bouyer }
96 1.1 bouyer
97 1.2 thorpej static void
98 1.2 thorpej hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
99 1.1 bouyer {
100 1.1 bouyer struct pciide_channel *cp;
101 1.1 bouyer int i, compatchan, revision;
102 1.1 bouyer pcireg_t interface;
103 1.1 bouyer bus_size_t cmdsize, ctlsize;
104 1.1 bouyer
105 1.1 bouyer if (pciide_chipen(sc, pa) == 0)
106 1.1 bouyer return;
107 1.1 bouyer
108 1.1 bouyer revision = PCI_REVISION(pa->pa_class);
109 1.1 bouyer aprint_normal("%s: Triones/Highpoint ",
110 1.1 bouyer sc->sc_wdcdev.sc_dev.dv_xname);
111 1.1 bouyer if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
112 1.1 bouyer aprint_normal("HPT374 IDE Controller\n");
113 1.1 bouyer else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372)
114 1.1 bouyer aprint_normal("HPT372 IDE Controller\n");
115 1.1 bouyer else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) {
116 1.1 bouyer if (revision == HPT372_REV)
117 1.1 bouyer aprint_normal("HPT372 IDE Controller\n");
118 1.1 bouyer else if (revision == HPT370_REV)
119 1.1 bouyer aprint_normal("HPT370 IDE Controller\n");
120 1.1 bouyer else if (revision == HPT370A_REV)
121 1.1 bouyer aprint_normal("HPT370A IDE Controller\n");
122 1.1 bouyer else if (revision == HPT366_REV)
123 1.1 bouyer aprint_normal("HPT366 IDE Controller\n");
124 1.1 bouyer else
125 1.1 bouyer aprint_normal("unknown HPT IDE controller rev %d\n",
126 1.1 bouyer revision);
127 1.1 bouyer } else
128 1.1 bouyer aprint_normal("unknown HPT IDE controller 0x%x\n",
129 1.1 bouyer sc->sc_pp->ide_product);
130 1.1 bouyer
131 1.1 bouyer /*
132 1.1 bouyer * when the chip is in native mode it identifies itself as a
133 1.1 bouyer * 'misc mass storage'. Fake interface in this case.
134 1.1 bouyer */
135 1.1 bouyer if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
136 1.1 bouyer interface = PCI_INTERFACE(pa->pa_class);
137 1.1 bouyer } else {
138 1.1 bouyer interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
139 1.1 bouyer PCIIDE_INTERFACE_PCI(0);
140 1.1 bouyer if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
141 1.1 bouyer (revision == HPT370_REV || revision == HPT370A_REV ||
142 1.1 bouyer revision == HPT372_REV)) ||
143 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 ||
144 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
145 1.1 bouyer interface |= PCIIDE_INTERFACE_PCI(1);
146 1.1 bouyer }
147 1.1 bouyer
148 1.1 bouyer aprint_normal("%s: bus-master DMA support present",
149 1.1 bouyer sc->sc_wdcdev.sc_dev.dv_xname);
150 1.1 bouyer pciide_mapreg_dma(sc, pa);
151 1.1 bouyer aprint_normal("\n");
152 1.1 bouyer sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
153 1.1 bouyer WDC_CAPABILITY_MODE;
154 1.1 bouyer if (sc->sc_dma_ok) {
155 1.1 bouyer sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
156 1.1 bouyer sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
157 1.1 bouyer sc->sc_wdcdev.irqack = pciide_irqack;
158 1.1 bouyer }
159 1.1 bouyer sc->sc_wdcdev.PIO_cap = 4;
160 1.1 bouyer sc->sc_wdcdev.DMA_cap = 2;
161 1.1 bouyer
162 1.1 bouyer sc->sc_wdcdev.set_modes = hpt_setup_channel;
163 1.1 bouyer sc->sc_wdcdev.channels = sc->wdc_chanarray;
164 1.1 bouyer if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
165 1.1 bouyer revision == HPT366_REV) {
166 1.1 bouyer sc->sc_wdcdev.UDMA_cap = 4;
167 1.1 bouyer /*
168 1.1 bouyer * The 366 has 2 PCI IDE functions, one for primary and one
169 1.1 bouyer * for secondary. So we need to call pciide_mapregs_compat()
170 1.1 bouyer * with the real channel
171 1.1 bouyer */
172 1.1 bouyer if (pa->pa_function == 0) {
173 1.1 bouyer compatchan = 0;
174 1.1 bouyer } else if (pa->pa_function == 1) {
175 1.1 bouyer compatchan = 1;
176 1.1 bouyer } else {
177 1.1 bouyer aprint_error("%s: unexpected PCI function %d\n",
178 1.1 bouyer sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function);
179 1.1 bouyer return;
180 1.1 bouyer }
181 1.1 bouyer sc->sc_wdcdev.nchannels = 1;
182 1.1 bouyer } else {
183 1.1 bouyer sc->sc_wdcdev.nchannels = 2;
184 1.1 bouyer if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 ||
185 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 ||
186 1.1 bouyer (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
187 1.1 bouyer revision == HPT372_REV))
188 1.1 bouyer sc->sc_wdcdev.UDMA_cap = 6;
189 1.1 bouyer else
190 1.1 bouyer sc->sc_wdcdev.UDMA_cap = 5;
191 1.1 bouyer }
192 1.1 bouyer for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
193 1.1 bouyer cp = &sc->pciide_channels[i];
194 1.1 bouyer if (sc->sc_wdcdev.nchannels > 1) {
195 1.1 bouyer compatchan = i;
196 1.1 bouyer if((pciide_pci_read(sc->sc_pc, sc->sc_tag,
197 1.1 bouyer HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) {
198 1.1 bouyer aprint_normal(
199 1.1 bouyer "%s: %s channel ignored (disabled)\n",
200 1.1 bouyer sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
201 1.1 bouyer cp->wdc_channel.ch_flags |= WDCF_DISABLED;
202 1.1 bouyer continue;
203 1.1 bouyer }
204 1.1 bouyer }
205 1.1 bouyer if (pciide_chansetup(sc, i, interface) == 0)
206 1.1 bouyer continue;
207 1.1 bouyer if (interface & PCIIDE_INTERFACE_PCI(i)) {
208 1.1 bouyer pciide_mapregs_native(pa, cp, &cmdsize,
209 1.1 bouyer &ctlsize, hpt_pci_intr);
210 1.1 bouyer } else {
211 1.1 bouyer pciide_mapregs_compat(pa, cp, compatchan,
212 1.1 bouyer &cmdsize, &ctlsize);
213 1.1 bouyer }
214 1.1 bouyer wdcattach(&cp->wdc_channel);
215 1.1 bouyer }
216 1.1 bouyer if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
217 1.1 bouyer (revision == HPT370_REV || revision == HPT370A_REV ||
218 1.1 bouyer revision == HPT372_REV)) ||
219 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 ||
220 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) {
221 1.1 bouyer /*
222 1.1 bouyer * HPT370_REV and highter has a bit to disable interrupts,
223 1.1 bouyer * make sure to clear it
224 1.1 bouyer */
225 1.1 bouyer pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL,
226 1.1 bouyer pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) &
227 1.1 bouyer ~HPT_CSEL_IRQDIS);
228 1.1 bouyer }
229 1.1 bouyer /* set clocks, etc (mandatory on 372/4, optional otherwise) */
230 1.1 bouyer if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
231 1.1 bouyer revision == HPT372_REV ) ||
232 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 ||
233 1.1 bouyer sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
234 1.1 bouyer pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2,
235 1.1 bouyer (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) &
236 1.1 bouyer HPT_SC2_MAEN) | HPT_SC2_OSC_EN);
237 1.1 bouyer return;
238 1.1 bouyer }
239 1.1 bouyer
240 1.2 thorpej static void
241 1.2 thorpej hpt_setup_channel(struct channel_softc *chp)
242 1.1 bouyer {
243 1.1 bouyer struct ata_drive_datas *drvp;
244 1.1 bouyer int drive;
245 1.1 bouyer int cable;
246 1.1 bouyer u_int32_t before, after;
247 1.1 bouyer u_int32_t idedma_ctl;
248 1.1 bouyer struct pciide_channel *cp = (struct pciide_channel*)chp;
249 1.1 bouyer struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
250 1.1 bouyer int revision =
251 1.1 bouyer PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
252 1.1 bouyer
253 1.1 bouyer cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL);
254 1.1 bouyer
255 1.1 bouyer /* setup DMA if needed */
256 1.1 bouyer pciide_channel_dma_setup(cp);
257 1.1 bouyer
258 1.1 bouyer idedma_ctl = 0;
259 1.1 bouyer
260 1.1 bouyer /* Per drive settings */
261 1.1 bouyer for (drive = 0; drive < 2; drive++) {
262 1.1 bouyer drvp = &chp->ch_drive[drive];
263 1.1 bouyer /* If no drive, skip */
264 1.1 bouyer if ((drvp->drive_flags & DRIVE) == 0)
265 1.1 bouyer continue;
266 1.1 bouyer before = pci_conf_read(sc->sc_pc, sc->sc_tag,
267 1.1 bouyer HPT_IDETIM(chp->channel, drive));
268 1.1 bouyer
269 1.1 bouyer /* add timing values, setup DMA if needed */
270 1.1 bouyer if (drvp->drive_flags & DRIVE_UDMA) {
271 1.1 bouyer /* use Ultra/DMA */
272 1.1 bouyer drvp->drive_flags &= ~DRIVE_DMA;
273 1.1 bouyer if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 &&
274 1.1 bouyer drvp->UDMA_mode > 2)
275 1.1 bouyer drvp->UDMA_mode = 2;
276 1.1 bouyer switch (sc->sc_pp->ide_product) {
277 1.1 bouyer case PCI_PRODUCT_TRIONES_HPT374:
278 1.1 bouyer after = hpt374_udma[drvp->UDMA_mode];
279 1.1 bouyer break;
280 1.1 bouyer case PCI_PRODUCT_TRIONES_HPT372:
281 1.1 bouyer after = hpt372_udma[drvp->UDMA_mode];
282 1.1 bouyer break;
283 1.1 bouyer case PCI_PRODUCT_TRIONES_HPT366:
284 1.1 bouyer default:
285 1.1 bouyer switch(revision) {
286 1.1 bouyer case HPT372_REV:
287 1.1 bouyer after = hpt372_udma[drvp->UDMA_mode];
288 1.1 bouyer break;
289 1.1 bouyer case HPT370_REV:
290 1.1 bouyer case HPT370A_REV:
291 1.1 bouyer after = hpt370_udma[drvp->UDMA_mode];
292 1.1 bouyer break;
293 1.1 bouyer case HPT366_REV:
294 1.1 bouyer default:
295 1.1 bouyer after = hpt366_udma[drvp->UDMA_mode];
296 1.1 bouyer break;
297 1.1 bouyer }
298 1.1 bouyer }
299 1.1 bouyer idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
300 1.1 bouyer } else if (drvp->drive_flags & DRIVE_DMA) {
301 1.1 bouyer /*
302 1.1 bouyer * use Multiword DMA.
303 1.1 bouyer * Timings will be used for both PIO and DMA, so adjust
304 1.1 bouyer * DMA mode if needed
305 1.1 bouyer */
306 1.1 bouyer if (drvp->PIO_mode >= 3 &&
307 1.1 bouyer (drvp->DMA_mode + 2) > drvp->PIO_mode) {
308 1.1 bouyer drvp->DMA_mode = drvp->PIO_mode - 2;
309 1.1 bouyer }
310 1.1 bouyer switch (sc->sc_pp->ide_product) {
311 1.1 bouyer case PCI_PRODUCT_TRIONES_HPT374:
312 1.1 bouyer after = hpt374_dma[drvp->DMA_mode];
313 1.1 bouyer break;
314 1.1 bouyer case PCI_PRODUCT_TRIONES_HPT372:
315 1.1 bouyer after = hpt372_dma[drvp->DMA_mode];
316 1.1 bouyer break;
317 1.1 bouyer case PCI_PRODUCT_TRIONES_HPT366:
318 1.1 bouyer default:
319 1.1 bouyer switch(revision) {
320 1.1 bouyer case HPT372_REV:
321 1.1 bouyer after = hpt372_dma[drvp->DMA_mode];
322 1.1 bouyer break;
323 1.1 bouyer case HPT370_REV:
324 1.1 bouyer case HPT370A_REV:
325 1.1 bouyer after = hpt370_dma[drvp->DMA_mode];
326 1.1 bouyer break;
327 1.1 bouyer case HPT366_REV:
328 1.1 bouyer default:
329 1.1 bouyer after = hpt366_dma[drvp->DMA_mode];
330 1.1 bouyer break;
331 1.1 bouyer }
332 1.1 bouyer }
333 1.1 bouyer idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
334 1.1 bouyer } else {
335 1.1 bouyer /* PIO only */
336 1.1 bouyer switch (sc->sc_pp->ide_product) {
337 1.1 bouyer case PCI_PRODUCT_TRIONES_HPT374:
338 1.1 bouyer after = hpt374_pio[drvp->PIO_mode];
339 1.1 bouyer break;
340 1.1 bouyer case PCI_PRODUCT_TRIONES_HPT372:
341 1.1 bouyer after = hpt372_pio[drvp->PIO_mode];
342 1.1 bouyer break;
343 1.1 bouyer case PCI_PRODUCT_TRIONES_HPT366:
344 1.1 bouyer default:
345 1.1 bouyer switch(revision) {
346 1.1 bouyer case HPT372_REV:
347 1.1 bouyer after = hpt372_pio[drvp->PIO_mode];
348 1.1 bouyer break;
349 1.1 bouyer case HPT370_REV:
350 1.1 bouyer case HPT370A_REV:
351 1.1 bouyer after = hpt370_pio[drvp->PIO_mode];
352 1.1 bouyer break;
353 1.1 bouyer case HPT366_REV:
354 1.1 bouyer default:
355 1.1 bouyer after = hpt366_pio[drvp->PIO_mode];
356 1.1 bouyer break;
357 1.1 bouyer }
358 1.1 bouyer }
359 1.1 bouyer }
360 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag,
361 1.1 bouyer HPT_IDETIM(chp->channel, drive), after);
362 1.1 bouyer WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x "
363 1.1 bouyer "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname,
364 1.1 bouyer after, before), DEBUG_PROBE);
365 1.1 bouyer }
366 1.1 bouyer if (idedma_ctl != 0) {
367 1.1 bouyer /* Add software bits in status register */
368 1.1 bouyer bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
369 1.1 bouyer IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel),
370 1.1 bouyer idedma_ctl);
371 1.1 bouyer }
372 1.1 bouyer }
373 1.1 bouyer
374 1.2 thorpej static int
375 1.2 thorpej hpt_pci_intr(void *arg)
376 1.1 bouyer {
377 1.1 bouyer struct pciide_softc *sc = arg;
378 1.1 bouyer struct pciide_channel *cp;
379 1.1 bouyer struct channel_softc *wdc_cp;
380 1.1 bouyer int rv = 0;
381 1.1 bouyer int dmastat, i, crv;
382 1.1 bouyer
383 1.1 bouyer for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
384 1.1 bouyer dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh,
385 1.1 bouyer IDEDMA_CTL + IDEDMA_SCH_OFFSET * i);
386 1.1 bouyer if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
387 1.1 bouyer IDEDMA_CTL_INTR)
388 1.1 bouyer continue;
389 1.1 bouyer cp = &sc->pciide_channels[i];
390 1.1 bouyer wdc_cp = &cp->wdc_channel;
391 1.1 bouyer crv = wdcintr(wdc_cp);
392 1.1 bouyer if (crv == 0) {
393 1.1 bouyer printf("%s:%d: bogus intr\n",
394 1.1 bouyer sc->sc_wdcdev.sc_dev.dv_xname, i);
395 1.1 bouyer bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh,
396 1.1 bouyer IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat);
397 1.1 bouyer } else
398 1.1 bouyer rv = 1;
399 1.1 bouyer }
400 1.1 bouyer return rv;
401 1.1 bouyer }
402