hptide.c revision 1.10.2.7
1 /* $NetBSD: hptide.c,v 1.10.2.7 2005/11/10 14:06:01 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hptide.c,v 1.10.2.7 2005/11/10 14:06:01 skrll Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_hpt_reg.h> 43 44 static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*); 45 static void hpt_setup_channel(struct ata_channel*); 46 static int hpt_pci_intr(void *); 47 48 static int hptide_match(struct device *, struct cfdata *, void *); 49 static void hptide_attach(struct device *, struct device *, void *); 50 51 CFATTACH_DECL(hptide, sizeof(struct pciide_softc), 52 hptide_match, hptide_attach, NULL, NULL); 53 54 static const struct pciide_product_desc pciide_triones_products[] = { 55 { PCI_PRODUCT_TRIONES_HPT302, 56 0, 57 NULL, 58 hpt_chip_map 59 }, 60 { PCI_PRODUCT_TRIONES_HPT366, 61 0, 62 NULL, 63 hpt_chip_map, 64 }, 65 { PCI_PRODUCT_TRIONES_HPT371, 66 0, 67 NULL, 68 hpt_chip_map, 69 }, 70 { PCI_PRODUCT_TRIONES_HPT372A, 71 0, 72 NULL, 73 hpt_chip_map 74 }, 75 { PCI_PRODUCT_TRIONES_HPT374, 76 0, 77 NULL, 78 hpt_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static int 88 hptide_match(struct device *parent, struct cfdata *match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) { 93 if (pciide_lookup_product(pa->pa_id, pciide_triones_products)) 94 return (2); 95 } 96 return (0); 97 } 98 99 static void 100 hptide_attach(struct device *parent, struct device *self, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 struct pciide_softc *sc = (struct pciide_softc *)self; 104 105 pciide_common_attach(sc, pa, 106 pciide_lookup_product(pa->pa_id, pciide_triones_products)); 107 108 } 109 110 static void 111 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 112 { 113 struct pciide_channel *cp; 114 int i, compatchan, revision; 115 pcireg_t interface; 116 bus_size_t cmdsize, ctlsize; 117 118 if (pciide_chipen(sc, pa) == 0) 119 return; 120 121 revision = PCI_REVISION(pa->pa_class); 122 aprint_normal("%s: Triones/Highpoint ", 123 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 124 switch (sc->sc_pp->ide_product) { 125 case PCI_PRODUCT_TRIONES_HPT302: 126 aprint_normal("HPT302 IDE Controller\n"); 127 break; 128 case PCI_PRODUCT_TRIONES_HPT371: 129 aprint_normal("HPT371 IDE Controller\n"); 130 break; 131 case PCI_PRODUCT_TRIONES_HPT374: 132 aprint_normal("HPT374 IDE Controller\n"); 133 break; 134 case PCI_PRODUCT_TRIONES_HPT372A: 135 aprint_normal("HPT372A IDE Controller\n"); 136 break; 137 case PCI_PRODUCT_TRIONES_HPT366: 138 if (revision == HPT372_REV) 139 aprint_normal("HPT372 IDE Controller\n"); 140 else if (revision == HPT370_REV) 141 aprint_normal("HPT370 IDE Controller\n"); 142 else if (revision == HPT370A_REV) 143 aprint_normal("HPT370A IDE Controller\n"); 144 else if (revision == HPT366_REV) 145 aprint_normal("HPT366 IDE Controller\n"); 146 else 147 aprint_normal("unknown HPT IDE controller rev %d\n", 148 revision); 149 break; 150 default: 151 aprint_normal("unknown HPT IDE controller 0x%x\n", 152 sc->sc_pp->ide_product); 153 } 154 155 /* 156 * when the chip is in native mode it identifies itself as a 157 * 'misc mass storage'. Fake interface in this case. 158 */ 159 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 160 interface = PCI_INTERFACE(pa->pa_class); 161 } else { 162 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 163 PCIIDE_INTERFACE_PCI(0); 164 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 165 (revision == HPT370_REV || revision == HPT370A_REV || 166 revision == HPT372_REV)) || 167 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 168 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 169 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 170 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 171 interface |= PCIIDE_INTERFACE_PCI(1); 172 } 173 174 aprint_normal("%s: bus-master DMA support present", 175 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 176 pciide_mapreg_dma(sc, pa); 177 aprint_normal("\n"); 178 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 179 if (sc->sc_dma_ok) { 180 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 181 sc->sc_wdcdev.irqack = pciide_irqack; 182 } 183 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 184 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 185 186 sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel; 187 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 188 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 189 revision == HPT366_REV) { 190 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 191 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 192 } else { 193 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 194 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 195 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 196 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 197 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 198 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 199 revision == HPT372_REV)) 200 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 201 else 202 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 203 } 204 205 wdc_allocate_regs(&sc->sc_wdcdev); 206 207 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 208 cp = &sc->pciide_channels[i]; 209 if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) { 210 compatchan = i; 211 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 212 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 213 aprint_normal( 214 "%s: %s channel ignored (disabled)\n", 215 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 216 cp->ata_channel.ch_flags |= ATACH_DISABLED; 217 continue; 218 } 219 } else { 220 /* 221 * The 366 has 2 PCI IDE functions, one for primary and 222 * one for secondary. So we need to call 223 * pciide_mapregs_compat() with the real channel. 224 */ 225 if (pa->pa_function == 0) 226 compatchan = 0; 227 else if (pa->pa_function == 1) 228 compatchan = 1; 229 else { 230 aprint_error("%s: unexpected PCI function %d\n", 231 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, pa->pa_function); 232 return; 233 } 234 } 235 if (pciide_chansetup(sc, i, interface) == 0) 236 continue; 237 if (interface & PCIIDE_INTERFACE_PCI(i)) { 238 pciide_mapregs_native(pa, cp, &cmdsize, 239 &ctlsize, hpt_pci_intr); 240 } else { 241 pciide_mapregs_compat(pa, cp, compatchan, 242 &cmdsize, &ctlsize); 243 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 244 pciide_map_compat_intr(pa, cp, 245 sc->sc_cy_compatchan); 246 } 247 wdcattach(&cp->ata_channel); 248 } 249 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 250 (revision == HPT370_REV || revision == HPT370A_REV || 251 revision == HPT372_REV)) || 252 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 253 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 254 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 255 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 256 /* 257 * HPT370_REV and highter has a bit to disable interrupts, 258 * make sure to clear it 259 */ 260 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 261 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 262 ~HPT_CSEL_IRQDIS); 263 } 264 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 265 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 266 revision == HPT372_REV ) || 267 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 268 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 269 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 270 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 271 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 272 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 273 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 274 return; 275 } 276 277 static void 278 hpt_setup_channel(struct ata_channel *chp) 279 { 280 struct ata_drive_datas *drvp; 281 int drive, s; 282 int cable; 283 u_int32_t before, after; 284 u_int32_t idedma_ctl; 285 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 286 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 287 int revision = 288 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 289 const u_int32_t *tim_pio, *tim_dma, *tim_udma; 290 291 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 292 293 /* setup DMA if needed */ 294 pciide_channel_dma_setup(cp); 295 296 idedma_ctl = 0; 297 298 /* select the timing arrays for the chip */ 299 switch (sc->sc_pp->ide_product) { 300 case PCI_PRODUCT_TRIONES_HPT374: 301 tim_udma = hpt374_udma; 302 tim_dma = hpt374_dma; 303 tim_pio = hpt374_pio; 304 break; 305 case PCI_PRODUCT_TRIONES_HPT302: 306 case PCI_PRODUCT_TRIONES_HPT371: 307 case PCI_PRODUCT_TRIONES_HPT372A: 308 tim_udma = hpt372_udma; 309 tim_dma = hpt372_dma; 310 tim_pio = hpt372_pio; 311 break; 312 case PCI_PRODUCT_TRIONES_HPT366: 313 default: 314 switch (revision) { 315 case HPT372_REV: 316 tim_udma = hpt372_udma; 317 tim_dma = hpt372_dma; 318 tim_pio = hpt372_pio; 319 break; 320 case HPT370_REV: 321 case HPT370A_REV: 322 tim_udma = hpt370_udma; 323 tim_dma = hpt370_dma; 324 tim_pio = hpt370_pio; 325 break; 326 case HPT366_REV: 327 default: 328 tim_udma = hpt366_udma; 329 tim_dma = hpt366_dma; 330 tim_pio = hpt366_pio; 331 break; 332 } 333 } 334 335 /* Per drive settings */ 336 for (drive = 0; drive < 2; drive++) { 337 drvp = &chp->ch_drive[drive]; 338 /* If no drive, skip */ 339 if ((drvp->drive_flags & DRIVE) == 0) 340 continue; 341 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 342 HPT_IDETIM(chp->ch_channel, drive)); 343 344 /* add timing values, setup DMA if needed */ 345 if (drvp->drive_flags & DRIVE_UDMA) { 346 /* use Ultra/DMA */ 347 s = splbio(); 348 drvp->drive_flags &= ~DRIVE_DMA; 349 splx(s); 350 if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 && 351 drvp->UDMA_mode > 2) 352 drvp->UDMA_mode = 2; 353 after = tim_udma[drvp->UDMA_mode]; 354 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 355 } else if (drvp->drive_flags & DRIVE_DMA) { 356 /* 357 * use Multiword DMA. 358 * Timings will be used for both PIO and DMA, so adjust 359 * DMA mode if needed 360 */ 361 if (drvp->PIO_mode >= 3 && 362 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 363 drvp->DMA_mode = drvp->PIO_mode - 2; 364 } 365 after = tim_dma[drvp->DMA_mode]; 366 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 367 } else { 368 /* PIO only */ 369 after = tim_pio[drvp->PIO_mode]; 370 } 371 pci_conf_write(sc->sc_pc, sc->sc_tag, 372 HPT_IDETIM(chp->ch_channel, drive), after); 373 ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x " 374 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 375 after, before), DEBUG_PROBE); 376 } 377 if (idedma_ctl != 0) { 378 /* Add software bits in status register */ 379 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 380 idedma_ctl); 381 } 382 } 383 384 static int 385 hpt_pci_intr(void *arg) 386 { 387 struct pciide_softc *sc = arg; 388 struct pciide_channel *cp; 389 struct ata_channel *wdc_cp; 390 int rv = 0; 391 int dmastat, i, crv; 392 393 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 394 cp = &sc->pciide_channels[i]; 395 dmastat = bus_space_read_1(sc->sc_dma_iot, 396 cp->dma_iohs[IDEDMA_CTL], 0); 397 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 398 IDEDMA_CTL_INTR) 399 continue; 400 wdc_cp = &cp->ata_channel; 401 crv = wdcintr(wdc_cp); 402 if (crv == 0) { 403 printf("%s:%d: bogus intr\n", 404 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 405 bus_space_write_1(sc->sc_dma_iot, 406 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 407 } else 408 rv = 1; 409 } 410 return rv; 411 } 412
Indexes created Sat Oct 18 23:09:54 GMT 2025