hptide.c revision 1.16
1 /* $NetBSD: hptide.c,v 1.16 2004/08/21 00:28:34 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_hpt_reg.h> 40 41 static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*); 42 static void hpt_setup_channel(struct ata_channel*); 43 static int hpt_pci_intr(void *); 44 45 static int hptide_match(struct device *, struct cfdata *, void *); 46 static void hptide_attach(struct device *, struct device *, void *); 47 48 CFATTACH_DECL(hptide, sizeof(struct pciide_softc), 49 hptide_match, hptide_attach, NULL, NULL); 50 51 static const struct pciide_product_desc pciide_triones_products[] = { 52 { PCI_PRODUCT_TRIONES_HPT302, 53 0, 54 NULL, 55 hpt_chip_map 56 }, 57 { PCI_PRODUCT_TRIONES_HPT366, 58 0, 59 NULL, 60 hpt_chip_map, 61 }, 62 { PCI_PRODUCT_TRIONES_HPT371, 63 0, 64 NULL, 65 hpt_chip_map, 66 }, 67 { PCI_PRODUCT_TRIONES_HPT372A, 68 0, 69 NULL, 70 hpt_chip_map 71 }, 72 { PCI_PRODUCT_TRIONES_HPT374, 73 0, 74 NULL, 75 hpt_chip_map 76 }, 77 { 0, 78 0, 79 NULL, 80 NULL 81 } 82 }; 83 84 static int 85 hptide_match(struct device *parent, struct cfdata *match, void *aux) 86 { 87 struct pci_attach_args *pa = aux; 88 89 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) { 90 if (pciide_lookup_product(pa->pa_id, pciide_triones_products)) 91 return (2); 92 } 93 return (0); 94 } 95 96 static void 97 hptide_attach(struct device *parent, struct device *self, void *aux) 98 { 99 struct pci_attach_args *pa = aux; 100 struct pciide_softc *sc = (struct pciide_softc *)self; 101 102 pciide_common_attach(sc, pa, 103 pciide_lookup_product(pa->pa_id, pciide_triones_products)); 104 105 } 106 107 static void 108 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 109 { 110 struct pciide_channel *cp; 111 int i, compatchan, revision; 112 pcireg_t interface; 113 bus_size_t cmdsize, ctlsize; 114 115 if (pciide_chipen(sc, pa) == 0) 116 return; 117 118 revision = PCI_REVISION(pa->pa_class); 119 aprint_normal("%s: Triones/Highpoint ", 120 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 121 switch (sc->sc_pp->ide_product) { 122 case PCI_PRODUCT_TRIONES_HPT302: 123 aprint_normal("HPT302 IDE Controller\n"); 124 break; 125 case PCI_PRODUCT_TRIONES_HPT371: 126 aprint_normal("HPT371 IDE Controller\n"); 127 break; 128 case PCI_PRODUCT_TRIONES_HPT374: 129 aprint_normal("HPT374 IDE Controller\n"); 130 break; 131 case PCI_PRODUCT_TRIONES_HPT372A: 132 aprint_normal("HPT372A IDE Controller\n"); 133 break; 134 case PCI_PRODUCT_TRIONES_HPT366: 135 if (revision == HPT372_REV) 136 aprint_normal("HPT372 IDE Controller\n"); 137 else if (revision == HPT370_REV) 138 aprint_normal("HPT370 IDE Controller\n"); 139 else if (revision == HPT370A_REV) 140 aprint_normal("HPT370A IDE Controller\n"); 141 else if (revision == HPT366_REV) 142 aprint_normal("HPT366 IDE Controller\n"); 143 else 144 aprint_normal("unknown HPT IDE controller rev %d\n", 145 revision); 146 break; 147 default: 148 aprint_normal("unknown HPT IDE controller 0x%x\n", 149 sc->sc_pp->ide_product); 150 } 151 152 /* 153 * when the chip is in native mode it identifies itself as a 154 * 'misc mass storage'. Fake interface in this case. 155 */ 156 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 157 interface = PCI_INTERFACE(pa->pa_class); 158 } else { 159 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 160 PCIIDE_INTERFACE_PCI(0); 161 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 162 (revision == HPT370_REV || revision == HPT370A_REV || 163 revision == HPT372_REV)) || 164 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 165 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 166 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 167 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 168 interface |= PCIIDE_INTERFACE_PCI(1); 169 } 170 171 aprint_normal("%s: bus-master DMA support present", 172 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 173 pciide_mapreg_dma(sc, pa); 174 aprint_normal("\n"); 175 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 176 if (sc->sc_dma_ok) { 177 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 178 sc->sc_wdcdev.irqack = pciide_irqack; 179 } 180 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 181 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 182 183 sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel; 184 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 185 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 186 revision == HPT366_REV) { 187 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 188 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 189 } else { 190 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 191 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 192 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 193 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 194 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 195 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 196 revision == HPT372_REV)) 197 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 198 else 199 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 200 } 201 202 wdc_allocate_regs(&sc->sc_wdcdev); 203 204 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 205 cp = &sc->pciide_channels[i]; 206 if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) { 207 compatchan = i; 208 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 209 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 210 aprint_normal( 211 "%s: %s channel ignored (disabled)\n", 212 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 213 cp->ata_channel.ch_flags |= ATACH_DISABLED; 214 continue; 215 } 216 } else { 217 /* 218 * The 366 has 2 PCI IDE functions, one for primary and 219 * one for secondary. So we need to call 220 * pciide_mapregs_compat() with the real channel. 221 */ 222 if (pa->pa_function == 0) 223 compatchan = 0; 224 else if (pa->pa_function == 1) 225 compatchan = 1; 226 else { 227 aprint_error("%s: unexpected PCI function %d\n", 228 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, pa->pa_function); 229 return; 230 } 231 } 232 if (pciide_chansetup(sc, i, interface) == 0) 233 continue; 234 if (interface & PCIIDE_INTERFACE_PCI(i)) { 235 pciide_mapregs_native(pa, cp, &cmdsize, 236 &ctlsize, hpt_pci_intr); 237 } else { 238 pciide_mapregs_compat(pa, cp, compatchan, 239 &cmdsize, &ctlsize); 240 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 241 pciide_map_compat_intr(pa, cp, 242 sc->sc_cy_compatchan); 243 } 244 wdcattach(&cp->ata_channel); 245 } 246 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 247 (revision == HPT370_REV || revision == HPT370A_REV || 248 revision == HPT372_REV)) || 249 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 250 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 251 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 252 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 253 /* 254 * HPT370_REV and highter has a bit to disable interrupts, 255 * make sure to clear it 256 */ 257 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 258 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 259 ~HPT_CSEL_IRQDIS); 260 } 261 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 262 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 263 revision == HPT372_REV ) || 264 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 265 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 266 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 267 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 268 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 269 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 270 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 271 return; 272 } 273 274 static void 275 hpt_setup_channel(struct ata_channel *chp) 276 { 277 struct ata_drive_datas *drvp; 278 int drive, s; 279 int cable; 280 u_int32_t before, after; 281 u_int32_t idedma_ctl; 282 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 283 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 284 int revision = 285 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 286 const u_int32_t *tim_pio, *tim_dma, *tim_udma; 287 288 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 289 290 /* setup DMA if needed */ 291 pciide_channel_dma_setup(cp); 292 293 idedma_ctl = 0; 294 295 /* select the timing arrays for the chip */ 296 switch (sc->sc_pp->ide_product) { 297 case PCI_PRODUCT_TRIONES_HPT374: 298 tim_udma = hpt374_udma; 299 tim_dma = hpt374_dma; 300 tim_pio = hpt374_pio; 301 break; 302 case PCI_PRODUCT_TRIONES_HPT302: 303 case PCI_PRODUCT_TRIONES_HPT371: 304 case PCI_PRODUCT_TRIONES_HPT372A: 305 tim_udma = hpt372_udma; 306 tim_dma = hpt372_dma; 307 tim_pio = hpt372_pio; 308 break; 309 case PCI_PRODUCT_TRIONES_HPT366: 310 default: 311 switch (revision) { 312 case HPT372_REV: 313 tim_udma = hpt372_udma; 314 tim_dma = hpt372_dma; 315 tim_pio = hpt372_pio; 316 break; 317 case HPT370_REV: 318 case HPT370A_REV: 319 tim_udma = hpt370_udma; 320 tim_dma = hpt370_dma; 321 tim_pio = hpt370_pio; 322 break; 323 case HPT366_REV: 324 default: 325 tim_udma = hpt366_udma; 326 tim_dma = hpt366_dma; 327 tim_pio = hpt366_pio; 328 break; 329 } 330 } 331 332 /* Per drive settings */ 333 for (drive = 0; drive < 2; drive++) { 334 drvp = &chp->ch_drive[drive]; 335 /* If no drive, skip */ 336 if ((drvp->drive_flags & DRIVE) == 0) 337 continue; 338 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 339 HPT_IDETIM(chp->ch_channel, drive)); 340 341 /* add timing values, setup DMA if needed */ 342 if (drvp->drive_flags & DRIVE_UDMA) { 343 /* use Ultra/DMA */ 344 s = splbio(); 345 drvp->drive_flags &= ~DRIVE_DMA; 346 splx(s); 347 if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 && 348 drvp->UDMA_mode > 2) 349 drvp->UDMA_mode = 2; 350 after = tim_udma[drvp->UDMA_mode]; 351 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 352 } else if (drvp->drive_flags & DRIVE_DMA) { 353 /* 354 * use Multiword DMA. 355 * Timings will be used for both PIO and DMA, so adjust 356 * DMA mode if needed 357 */ 358 if (drvp->PIO_mode >= 3 && 359 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 360 drvp->DMA_mode = drvp->PIO_mode - 2; 361 } 362 after = tim_dma[drvp->DMA_mode]; 363 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 364 } else { 365 /* PIO only */ 366 after = tim_pio[drvp->PIO_mode]; 367 } 368 pci_conf_write(sc->sc_pc, sc->sc_tag, 369 HPT_IDETIM(chp->ch_channel, drive), after); 370 ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x " 371 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 372 after, before), DEBUG_PROBE); 373 } 374 if (idedma_ctl != 0) { 375 /* Add software bits in status register */ 376 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 377 idedma_ctl); 378 } 379 } 380 381 static int 382 hpt_pci_intr(void *arg) 383 { 384 struct pciide_softc *sc = arg; 385 struct pciide_channel *cp; 386 struct ata_channel *wdc_cp; 387 int rv = 0; 388 int dmastat, i, crv; 389 390 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 391 cp = &sc->pciide_channels[i]; 392 dmastat = bus_space_read_1(sc->sc_dma_iot, 393 cp->dma_iohs[IDEDMA_CTL], 0); 394 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 395 IDEDMA_CTL_INTR) 396 continue; 397 wdc_cp = &cp->ata_channel; 398 crv = wdcintr(wdc_cp); 399 if (crv == 0) { 400 printf("%s:%d: bogus intr\n", 401 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 402 bus_space_write_1(sc->sc_dma_iot, 403 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 404 } else 405 rv = 1; 406 } 407 return rv; 408 } 409
Indexes created Wed Oct 15 16:09:53 GMT 2025