hptide.c revision 1.17.2.1 1 /* $NetBSD: hptide.c,v 1.17.2.1 2006/08/06 08:44:07 ghen Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Manuel Bouyer.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34
35 #include <dev/pci/pcivar.h>
36 #include <dev/pci/pcidevs.h>
37 #include <dev/pci/pciidereg.h>
38 #include <dev/pci/pciidevar.h>
39 #include <dev/pci/pciide_hpt_reg.h>
40
41 static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*);
42 static void hpt_setup_channel(struct ata_channel*);
43 static int hpt_pci_intr(void *);
44
45 static int hptide_match(struct device *, struct cfdata *, void *);
46 static void hptide_attach(struct device *, struct device *, void *);
47
48 CFATTACH_DECL(hptide, sizeof(struct pciide_softc),
49 hptide_match, hptide_attach, NULL, NULL);
50
51 static const struct pciide_product_desc pciide_triones_products[] = {
52 { PCI_PRODUCT_TRIONES_HPT302,
53 0,
54 NULL,
55 hpt_chip_map
56 },
57 { PCI_PRODUCT_TRIONES_HPT366,
58 0,
59 NULL,
60 hpt_chip_map,
61 },
62 { PCI_PRODUCT_TRIONES_HPT371,
63 0,
64 NULL,
65 hpt_chip_map,
66 },
67 { PCI_PRODUCT_TRIONES_HPT372A,
68 0,
69 NULL,
70 hpt_chip_map
71 },
72 { PCI_PRODUCT_TRIONES_HPT374,
73 0,
74 NULL,
75 hpt_chip_map
76 },
77 { 0,
78 0,
79 NULL,
80 NULL
81 }
82 };
83
84 static int
85 hptide_match(struct device *parent, struct cfdata *match, void *aux)
86 {
87 struct pci_attach_args *pa = aux;
88
89 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) {
90 if (pciide_lookup_product(pa->pa_id, pciide_triones_products))
91 return (2);
92 }
93 return (0);
94 }
95
96 static void
97 hptide_attach(struct device *parent, struct device *self, void *aux)
98 {
99 struct pci_attach_args *pa = aux;
100 struct pciide_softc *sc = (struct pciide_softc *)self;
101
102 pciide_common_attach(sc, pa,
103 pciide_lookup_product(pa->pa_id, pciide_triones_products));
104
105 }
106
107 static void
108 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
109 {
110 struct pciide_channel *cp;
111 int i, compatchan, revision;
112 pcireg_t interface;
113 bus_size_t cmdsize, ctlsize;
114
115 if (pciide_chipen(sc, pa) == 0)
116 return;
117
118 revision = PCI_REVISION(pa->pa_class);
119 aprint_normal("%s: Triones/Highpoint ",
120 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
121 switch (sc->sc_pp->ide_product) {
122 case PCI_PRODUCT_TRIONES_HPT302:
123 aprint_normal("HPT302 IDE Controller\n");
124 break;
125 case PCI_PRODUCT_TRIONES_HPT371:
126 aprint_normal("HPT371 IDE Controller\n");
127 break;
128 case PCI_PRODUCT_TRIONES_HPT374:
129 aprint_normal("HPT374 IDE Controller\n");
130 break;
131 case PCI_PRODUCT_TRIONES_HPT372A:
132 aprint_normal("HPT372A IDE Controller\n");
133 break;
134 case PCI_PRODUCT_TRIONES_HPT366:
135 if (revision == HPT372_REV)
136 aprint_normal("HPT372 IDE Controller\n");
137 else if (revision == HPT370_REV)
138 aprint_normal("HPT370 IDE Controller\n");
139 else if (revision == HPT370A_REV)
140 aprint_normal("HPT370A IDE Controller\n");
141 else if (revision == HPT368_REV)
142 aprint_normal("HPT368 IDE Controller\n");
143 else if (revision == HPT366_REV)
144 aprint_normal("HPT366 IDE Controller\n");
145 else
146 aprint_normal("unknown HPT IDE controller rev %d\n",
147 revision);
148 break;
149 default:
150 aprint_normal("unknown HPT IDE controller 0x%x\n",
151 sc->sc_pp->ide_product);
152 }
153
154 /*
155 * when the chip is in native mode it identifies itself as a
156 * 'misc mass storage'. Fake interface in this case.
157 */
158 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
159 interface = PCI_INTERFACE(pa->pa_class);
160 } else {
161 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
162 PCIIDE_INTERFACE_PCI(0);
163 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
164 (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV ||
165 revision == HPT372_REV)) ||
166 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
167 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
168 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
169 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
170 interface |= PCIIDE_INTERFACE_PCI(1);
171 }
172
173 aprint_normal("%s: bus-master DMA support present",
174 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
175 pciide_mapreg_dma(sc, pa);
176 aprint_normal("\n");
177 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
178 if (sc->sc_dma_ok) {
179 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
180 sc->sc_wdcdev.irqack = pciide_irqack;
181 }
182 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
183 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
184
185 sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel;
186 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
187 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
188 (revision == HPT366_REV || revision == HPT368_REV)) {
189 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
190 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
191 } else {
192 sc->sc_wdcdev.sc_atac.atac_nchannels = 2;
193 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 ||
194 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
195 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
196 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
197 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
198 revision == HPT372_REV))
199 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
200 else
201 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
202 }
203
204 wdc_allocate_regs(&sc->sc_wdcdev);
205
206 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
207 cp = &sc->pciide_channels[i];
208 if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) {
209 compatchan = i;
210 if((pciide_pci_read(sc->sc_pc, sc->sc_tag,
211 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) {
212 aprint_normal(
213 "%s: %s channel ignored (disabled)\n",
214 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
215 cp->ata_channel.ch_flags |= ATACH_DISABLED;
216 continue;
217 }
218 } else {
219 /*
220 * The 366 has 2 PCI IDE functions, one for primary and
221 * one for secondary. So we need to call
222 * pciide_mapregs_compat() with the real channel.
223 */
224 if (pa->pa_function == 0)
225 compatchan = 0;
226 else if (pa->pa_function == 1)
227 compatchan = 1;
228 else {
229 aprint_error("%s: unexpected PCI function %d\n",
230 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, pa->pa_function);
231 return;
232 }
233 }
234 if (pciide_chansetup(sc, i, interface) == 0)
235 continue;
236 if (interface & PCIIDE_INTERFACE_PCI(i)) {
237 pciide_mapregs_native(pa, cp, &cmdsize,
238 &ctlsize, hpt_pci_intr);
239 } else {
240 pciide_mapregs_compat(pa, cp, compatchan,
241 &cmdsize, &ctlsize);
242 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
243 pciide_map_compat_intr(pa, cp,
244 sc->sc_cy_compatchan);
245 }
246 wdcattach(&cp->ata_channel);
247 }
248 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
249 (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV ||
250 revision == HPT372_REV)) ||
251 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
252 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
253 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
254 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) {
255 /*
256 * HPT370_REV and highter has a bit to disable interrupts,
257 * make sure to clear it
258 */
259 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL,
260 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) &
261 ~HPT_CSEL_IRQDIS);
262 }
263 /* set clocks, etc (mandatory on 372/4, optional otherwise) */
264 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
265 revision == HPT372_REV ) ||
266 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
267 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
268 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
269 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
270 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2,
271 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) &
272 HPT_SC2_MAEN) | HPT_SC2_OSC_EN);
273 return;
274 }
275
276 static void
277 hpt_setup_channel(struct ata_channel *chp)
278 {
279 struct ata_drive_datas *drvp;
280 int drive, s;
281 int cable;
282 u_int32_t before, after;
283 u_int32_t idedma_ctl;
284 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
285 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
286 int revision =
287 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
288 const u_int32_t *tim_pio, *tim_dma, *tim_udma;
289
290 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL);
291
292 /* setup DMA if needed */
293 pciide_channel_dma_setup(cp);
294
295 idedma_ctl = 0;
296
297 /* select the timing arrays for the chip */
298 switch (sc->sc_pp->ide_product) {
299 case PCI_PRODUCT_TRIONES_HPT374:
300 tim_udma = hpt374_udma;
301 tim_dma = hpt374_dma;
302 tim_pio = hpt374_pio;
303 break;
304 case PCI_PRODUCT_TRIONES_HPT302:
305 case PCI_PRODUCT_TRIONES_HPT371:
306 case PCI_PRODUCT_TRIONES_HPT372A:
307 tim_udma = hpt372_udma;
308 tim_dma = hpt372_dma;
309 tim_pio = hpt372_pio;
310 break;
311 case PCI_PRODUCT_TRIONES_HPT366:
312 default:
313 switch (revision) {
314 case HPT372_REV:
315 tim_udma = hpt372_udma;
316 tim_dma = hpt372_dma;
317 tim_pio = hpt372_pio;
318 break;
319 case HPT370_REV:
320 case HPT370A_REV:
321 tim_udma = hpt370_udma;
322 tim_dma = hpt370_dma;
323 tim_pio = hpt370_pio;
324 break;
325 case HPT368_REV:
326 case HPT366_REV:
327 default:
328 tim_udma = hpt366_udma;
329 tim_dma = hpt366_dma;
330 tim_pio = hpt366_pio;
331 break;
332 }
333 }
334
335 /* Per drive settings */
336 for (drive = 0; drive < 2; drive++) {
337 drvp = &chp->ch_drive[drive];
338 /* If no drive, skip */
339 if ((drvp->drive_flags & DRIVE) == 0)
340 continue;
341 before = pci_conf_read(sc->sc_pc, sc->sc_tag,
342 HPT_IDETIM(chp->ch_channel, drive));
343
344 /* add timing values, setup DMA if needed */
345 if (drvp->drive_flags & DRIVE_UDMA) {
346 /* use Ultra/DMA */
347 s = splbio();
348 drvp->drive_flags &= ~DRIVE_DMA;
349 splx(s);
350 if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 &&
351 drvp->UDMA_mode > 2)
352 drvp->UDMA_mode = 2;
353 after = tim_udma[drvp->UDMA_mode];
354 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
355 } else if (drvp->drive_flags & DRIVE_DMA) {
356 /*
357 * use Multiword DMA.
358 * Timings will be used for both PIO and DMA, so adjust
359 * DMA mode if needed
360 */
361 if (drvp->PIO_mode >= 3 &&
362 (drvp->DMA_mode + 2) > drvp->PIO_mode) {
363 drvp->DMA_mode = drvp->PIO_mode - 2;
364 }
365 after = tim_dma[drvp->DMA_mode];
366 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
367 } else {
368 /* PIO only */
369 after = tim_pio[drvp->PIO_mode];
370 }
371 pci_conf_write(sc->sc_pc, sc->sc_tag,
372 HPT_IDETIM(chp->ch_channel, drive), after);
373 ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x "
374 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname,
375 after, before), DEBUG_PROBE);
376 }
377 if (idedma_ctl != 0) {
378 /* Add software bits in status register */
379 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
380 idedma_ctl);
381 }
382 }
383
384 static int
385 hpt_pci_intr(void *arg)
386 {
387 struct pciide_softc *sc = arg;
388 struct pciide_channel *cp;
389 struct ata_channel *wdc_cp;
390 int rv = 0;
391 int dmastat, i, crv;
392
393 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
394 cp = &sc->pciide_channels[i];
395 dmastat = bus_space_read_1(sc->sc_dma_iot,
396 cp->dma_iohs[IDEDMA_CTL], 0);
397 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
398 IDEDMA_CTL_INTR)
399 continue;
400 wdc_cp = &cp->ata_channel;
401 crv = wdcintr(wdc_cp);
402 if (crv == 0) {
403 printf("%s:%d: bogus intr\n",
404 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i);
405 bus_space_write_1(sc->sc_dma_iot,
406 cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
407 } else
408 rv = 1;
409 }
410 return rv;
411 }
412