hptide.c revision 1.20.6.1
1 /* $NetBSD: hptide.c,v 1.20.6.1 2006/08/11 15:44:25 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hptide.c,v 1.20.6.1 2006/08/11 15:44:25 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_hpt_reg.h> 43 44 static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*); 45 static void hpt_setup_channel(struct ata_channel*); 46 static int hpt_pci_intr(void *); 47 48 static int hptide_match(struct device *, struct cfdata *, void *); 49 static void hptide_attach(struct device *, struct device *, void *); 50 51 CFATTACH_DECL(hptide, sizeof(struct pciide_softc), 52 hptide_match, hptide_attach, NULL, NULL); 53 54 static const struct pciide_product_desc pciide_triones_products[] = { 55 { PCI_PRODUCT_TRIONES_HPT302, 56 0, 57 NULL, 58 hpt_chip_map 59 }, 60 { PCI_PRODUCT_TRIONES_HPT366, 61 0, 62 NULL, 63 hpt_chip_map, 64 }, 65 { PCI_PRODUCT_TRIONES_HPT371, 66 0, 67 NULL, 68 hpt_chip_map, 69 }, 70 { PCI_PRODUCT_TRIONES_HPT372A, 71 0, 72 NULL, 73 hpt_chip_map 74 }, 75 { PCI_PRODUCT_TRIONES_HPT374, 76 0, 77 NULL, 78 hpt_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static int 88 hptide_match(struct device *parent, struct cfdata *match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) { 93 if (pciide_lookup_product(pa->pa_id, pciide_triones_products)) 94 return (2); 95 } 96 return (0); 97 } 98 99 static void 100 hptide_attach(struct device *parent, struct device *self, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 struct pciide_softc *sc = (struct pciide_softc *)self; 104 105 pciide_common_attach(sc, pa, 106 pciide_lookup_product(pa->pa_id, pciide_triones_products)); 107 108 } 109 110 static void 111 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 112 { 113 struct pciide_channel *cp; 114 int i, compatchan, revision; 115 pcireg_t interface; 116 bus_size_t cmdsize, ctlsize; 117 118 if (pciide_chipen(sc, pa) == 0) 119 return; 120 121 revision = PCI_REVISION(pa->pa_class); 122 aprint_normal("%s: Triones/Highpoint ", 123 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 124 switch (sc->sc_pp->ide_product) { 125 case PCI_PRODUCT_TRIONES_HPT302: 126 aprint_normal("HPT302 IDE Controller\n"); 127 break; 128 case PCI_PRODUCT_TRIONES_HPT371: 129 aprint_normal("HPT371 IDE Controller\n"); 130 break; 131 case PCI_PRODUCT_TRIONES_HPT374: 132 aprint_normal("HPT374 IDE Controller\n"); 133 break; 134 case PCI_PRODUCT_TRIONES_HPT372A: 135 aprint_normal("HPT372A IDE Controller\n"); 136 break; 137 case PCI_PRODUCT_TRIONES_HPT366: 138 if (revision == HPT372_REV) 139 aprint_normal("HPT372 IDE Controller\n"); 140 else if (revision == HPT370_REV) 141 aprint_normal("HPT370 IDE Controller\n"); 142 else if (revision == HPT370A_REV) 143 aprint_normal("HPT370A IDE Controller\n"); 144 else if (revision == HPT368_REV) 145 aprint_normal("HPT368 IDE Controller\n"); 146 else if (revision == HPT366_REV) 147 aprint_normal("HPT366 IDE Controller\n"); 148 else 149 aprint_normal("unknown HPT IDE controller rev %d\n", 150 revision); 151 break; 152 default: 153 aprint_normal("unknown HPT IDE controller 0x%x\n", 154 sc->sc_pp->ide_product); 155 } 156 157 /* 158 * when the chip is in native mode it identifies itself as a 159 * 'misc mass storage'. Fake interface in this case. 160 */ 161 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 162 interface = PCI_INTERFACE(pa->pa_class); 163 } else { 164 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 165 PCIIDE_INTERFACE_PCI(0); 166 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 167 (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV || 168 revision == HPT372_REV)) || 169 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 170 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 171 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 172 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 173 interface |= PCIIDE_INTERFACE_PCI(1); 174 } 175 176 aprint_normal("%s: bus-master DMA support present", 177 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 178 pciide_mapreg_dma(sc, pa); 179 aprint_normal("\n"); 180 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 181 if (sc->sc_dma_ok) { 182 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 183 sc->sc_wdcdev.irqack = pciide_irqack; 184 } 185 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 186 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 187 188 sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel; 189 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 190 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 191 (revision == HPT366_REV || revision == HPT368_REV)) { 192 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 193 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 194 } else { 195 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 196 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 197 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 198 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 199 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 200 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 201 revision == HPT372_REV)) 202 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 203 else 204 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 205 } 206 207 wdc_allocate_regs(&sc->sc_wdcdev); 208 209 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 210 cp = &sc->pciide_channels[i]; 211 if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) { 212 compatchan = i; 213 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 214 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 215 aprint_normal( 216 "%s: %s channel ignored (disabled)\n", 217 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 218 cp->ata_channel.ch_flags |= ATACH_DISABLED; 219 continue; 220 } 221 } else { 222 /* 223 * The 366 has 2 PCI IDE functions, one for primary and 224 * one for secondary. So we need to call 225 * pciide_mapregs_compat() with the real channel. 226 */ 227 if (pa->pa_function == 0) 228 compatchan = 0; 229 else if (pa->pa_function == 1) 230 compatchan = 1; 231 else { 232 aprint_error("%s: unexpected PCI function %d\n", 233 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, pa->pa_function); 234 return; 235 } 236 } 237 if (pciide_chansetup(sc, i, interface) == 0) 238 continue; 239 if (interface & PCIIDE_INTERFACE_PCI(i)) { 240 pciide_mapregs_native(pa, cp, &cmdsize, 241 &ctlsize, hpt_pci_intr); 242 } else { 243 pciide_mapregs_compat(pa, cp, compatchan, 244 &cmdsize, &ctlsize); 245 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 246 pciide_map_compat_intr(pa, cp, 247 sc->sc_cy_compatchan); 248 } 249 wdcattach(&cp->ata_channel); 250 } 251 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 252 (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV || 253 revision == HPT372_REV)) || 254 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 255 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 256 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 257 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 258 /* 259 * HPT370_REV and highter has a bit to disable interrupts, 260 * make sure to clear it 261 */ 262 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 263 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 264 ~HPT_CSEL_IRQDIS); 265 } 266 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 267 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 268 revision == HPT372_REV ) || 269 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 270 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 271 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 272 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 273 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 274 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 275 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 276 return; 277 } 278 279 static void 280 hpt_setup_channel(struct ata_channel *chp) 281 { 282 struct ata_drive_datas *drvp; 283 int drive, s; 284 int cable; 285 u_int32_t before, after; 286 u_int32_t idedma_ctl; 287 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 288 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 289 int revision = 290 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 291 const u_int32_t *tim_pio, *tim_dma, *tim_udma; 292 293 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 294 295 /* setup DMA if needed */ 296 pciide_channel_dma_setup(cp); 297 298 idedma_ctl = 0; 299 300 /* select the timing arrays for the chip */ 301 switch (sc->sc_pp->ide_product) { 302 case PCI_PRODUCT_TRIONES_HPT374: 303 tim_udma = hpt374_udma; 304 tim_dma = hpt374_dma; 305 tim_pio = hpt374_pio; 306 break; 307 case PCI_PRODUCT_TRIONES_HPT302: 308 case PCI_PRODUCT_TRIONES_HPT371: 309 case PCI_PRODUCT_TRIONES_HPT372A: 310 tim_udma = hpt372_udma; 311 tim_dma = hpt372_dma; 312 tim_pio = hpt372_pio; 313 break; 314 case PCI_PRODUCT_TRIONES_HPT366: 315 default: 316 switch (revision) { 317 case HPT372_REV: 318 tim_udma = hpt372_udma; 319 tim_dma = hpt372_dma; 320 tim_pio = hpt372_pio; 321 break; 322 case HPT370_REV: 323 case HPT370A_REV: 324 tim_udma = hpt370_udma; 325 tim_dma = hpt370_dma; 326 tim_pio = hpt370_pio; 327 break; 328 case HPT368_REV: 329 case HPT366_REV: 330 default: 331 tim_udma = hpt366_udma; 332 tim_dma = hpt366_dma; 333 tim_pio = hpt366_pio; 334 break; 335 } 336 } 337 338 /* Per drive settings */ 339 for (drive = 0; drive < chp->ch_ndrive; drive++) { 340 drvp = &chp->ch_drive[drive]; 341 /* If no drive, skip */ 342 if ((drvp->drive_flags & DRIVE) == 0) 343 continue; 344 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 345 HPT_IDETIM(chp->ch_channel, drive)); 346 347 /* add timing values, setup DMA if needed */ 348 if (drvp->drive_flags & DRIVE_UDMA) { 349 /* use Ultra/DMA */ 350 s = splbio(); 351 drvp->drive_flags &= ~DRIVE_DMA; 352 splx(s); 353 if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 && 354 drvp->UDMA_mode > 2) 355 drvp->UDMA_mode = 2; 356 after = tim_udma[drvp->UDMA_mode]; 357 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 358 } else if (drvp->drive_flags & DRIVE_DMA) { 359 /* 360 * use Multiword DMA. 361 * Timings will be used for both PIO and DMA, so adjust 362 * DMA mode if needed 363 */ 364 if (drvp->PIO_mode >= 3 && 365 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 366 drvp->DMA_mode = drvp->PIO_mode - 2; 367 } 368 after = tim_dma[drvp->DMA_mode]; 369 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 370 } else { 371 /* PIO only */ 372 after = tim_pio[drvp->PIO_mode]; 373 } 374 pci_conf_write(sc->sc_pc, sc->sc_tag, 375 HPT_IDETIM(chp->ch_channel, drive), after); 376 ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x " 377 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 378 after, before), DEBUG_PROBE); 379 } 380 if (idedma_ctl != 0) { 381 /* Add software bits in status register */ 382 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 383 idedma_ctl); 384 } 385 } 386 387 static int 388 hpt_pci_intr(void *arg) 389 { 390 struct pciide_softc *sc = arg; 391 struct pciide_channel *cp; 392 struct ata_channel *wdc_cp; 393 int rv = 0; 394 int dmastat, i, crv; 395 396 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 397 cp = &sc->pciide_channels[i]; 398 dmastat = bus_space_read_1(sc->sc_dma_iot, 399 cp->dma_iohs[IDEDMA_CTL], 0); 400 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 401 IDEDMA_CTL_INTR) 402 continue; 403 wdc_cp = &cp->ata_channel; 404 crv = wdcintr(wdc_cp); 405 if (crv == 0) { 406 printf("%s:%d: bogus intr\n", 407 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 408 bus_space_write_1(sc->sc_dma_iot, 409 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 410 } else 411 rv = 1; 412 } 413 return rv; 414 } 415
Indexes created Sun Oct 19 21:10:07 GMT 2025