hptide.c revision 1.24
1 /* $NetBSD: hptide.c,v 1.24 2007/02/09 21:55:27 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hptide.c,v 1.24 2007/02/09 21:55:27 ad Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_hpt_reg.h> 43 44 static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*); 45 static void hpt_setup_channel(struct ata_channel*); 46 static int hpt_pci_intr(void *); 47 48 static int hptide_match(struct device *, struct cfdata *, void *); 49 static void hptide_attach(struct device *, struct device *, void *); 50 51 CFATTACH_DECL(hptide, sizeof(struct pciide_softc), 52 hptide_match, hptide_attach, NULL, NULL); 53 54 static const struct pciide_product_desc pciide_triones_products[] = { 55 { PCI_PRODUCT_TRIONES_HPT302, 56 0, 57 NULL, 58 hpt_chip_map 59 }, 60 { PCI_PRODUCT_TRIONES_HPT366, 61 0, 62 NULL, 63 hpt_chip_map, 64 }, 65 { PCI_PRODUCT_TRIONES_HPT371, 66 0, 67 NULL, 68 hpt_chip_map, 69 }, 70 { PCI_PRODUCT_TRIONES_HPT372A, 71 0, 72 NULL, 73 hpt_chip_map 74 }, 75 { PCI_PRODUCT_TRIONES_HPT374, 76 0, 77 NULL, 78 hpt_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static int 88 hptide_match(struct device *parent, struct cfdata *match, 89 void *aux) 90 { 91 struct pci_attach_args *pa = aux; 92 93 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) { 94 if (pciide_lookup_product(pa->pa_id, pciide_triones_products)) 95 return (2); 96 } 97 return (0); 98 } 99 100 static void 101 hptide_attach(struct device *parent, struct device *self, void *aux) 102 { 103 struct pci_attach_args *pa = aux; 104 struct pciide_softc *sc = (struct pciide_softc *)self; 105 106 pciide_common_attach(sc, pa, 107 pciide_lookup_product(pa->pa_id, pciide_triones_products)); 108 109 } 110 111 static void 112 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 113 { 114 struct pciide_channel *cp; 115 int i, compatchan, revision; 116 pcireg_t interface; 117 bus_size_t cmdsize, ctlsize; 118 119 if (pciide_chipen(sc, pa) == 0) 120 return; 121 122 revision = PCI_REVISION(pa->pa_class); 123 aprint_normal("%s: Triones/Highpoint ", 124 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 125 switch (sc->sc_pp->ide_product) { 126 case PCI_PRODUCT_TRIONES_HPT302: 127 aprint_normal("HPT302 IDE Controller\n"); 128 break; 129 case PCI_PRODUCT_TRIONES_HPT371: 130 aprint_normal("HPT371 IDE Controller\n"); 131 break; 132 case PCI_PRODUCT_TRIONES_HPT374: 133 aprint_normal("HPT374 IDE Controller\n"); 134 break; 135 case PCI_PRODUCT_TRIONES_HPT372A: 136 aprint_normal("HPT372A IDE Controller\n"); 137 break; 138 case PCI_PRODUCT_TRIONES_HPT366: 139 if (revision == HPT372_REV) 140 aprint_normal("HPT372 IDE Controller\n"); 141 else if (revision == HPT370_REV) 142 aprint_normal("HPT370 IDE Controller\n"); 143 else if (revision == HPT370A_REV) 144 aprint_normal("HPT370A IDE Controller\n"); 145 else if (revision == HPT368_REV) 146 aprint_normal("HPT368 IDE Controller\n"); 147 else if (revision == HPT366_REV) 148 aprint_normal("HPT366 IDE Controller\n"); 149 else 150 aprint_normal("unknown HPT IDE controller rev %d\n", 151 revision); 152 break; 153 default: 154 aprint_normal("unknown HPT IDE controller 0x%x\n", 155 sc->sc_pp->ide_product); 156 } 157 158 /* 159 * when the chip is in native mode it identifies itself as a 160 * 'misc mass storage'. Fake interface in this case. 161 */ 162 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 163 interface = PCI_INTERFACE(pa->pa_class); 164 } else { 165 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 166 PCIIDE_INTERFACE_PCI(0); 167 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 168 (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV || 169 revision == HPT372_REV)) || 170 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 171 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 172 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 173 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 174 interface |= PCIIDE_INTERFACE_PCI(1); 175 } 176 177 aprint_verbose("%s: bus-master DMA support present", 178 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 179 pciide_mapreg_dma(sc, pa); 180 aprint_verbose("\n"); 181 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 182 if (sc->sc_dma_ok) { 183 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 184 sc->sc_wdcdev.irqack = pciide_irqack; 185 } 186 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 187 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 188 189 sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel; 190 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 191 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 192 (revision == HPT366_REV || revision == HPT368_REV)) { 193 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 194 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 195 } else { 196 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 197 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 198 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 199 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 200 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 201 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 202 revision == HPT372_REV)) 203 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 204 else 205 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 206 } 207 208 wdc_allocate_regs(&sc->sc_wdcdev); 209 210 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 211 cp = &sc->pciide_channels[i]; 212 if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) { 213 compatchan = i; 214 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 215 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 216 aprint_normal( 217 "%s: %s channel ignored (disabled)\n", 218 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 219 cp->ata_channel.ch_flags |= ATACH_DISABLED; 220 continue; 221 } 222 } else { 223 /* 224 * The 366 has 2 PCI IDE functions, one for primary and 225 * one for secondary. So we need to call 226 * pciide_mapregs_compat() with the real channel. 227 */ 228 if (pa->pa_function == 0) 229 compatchan = 0; 230 else if (pa->pa_function == 1) 231 compatchan = 1; 232 else { 233 aprint_error("%s: unexpected PCI function %d\n", 234 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, pa->pa_function); 235 return; 236 } 237 } 238 if (pciide_chansetup(sc, i, interface) == 0) 239 continue; 240 if (interface & PCIIDE_INTERFACE_PCI(i)) { 241 pciide_mapregs_native(pa, cp, &cmdsize, 242 &ctlsize, hpt_pci_intr); 243 } else { 244 pciide_mapregs_compat(pa, cp, compatchan, 245 &cmdsize, &ctlsize); 246 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 247 pciide_map_compat_intr(pa, cp, 248 sc->sc_cy_compatchan); 249 } 250 wdcattach(&cp->ata_channel); 251 } 252 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 253 (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV || 254 revision == HPT372_REV)) || 255 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 256 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 257 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 258 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 259 /* 260 * HPT370_REV and highter has a bit to disable interrupts, 261 * make sure to clear it 262 */ 263 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 264 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 265 ~HPT_CSEL_IRQDIS); 266 } 267 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 268 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 269 revision == HPT372_REV ) || 270 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 271 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 272 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 273 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 274 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 275 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 276 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 277 return; 278 } 279 280 static void 281 hpt_setup_channel(struct ata_channel *chp) 282 { 283 struct ata_drive_datas *drvp; 284 int drive, s; 285 int cable; 286 u_int32_t before, after; 287 u_int32_t idedma_ctl; 288 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 289 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 290 int revision = 291 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 292 const u_int32_t *tim_pio, *tim_dma, *tim_udma; 293 294 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 295 296 /* setup DMA if needed */ 297 pciide_channel_dma_setup(cp); 298 299 idedma_ctl = 0; 300 301 /* select the timing arrays for the chip */ 302 switch (sc->sc_pp->ide_product) { 303 case PCI_PRODUCT_TRIONES_HPT374: 304 tim_udma = hpt374_udma; 305 tim_dma = hpt374_dma; 306 tim_pio = hpt374_pio; 307 break; 308 case PCI_PRODUCT_TRIONES_HPT302: 309 case PCI_PRODUCT_TRIONES_HPT371: 310 case PCI_PRODUCT_TRIONES_HPT372A: 311 tim_udma = hpt372_udma; 312 tim_dma = hpt372_dma; 313 tim_pio = hpt372_pio; 314 break; 315 case PCI_PRODUCT_TRIONES_HPT366: 316 default: 317 switch (revision) { 318 case HPT372_REV: 319 tim_udma = hpt372_udma; 320 tim_dma = hpt372_dma; 321 tim_pio = hpt372_pio; 322 break; 323 case HPT370_REV: 324 case HPT370A_REV: 325 tim_udma = hpt370_udma; 326 tim_dma = hpt370_dma; 327 tim_pio = hpt370_pio; 328 break; 329 case HPT368_REV: 330 case HPT366_REV: 331 default: 332 tim_udma = hpt366_udma; 333 tim_dma = hpt366_dma; 334 tim_pio = hpt366_pio; 335 break; 336 } 337 } 338 339 /* Per drive settings */ 340 for (drive = 0; drive < chp->ch_ndrive; drive++) { 341 drvp = &chp->ch_drive[drive]; 342 /* If no drive, skip */ 343 if ((drvp->drive_flags & DRIVE) == 0) 344 continue; 345 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 346 HPT_IDETIM(chp->ch_channel, drive)); 347 348 /* add timing values, setup DMA if needed */ 349 if (drvp->drive_flags & DRIVE_UDMA) { 350 /* use Ultra/DMA */ 351 s = splbio(); 352 drvp->drive_flags &= ~DRIVE_DMA; 353 splx(s); 354 if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 && 355 drvp->UDMA_mode > 2) 356 drvp->UDMA_mode = 2; 357 after = tim_udma[drvp->UDMA_mode]; 358 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 359 } else if (drvp->drive_flags & DRIVE_DMA) { 360 /* 361 * use Multiword DMA. 362 * Timings will be used for both PIO and DMA, so adjust 363 * DMA mode if needed 364 */ 365 if (drvp->PIO_mode >= 3 && 366 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 367 drvp->DMA_mode = drvp->PIO_mode - 2; 368 } 369 after = tim_dma[drvp->DMA_mode]; 370 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 371 } else { 372 /* PIO only */ 373 after = tim_pio[drvp->PIO_mode]; 374 } 375 pci_conf_write(sc->sc_pc, sc->sc_tag, 376 HPT_IDETIM(chp->ch_channel, drive), after); 377 ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x " 378 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 379 after, before), DEBUG_PROBE); 380 } 381 if (idedma_ctl != 0) { 382 /* Add software bits in status register */ 383 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 384 idedma_ctl); 385 } 386 } 387 388 static int 389 hpt_pci_intr(void *arg) 390 { 391 struct pciide_softc *sc = arg; 392 struct pciide_channel *cp; 393 struct ata_channel *wdc_cp; 394 int rv = 0; 395 int dmastat, i, crv; 396 397 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 398 cp = &sc->pciide_channels[i]; 399 dmastat = bus_space_read_1(sc->sc_dma_iot, 400 cp->dma_iohs[IDEDMA_CTL], 0); 401 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 402 IDEDMA_CTL_INTR) 403 continue; 404 wdc_cp = &cp->ata_channel; 405 crv = wdcintr(wdc_cp); 406 if (crv == 0) { 407 printf("%s:%d: bogus intr\n", 408 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 409 bus_space_write_1(sc->sc_dma_iot, 410 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 411 } else 412 rv = 1; 413 } 414 return rv; 415 } 416
Indexes created Wed Oct 15 16:09:53 GMT 2025