hptide.c revision 1.24.36.1
1 /* $NetBSD: hptide.c,v 1.24.36.1 2008/03/24 07:15:47 keiichi Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hptide.c,v 1.24.36.1 2008/03/24 07:15:47 keiichi Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_hpt_reg.h> 43 44 static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*); 45 static void hpt_setup_channel(struct ata_channel*); 46 static int hpt_pci_intr(void *); 47 48 static int hptide_match(device_t, cfdata_t, void *); 49 static void hptide_attach(device_t, device_t, void *); 50 51 CFATTACH_DECL_NEW(hptide, sizeof(struct pciide_softc), 52 hptide_match, hptide_attach, NULL, NULL); 53 54 static const struct pciide_product_desc pciide_triones_products[] = { 55 { PCI_PRODUCT_TRIONES_HPT302, 56 0, 57 NULL, 58 hpt_chip_map 59 }, 60 { PCI_PRODUCT_TRIONES_HPT366, 61 0, 62 NULL, 63 hpt_chip_map, 64 }, 65 { PCI_PRODUCT_TRIONES_HPT371, 66 0, 67 NULL, 68 hpt_chip_map, 69 }, 70 { PCI_PRODUCT_TRIONES_HPT372A, 71 0, 72 NULL, 73 hpt_chip_map 74 }, 75 { PCI_PRODUCT_TRIONES_HPT374, 76 0, 77 NULL, 78 hpt_chip_map 79 }, 80 { 0, 81 0, 82 NULL, 83 NULL 84 } 85 }; 86 87 static int 88 hptide_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) { 93 if (pciide_lookup_product(pa->pa_id, pciide_triones_products)) 94 return (2); 95 } 96 return (0); 97 } 98 99 static void 100 hptide_attach(device_t parent, device_t self, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 struct pciide_softc *sc = device_private(self); 104 105 sc->sc_wdcdev.sc_atac.atac_dev = self; 106 107 pciide_common_attach(sc, pa, 108 pciide_lookup_product(pa->pa_id, pciide_triones_products)); 109 110 } 111 112 static void 113 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 114 { 115 struct pciide_channel *cp; 116 int i, compatchan, revision; 117 pcireg_t interface; 118 bus_size_t cmdsize, ctlsize; 119 120 if (pciide_chipen(sc, pa) == 0) 121 return; 122 123 revision = PCI_REVISION(pa->pa_class); 124 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 125 "Triones/Highpoint "); 126 switch (sc->sc_pp->ide_product) { 127 case PCI_PRODUCT_TRIONES_HPT302: 128 aprint_normal("HPT302 IDE Controller\n"); 129 break; 130 case PCI_PRODUCT_TRIONES_HPT371: 131 aprint_normal("HPT371 IDE Controller\n"); 132 break; 133 case PCI_PRODUCT_TRIONES_HPT374: 134 aprint_normal("HPT374 IDE Controller\n"); 135 break; 136 case PCI_PRODUCT_TRIONES_HPT372A: 137 aprint_normal("HPT372A IDE Controller\n"); 138 break; 139 case PCI_PRODUCT_TRIONES_HPT366: 140 if (revision == HPT372_REV) 141 aprint_normal("HPT372 IDE Controller\n"); 142 else if (revision == HPT370_REV) 143 aprint_normal("HPT370 IDE Controller\n"); 144 else if (revision == HPT370A_REV) 145 aprint_normal("HPT370A IDE Controller\n"); 146 else if (revision == HPT368_REV) 147 aprint_normal("HPT368 IDE Controller\n"); 148 else if (revision == HPT366_REV) 149 aprint_normal("HPT366 IDE Controller\n"); 150 else 151 aprint_normal("unknown HPT IDE controller rev %d\n", 152 revision); 153 break; 154 default: 155 aprint_normal("unknown HPT IDE controller 0x%x\n", 156 sc->sc_pp->ide_product); 157 } 158 159 /* 160 * when the chip is in native mode it identifies itself as a 161 * 'misc mass storage'. Fake interface in this case. 162 */ 163 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 164 interface = PCI_INTERFACE(pa->pa_class); 165 } else { 166 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 167 PCIIDE_INTERFACE_PCI(0); 168 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 169 (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV || 170 revision == HPT372_REV)) || 171 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 172 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 173 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 174 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 175 interface |= PCIIDE_INTERFACE_PCI(1); 176 } 177 178 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 179 "bus-master DMA support present"); 180 pciide_mapreg_dma(sc, pa); 181 aprint_verbose("\n"); 182 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 183 if (sc->sc_dma_ok) { 184 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 185 sc->sc_wdcdev.irqack = pciide_irqack; 186 } 187 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 188 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 189 190 sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel; 191 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 192 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 193 (revision == HPT366_REV || revision == HPT368_REV)) { 194 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 195 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 196 } else { 197 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 198 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 199 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 200 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 201 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 202 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 203 revision == HPT372_REV)) 204 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 205 else 206 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 207 } 208 209 wdc_allocate_regs(&sc->sc_wdcdev); 210 211 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 212 cp = &sc->pciide_channels[i]; 213 if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) { 214 compatchan = i; 215 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 216 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 217 aprint_normal( 218 "%s: %s channel ignored (disabled)\n", 219 device_xname( 220 sc->sc_wdcdev.sc_atac.atac_dev), 221 cp->name); 222 cp->ata_channel.ch_flags |= ATACH_DISABLED; 223 continue; 224 } 225 } else { 226 /* 227 * The 366 has 2 PCI IDE functions, one for primary and 228 * one for secondary. So we need to call 229 * pciide_mapregs_compat() with the real channel. 230 */ 231 if (pa->pa_function == 0) 232 compatchan = 0; 233 else if (pa->pa_function == 1) 234 compatchan = 1; 235 else { 236 aprint_error_dev( 237 sc->sc_wdcdev.sc_atac.atac_dev, 238 "unexpected PCI function %d\n", 239 pa->pa_function); 240 return; 241 } 242 } 243 if (pciide_chansetup(sc, i, interface) == 0) 244 continue; 245 if (interface & PCIIDE_INTERFACE_PCI(i)) { 246 pciide_mapregs_native(pa, cp, &cmdsize, 247 &ctlsize, hpt_pci_intr); 248 } else { 249 pciide_mapregs_compat(pa, cp, compatchan, 250 &cmdsize, &ctlsize); 251 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 252 pciide_map_compat_intr(pa, cp, 253 sc->sc_cy_compatchan); 254 } 255 wdcattach(&cp->ata_channel); 256 } 257 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 258 (revision == HPT368_REV || revision == HPT370_REV || revision == HPT370A_REV || 259 revision == HPT372_REV)) || 260 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 261 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 262 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 263 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 264 /* 265 * HPT370_REV and highter has a bit to disable interrupts, 266 * make sure to clear it 267 */ 268 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 269 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 270 ~HPT_CSEL_IRQDIS); 271 } 272 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 273 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 274 revision == HPT372_REV ) || 275 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 || 276 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 || 277 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A || 278 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 279 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 280 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 281 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 282 return; 283 } 284 285 static void 286 hpt_setup_channel(struct ata_channel *chp) 287 { 288 struct ata_drive_datas *drvp; 289 int drive, s; 290 int cable; 291 u_int32_t before, after; 292 u_int32_t idedma_ctl; 293 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 294 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 295 int revision = 296 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 297 const u_int32_t *tim_pio, *tim_dma, *tim_udma; 298 299 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 300 301 /* setup DMA if needed */ 302 pciide_channel_dma_setup(cp); 303 304 idedma_ctl = 0; 305 306 /* select the timing arrays for the chip */ 307 switch (sc->sc_pp->ide_product) { 308 case PCI_PRODUCT_TRIONES_HPT374: 309 tim_udma = hpt374_udma; 310 tim_dma = hpt374_dma; 311 tim_pio = hpt374_pio; 312 break; 313 case PCI_PRODUCT_TRIONES_HPT302: 314 case PCI_PRODUCT_TRIONES_HPT371: 315 case PCI_PRODUCT_TRIONES_HPT372A: 316 tim_udma = hpt372_udma; 317 tim_dma = hpt372_dma; 318 tim_pio = hpt372_pio; 319 break; 320 case PCI_PRODUCT_TRIONES_HPT366: 321 default: 322 switch (revision) { 323 case HPT372_REV: 324 tim_udma = hpt372_udma; 325 tim_dma = hpt372_dma; 326 tim_pio = hpt372_pio; 327 break; 328 case HPT370_REV: 329 case HPT370A_REV: 330 tim_udma = hpt370_udma; 331 tim_dma = hpt370_dma; 332 tim_pio = hpt370_pio; 333 break; 334 case HPT368_REV: 335 case HPT366_REV: 336 default: 337 tim_udma = hpt366_udma; 338 tim_dma = hpt366_dma; 339 tim_pio = hpt366_pio; 340 break; 341 } 342 } 343 344 /* Per drive settings */ 345 for (drive = 0; drive < chp->ch_ndrive; drive++) { 346 drvp = &chp->ch_drive[drive]; 347 /* If no drive, skip */ 348 if ((drvp->drive_flags & DRIVE) == 0) 349 continue; 350 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 351 HPT_IDETIM(chp->ch_channel, drive)); 352 353 /* add timing values, setup DMA if needed */ 354 if (drvp->drive_flags & DRIVE_UDMA) { 355 /* use Ultra/DMA */ 356 s = splbio(); 357 drvp->drive_flags &= ~DRIVE_DMA; 358 splx(s); 359 if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 && 360 drvp->UDMA_mode > 2) 361 drvp->UDMA_mode = 2; 362 after = tim_udma[drvp->UDMA_mode]; 363 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 364 } else if (drvp->drive_flags & DRIVE_DMA) { 365 /* 366 * use Multiword DMA. 367 * Timings will be used for both PIO and DMA, so adjust 368 * DMA mode if needed 369 */ 370 if (drvp->PIO_mode >= 3 && 371 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 372 drvp->DMA_mode = drvp->PIO_mode - 2; 373 } 374 after = tim_dma[drvp->DMA_mode]; 375 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 376 } else { 377 /* PIO only */ 378 after = tim_pio[drvp->PIO_mode]; 379 } 380 pci_conf_write(sc->sc_pc, sc->sc_tag, 381 HPT_IDETIM(chp->ch_channel, drive), after); 382 ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x " 383 "(BIOS 0x%08x)\n", device_xname(drvp->drv_softc), 384 after, before), DEBUG_PROBE); 385 } 386 if (idedma_ctl != 0) { 387 /* Add software bits in status register */ 388 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 389 idedma_ctl); 390 } 391 } 392 393 static int 394 hpt_pci_intr(void *arg) 395 { 396 struct pciide_softc *sc = arg; 397 struct pciide_channel *cp; 398 struct ata_channel *wdc_cp; 399 int rv = 0; 400 int dmastat, i, crv; 401 402 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 403 cp = &sc->pciide_channels[i]; 404 dmastat = bus_space_read_1(sc->sc_dma_iot, 405 cp->dma_iohs[IDEDMA_CTL], 0); 406 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 407 IDEDMA_CTL_INTR) 408 continue; 409 wdc_cp = &cp->ata_channel; 410 crv = wdcintr(wdc_cp); 411 if (crv == 0) { 412 aprint_error("%s:%d: bogus intr\n", 413 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i); 414 bus_space_write_1(sc->sc_dma_iot, 415 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 416 } else 417 rv = 1; 418 } 419 return rv; 420 } 421
Indexes created Thu Oct 16 14:10:15 GMT 2025