hptide.c revision 1.4
1 /* $NetBSD: hptide.c,v 1.4 2003/10/25 18:31:11 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_hpt_reg.h> 40 41 static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*); 42 static void hpt_setup_channel(struct channel_softc*); 43 static int hpt_pci_intr(void *); 44 45 static int hptide_match(struct device *, struct cfdata *, void *); 46 static void hptide_attach(struct device *, struct device *, void *); 47 48 CFATTACH_DECL(hptide, sizeof(struct pciide_softc), 49 hptide_match, hptide_attach, NULL, NULL); 50 51 static const struct pciide_product_desc pciide_triones_products[] = { 52 { PCI_PRODUCT_TRIONES_HPT366, 53 0, 54 NULL, 55 hpt_chip_map, 56 }, 57 { PCI_PRODUCT_TRIONES_HPT372, 58 0, 59 NULL, 60 hpt_chip_map 61 }, 62 { PCI_PRODUCT_TRIONES_HPT374, 63 0, 64 NULL, 65 hpt_chip_map 66 }, 67 { 0, 68 0, 69 NULL, 70 NULL 71 } 72 }; 73 74 static int 75 hptide_match(struct device *parent, struct cfdata *match, void *aux) 76 { 77 struct pci_attach_args *pa = aux; 78 79 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) { 80 if (pciide_lookup_product(pa->pa_id, pciide_triones_products)) 81 return (2); 82 } 83 return (0); 84 } 85 86 static void 87 hptide_attach(struct device *parent, struct device *self, void *aux) 88 { 89 struct pci_attach_args *pa = aux; 90 struct pciide_softc *sc = (struct pciide_softc *)self; 91 92 pciide_common_attach(sc, pa, 93 pciide_lookup_product(pa->pa_id, pciide_triones_products)); 94 95 } 96 97 static void 98 hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 99 { 100 struct pciide_channel *cp; 101 int i, compatchan = -1, revision; /* XXX: gcc */ 102 pcireg_t interface; 103 bus_size_t cmdsize, ctlsize; 104 105 if (pciide_chipen(sc, pa) == 0) 106 return; 107 108 revision = PCI_REVISION(pa->pa_class); 109 aprint_normal("%s: Triones/Highpoint ", 110 sc->sc_wdcdev.sc_dev.dv_xname); 111 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 112 aprint_normal("HPT374 IDE Controller\n"); 113 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 114 aprint_normal("HPT372 IDE Controller\n"); 115 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 116 if (revision == HPT372_REV) 117 aprint_normal("HPT372 IDE Controller\n"); 118 else if (revision == HPT370_REV) 119 aprint_normal("HPT370 IDE Controller\n"); 120 else if (revision == HPT370A_REV) 121 aprint_normal("HPT370A IDE Controller\n"); 122 else if (revision == HPT366_REV) 123 aprint_normal("HPT366 IDE Controller\n"); 124 else 125 aprint_normal("unknown HPT IDE controller rev %d\n", 126 revision); 127 } else 128 aprint_normal("unknown HPT IDE controller 0x%x\n", 129 sc->sc_pp->ide_product); 130 131 /* 132 * when the chip is in native mode it identifies itself as a 133 * 'misc mass storage'. Fake interface in this case. 134 */ 135 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 136 interface = PCI_INTERFACE(pa->pa_class); 137 } else { 138 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 139 PCIIDE_INTERFACE_PCI(0); 140 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 141 (revision == HPT370_REV || revision == HPT370A_REV || 142 revision == HPT372_REV)) || 143 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 144 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 145 interface |= PCIIDE_INTERFACE_PCI(1); 146 } 147 148 aprint_normal("%s: bus-master DMA support present", 149 sc->sc_wdcdev.sc_dev.dv_xname); 150 pciide_mapreg_dma(sc, pa); 151 aprint_normal("\n"); 152 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 153 WDC_CAPABILITY_MODE; 154 if (sc->sc_dma_ok) { 155 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 156 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 157 sc->sc_wdcdev.irqack = pciide_irqack; 158 } 159 sc->sc_wdcdev.PIO_cap = 4; 160 sc->sc_wdcdev.DMA_cap = 2; 161 162 sc->sc_wdcdev.set_modes = hpt_setup_channel; 163 sc->sc_wdcdev.channels = sc->wdc_chanarray; 164 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 165 revision == HPT366_REV) { 166 sc->sc_wdcdev.UDMA_cap = 4; 167 /* 168 * The 366 has 2 PCI IDE functions, one for primary and one 169 * for secondary. So we need to call pciide_mapregs_compat() 170 * with the real channel 171 */ 172 if (pa->pa_function == 0) { 173 compatchan = 0; 174 } else if (pa->pa_function == 1) { 175 compatchan = 1; 176 } else { 177 aprint_error("%s: unexpected PCI function %d\n", 178 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 179 return; 180 } 181 sc->sc_wdcdev.nchannels = 1; 182 } else { 183 sc->sc_wdcdev.nchannels = 2; 184 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 185 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 186 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 187 revision == HPT372_REV)) 188 sc->sc_wdcdev.UDMA_cap = 6; 189 else 190 sc->sc_wdcdev.UDMA_cap = 5; 191 } 192 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 193 cp = &sc->pciide_channels[i]; 194 if (sc->sc_wdcdev.nchannels > 1) { 195 compatchan = i; 196 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 197 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 198 aprint_normal( 199 "%s: %s channel ignored (disabled)\n", 200 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 201 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 202 continue; 203 } 204 } 205 if (pciide_chansetup(sc, i, interface) == 0) 206 continue; 207 if (interface & PCIIDE_INTERFACE_PCI(i)) { 208 pciide_mapregs_native(pa, cp, &cmdsize, 209 &ctlsize, hpt_pci_intr); 210 } else { 211 pciide_mapregs_compat(pa, cp, compatchan, 212 &cmdsize, &ctlsize); 213 } 214 wdcattach(&cp->wdc_channel); 215 } 216 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 217 (revision == HPT370_REV || revision == HPT370A_REV || 218 revision == HPT372_REV)) || 219 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 220 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 221 /* 222 * HPT370_REV and highter has a bit to disable interrupts, 223 * make sure to clear it 224 */ 225 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 226 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 227 ~HPT_CSEL_IRQDIS); 228 } 229 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 230 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 231 revision == HPT372_REV ) || 232 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 233 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 234 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 235 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 236 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 237 return; 238 } 239 240 static void 241 hpt_setup_channel(struct channel_softc *chp) 242 { 243 struct ata_drive_datas *drvp; 244 int drive; 245 int cable; 246 u_int32_t before, after; 247 u_int32_t idedma_ctl; 248 struct pciide_channel *cp = (struct pciide_channel*)chp; 249 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 250 int revision = 251 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 252 253 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 254 255 /* setup DMA if needed */ 256 pciide_channel_dma_setup(cp); 257 258 idedma_ctl = 0; 259 260 /* Per drive settings */ 261 for (drive = 0; drive < 2; drive++) { 262 drvp = &chp->ch_drive[drive]; 263 /* If no drive, skip */ 264 if ((drvp->drive_flags & DRIVE) == 0) 265 continue; 266 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 267 HPT_IDETIM(chp->channel, drive)); 268 269 /* add timing values, setup DMA if needed */ 270 if (drvp->drive_flags & DRIVE_UDMA) { 271 /* use Ultra/DMA */ 272 drvp->drive_flags &= ~DRIVE_DMA; 273 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 274 drvp->UDMA_mode > 2) 275 drvp->UDMA_mode = 2; 276 switch (sc->sc_pp->ide_product) { 277 case PCI_PRODUCT_TRIONES_HPT374: 278 after = hpt374_udma[drvp->UDMA_mode]; 279 break; 280 case PCI_PRODUCT_TRIONES_HPT372: 281 after = hpt372_udma[drvp->UDMA_mode]; 282 break; 283 case PCI_PRODUCT_TRIONES_HPT366: 284 default: 285 switch(revision) { 286 case HPT372_REV: 287 after = hpt372_udma[drvp->UDMA_mode]; 288 break; 289 case HPT370_REV: 290 case HPT370A_REV: 291 after = hpt370_udma[drvp->UDMA_mode]; 292 break; 293 case HPT366_REV: 294 default: 295 after = hpt366_udma[drvp->UDMA_mode]; 296 break; 297 } 298 } 299 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 300 } else if (drvp->drive_flags & DRIVE_DMA) { 301 /* 302 * use Multiword DMA. 303 * Timings will be used for both PIO and DMA, so adjust 304 * DMA mode if needed 305 */ 306 if (drvp->PIO_mode >= 3 && 307 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 308 drvp->DMA_mode = drvp->PIO_mode - 2; 309 } 310 switch (sc->sc_pp->ide_product) { 311 case PCI_PRODUCT_TRIONES_HPT374: 312 after = hpt374_dma[drvp->DMA_mode]; 313 break; 314 case PCI_PRODUCT_TRIONES_HPT372: 315 after = hpt372_dma[drvp->DMA_mode]; 316 break; 317 case PCI_PRODUCT_TRIONES_HPT366: 318 default: 319 switch(revision) { 320 case HPT372_REV: 321 after = hpt372_dma[drvp->DMA_mode]; 322 break; 323 case HPT370_REV: 324 case HPT370A_REV: 325 after = hpt370_dma[drvp->DMA_mode]; 326 break; 327 case HPT366_REV: 328 default: 329 after = hpt366_dma[drvp->DMA_mode]; 330 break; 331 } 332 } 333 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 334 } else { 335 /* PIO only */ 336 switch (sc->sc_pp->ide_product) { 337 case PCI_PRODUCT_TRIONES_HPT374: 338 after = hpt374_pio[drvp->PIO_mode]; 339 break; 340 case PCI_PRODUCT_TRIONES_HPT372: 341 after = hpt372_pio[drvp->PIO_mode]; 342 break; 343 case PCI_PRODUCT_TRIONES_HPT366: 344 default: 345 switch(revision) { 346 case HPT372_REV: 347 after = hpt372_pio[drvp->PIO_mode]; 348 break; 349 case HPT370_REV: 350 case HPT370A_REV: 351 after = hpt370_pio[drvp->PIO_mode]; 352 break; 353 case HPT366_REV: 354 default: 355 after = hpt366_pio[drvp->PIO_mode]; 356 break; 357 } 358 } 359 } 360 pci_conf_write(sc->sc_pc, sc->sc_tag, 361 HPT_IDETIM(chp->channel, drive), after); 362 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 363 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 364 after, before), DEBUG_PROBE); 365 } 366 if (idedma_ctl != 0) { 367 /* Add software bits in status register */ 368 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 369 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 370 idedma_ctl); 371 } 372 } 373 374 static int 375 hpt_pci_intr(void *arg) 376 { 377 struct pciide_softc *sc = arg; 378 struct pciide_channel *cp; 379 struct channel_softc *wdc_cp; 380 int rv = 0; 381 int dmastat, i, crv; 382 383 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 384 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 385 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 386 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 387 IDEDMA_CTL_INTR) 388 continue; 389 cp = &sc->pciide_channels[i]; 390 wdc_cp = &cp->wdc_channel; 391 crv = wdcintr(wdc_cp); 392 if (crv == 0) { 393 printf("%s:%d: bogus intr\n", 394 sc->sc_wdcdev.sc_dev.dv_xname, i); 395 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 396 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 397 } else 398 rv = 1; 399 } 400 return rv; 401 } 402
Indexes created Thu Oct 23 22:10:10 GMT 2025