ichsmb.c revision 1.22.4.2 1 1.22.4.1 rmind /* $NetBSD: ichsmb.c,v 1.22.4.2 2011/05/31 03:04:39 rmind Exp $ */
2 1.1 kiyohara /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */
3 1.1 kiyohara
4 1.1 kiyohara /*
5 1.1 kiyohara * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org>
6 1.1 kiyohara *
7 1.1 kiyohara * Permission to use, copy, modify, and distribute this software for any
8 1.1 kiyohara * purpose with or without fee is hereby granted, provided that the above
9 1.1 kiyohara * copyright notice and this permission notice appear in all copies.
10 1.1 kiyohara *
11 1.1 kiyohara * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 1.1 kiyohara * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 1.1 kiyohara * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 1.1 kiyohara * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 1.1 kiyohara * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 1.1 kiyohara * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 1.1 kiyohara * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 1.1 kiyohara */
19 1.1 kiyohara
20 1.1 kiyohara /*
21 1.1 kiyohara * Intel ICH SMBus controller driver.
22 1.1 kiyohara */
23 1.1 kiyohara
24 1.6 xtraeme #include <sys/cdefs.h>
25 1.22.4.1 rmind __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.22.4.2 2011/05/31 03:04:39 rmind Exp $");
26 1.6 xtraeme
27 1.1 kiyohara #include <sys/param.h>
28 1.1 kiyohara #include <sys/device.h>
29 1.1 kiyohara #include <sys/errno.h>
30 1.1 kiyohara #include <sys/kernel.h>
31 1.8 xtraeme #include <sys/rwlock.h>
32 1.1 kiyohara #include <sys/proc.h>
33 1.1 kiyohara
34 1.10 ad #include <sys/bus.h>
35 1.1 kiyohara
36 1.1 kiyohara #include <dev/pci/pcidevs.h>
37 1.1 kiyohara #include <dev/pci/pcireg.h>
38 1.1 kiyohara #include <dev/pci/pcivar.h>
39 1.1 kiyohara
40 1.5 xtraeme #include <dev/ic/i82801lpcreg.h>
41 1.1 kiyohara
42 1.1 kiyohara #include <dev/i2c/i2cvar.h>
43 1.1 kiyohara
44 1.1 kiyohara #ifdef ICHIIC_DEBUG
45 1.1 kiyohara #define DPRINTF(x) printf x
46 1.1 kiyohara #else
47 1.1 kiyohara #define DPRINTF(x)
48 1.1 kiyohara #endif
49 1.1 kiyohara
50 1.1 kiyohara #define ICHIIC_DELAY 100
51 1.1 kiyohara #define ICHIIC_TIMEOUT 1
52 1.1 kiyohara
53 1.1 kiyohara struct ichsmb_softc {
54 1.12 kiyohara device_t sc_dev;
55 1.1 kiyohara
56 1.1 kiyohara bus_space_tag_t sc_iot;
57 1.1 kiyohara bus_space_handle_t sc_ioh;
58 1.1 kiyohara void * sc_ih;
59 1.1 kiyohara int sc_poll;
60 1.1 kiyohara
61 1.1 kiyohara struct i2c_controller sc_i2c_tag;
62 1.8 xtraeme krwlock_t sc_i2c_rwlock;
63 1.1 kiyohara struct {
64 1.1 kiyohara i2c_op_t op;
65 1.1 kiyohara void * buf;
66 1.1 kiyohara size_t len;
67 1.1 kiyohara int flags;
68 1.1 kiyohara volatile int error;
69 1.1 kiyohara } sc_i2c_xfer;
70 1.1 kiyohara };
71 1.1 kiyohara
72 1.21 cegger static int ichsmb_match(device_t, cfdata_t, void *);
73 1.12 kiyohara static void ichsmb_attach(device_t, device_t, void *);
74 1.1 kiyohara
75 1.1 kiyohara static int ichsmb_i2c_acquire_bus(void *, int);
76 1.1 kiyohara static void ichsmb_i2c_release_bus(void *, int);
77 1.1 kiyohara static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *,
78 1.1 kiyohara size_t, void *, size_t, int);
79 1.1 kiyohara
80 1.1 kiyohara static int ichsmb_intr(void *);
81 1.1 kiyohara
82 1.1 kiyohara
83 1.12 kiyohara CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc),
84 1.1 kiyohara ichsmb_match, ichsmb_attach, NULL, NULL);
85 1.1 kiyohara
86 1.1 kiyohara
87 1.1 kiyohara static int
88 1.21 cegger ichsmb_match(device_t parent, cfdata_t match, void *aux)
89 1.1 kiyohara {
90 1.1 kiyohara struct pci_attach_args *pa = aux;
91 1.1 kiyohara
92 1.1 kiyohara if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
93 1.1 kiyohara switch (PCI_PRODUCT(pa->pa_id)) {
94 1.1 kiyohara case PCI_PRODUCT_INTEL_6300ESB_SMB:
95 1.1 kiyohara case PCI_PRODUCT_INTEL_63XXESB_SMB:
96 1.1 kiyohara case PCI_PRODUCT_INTEL_82801AA_SMB:
97 1.1 kiyohara case PCI_PRODUCT_INTEL_82801AB_SMB:
98 1.1 kiyohara case PCI_PRODUCT_INTEL_82801BA_SMB:
99 1.1 kiyohara case PCI_PRODUCT_INTEL_82801CA_SMB:
100 1.1 kiyohara case PCI_PRODUCT_INTEL_82801DB_SMB:
101 1.1 kiyohara case PCI_PRODUCT_INTEL_82801E_SMB:
102 1.1 kiyohara case PCI_PRODUCT_INTEL_82801EB_SMB:
103 1.1 kiyohara case PCI_PRODUCT_INTEL_82801FB_SMB:
104 1.1 kiyohara case PCI_PRODUCT_INTEL_82801G_SMB:
105 1.1 kiyohara case PCI_PRODUCT_INTEL_82801H_SMB:
106 1.7 xtraeme case PCI_PRODUCT_INTEL_82801I_SMB:
107 1.22.4.1 rmind case PCI_PRODUCT_INTEL_82801JD_SMB:
108 1.22.4.1 rmind case PCI_PRODUCT_INTEL_82801JI_SMB:
109 1.22 tnn case PCI_PRODUCT_INTEL_3400_SMB:
110 1.22.4.2 rmind case PCI_PRODUCT_INTEL_6SERIES_SMB:
111 1.1 kiyohara return 1;
112 1.1 kiyohara }
113 1.1 kiyohara }
114 1.1 kiyohara return 0;
115 1.1 kiyohara }
116 1.1 kiyohara
117 1.1 kiyohara static void
118 1.12 kiyohara ichsmb_attach(device_t parent, device_t self, void *aux)
119 1.1 kiyohara {
120 1.12 kiyohara struct ichsmb_softc *sc = device_private(self);
121 1.1 kiyohara struct pci_attach_args *pa = aux;
122 1.1 kiyohara struct i2cbus_attach_args iba;
123 1.1 kiyohara pcireg_t conf;
124 1.1 kiyohara bus_size_t iosize;
125 1.1 kiyohara pci_intr_handle_t ih;
126 1.1 kiyohara const char *intrstr = NULL;
127 1.1 kiyohara char devinfo[256];
128 1.1 kiyohara
129 1.12 kiyohara sc->sc_dev = self;
130 1.12 kiyohara
131 1.1 kiyohara aprint_naive("\n");
132 1.1 kiyohara pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
133 1.1 kiyohara aprint_normal(": %s (rev. 0x%02x)\n", devinfo,
134 1.1 kiyohara PCI_REVISION(pa->pa_class));
135 1.1 kiyohara
136 1.1 kiyohara /* Read configuration */
137 1.5 xtraeme conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC);
138 1.16 njoly DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf));
139 1.1 kiyohara
140 1.5 xtraeme if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) {
141 1.12 kiyohara aprint_error_dev(self, "SMBus disabled\n");
142 1.1 kiyohara return;
143 1.1 kiyohara }
144 1.1 kiyohara
145 1.1 kiyohara /* Map I/O space */
146 1.5 xtraeme if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0,
147 1.1 kiyohara &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) {
148 1.12 kiyohara aprint_error_dev(self, "can't map I/O space\n");
149 1.1 kiyohara return;
150 1.1 kiyohara }
151 1.1 kiyohara
152 1.1 kiyohara sc->sc_poll = 1;
153 1.5 xtraeme if (conf & LPCIB_SMB_HOSTC_SMIEN) {
154 1.1 kiyohara /* No PCI IRQ */
155 1.15 njoly aprint_normal_dev(self, "interrupting at SMI\n");
156 1.1 kiyohara } else {
157 1.1 kiyohara /* Install interrupt handler */
158 1.1 kiyohara if (pci_intr_map(pa, &ih) == 0) {
159 1.1 kiyohara intrstr = pci_intr_string(pa->pa_pc, ih);
160 1.1 kiyohara sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
161 1.1 kiyohara ichsmb_intr, sc);
162 1.1 kiyohara if (sc->sc_ih != NULL) {
163 1.12 kiyohara aprint_normal_dev(self, "interrupting at %s\n",
164 1.12 kiyohara intrstr);
165 1.1 kiyohara sc->sc_poll = 0;
166 1.1 kiyohara }
167 1.1 kiyohara }
168 1.1 kiyohara if (sc->sc_poll)
169 1.12 kiyohara aprint_normal_dev(self, "polling\n");
170 1.1 kiyohara }
171 1.1 kiyohara
172 1.1 kiyohara /* Attach I2C bus */
173 1.8 xtraeme rw_init(&sc->sc_i2c_rwlock);
174 1.1 kiyohara sc->sc_i2c_tag.ic_cookie = sc;
175 1.1 kiyohara sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus;
176 1.1 kiyohara sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus;
177 1.1 kiyohara sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec;
178 1.1 kiyohara
179 1.20 cegger memset(&iba, 0, sizeof(iba));
180 1.9 riz iba.iba_type = I2C_TYPE_SMBUS;
181 1.1 kiyohara iba.iba_tag = &sc->sc_i2c_tag;
182 1.1 kiyohara config_found(self, &iba, iicbus_print);
183 1.1 kiyohara
184 1.11 jmcneill if (!pmf_device_register(self, NULL, NULL))
185 1.11 jmcneill aprint_error_dev(self, "couldn't establish power handler\n");
186 1.1 kiyohara }
187 1.1 kiyohara
188 1.1 kiyohara static int
189 1.1 kiyohara ichsmb_i2c_acquire_bus(void *cookie, int flags)
190 1.1 kiyohara {
191 1.1 kiyohara struct ichsmb_softc *sc = cookie;
192 1.1 kiyohara
193 1.1 kiyohara if (cold || sc->sc_poll || (flags & I2C_F_POLL))
194 1.8 xtraeme return 0;
195 1.1 kiyohara
196 1.8 xtraeme rw_enter(&sc->sc_i2c_rwlock, RW_WRITER);
197 1.8 xtraeme return 0;
198 1.1 kiyohara }
199 1.1 kiyohara
200 1.1 kiyohara static void
201 1.1 kiyohara ichsmb_i2c_release_bus(void *cookie, int flags)
202 1.1 kiyohara {
203 1.1 kiyohara struct ichsmb_softc *sc = cookie;
204 1.1 kiyohara
205 1.1 kiyohara if (cold || sc->sc_poll || (flags & I2C_F_POLL))
206 1.1 kiyohara return;
207 1.1 kiyohara
208 1.8 xtraeme rw_exit(&sc->sc_i2c_rwlock);
209 1.1 kiyohara }
210 1.1 kiyohara
211 1.1 kiyohara static int
212 1.1 kiyohara ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
213 1.1 kiyohara const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
214 1.1 kiyohara {
215 1.1 kiyohara struct ichsmb_softc *sc = cookie;
216 1.1 kiyohara const uint8_t *b;
217 1.1 kiyohara uint8_t ctl = 0, st;
218 1.1 kiyohara int retries;
219 1.4 kiyohara char fbuf[64];
220 1.1 kiyohara
221 1.14 njoly DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, "
222 1.14 njoly "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen,
223 1.1 kiyohara len, flags));
224 1.1 kiyohara
225 1.1 kiyohara /* Wait for bus to be idle */
226 1.1 kiyohara for (retries = 100; retries > 0; retries--) {
227 1.5 xtraeme st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS);
228 1.5 xtraeme if (!(st & LPCIB_SMB_HS_BUSY))
229 1.1 kiyohara break;
230 1.1 kiyohara DELAY(ICHIIC_DELAY);
231 1.1 kiyohara }
232 1.4 kiyohara #ifdef ICHIIC_DEBUG
233 1.18 christos snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st);
234 1.14 njoly printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf);
235 1.4 kiyohara #endif
236 1.5 xtraeme if (st & LPCIB_SMB_HS_BUSY)
237 1.1 kiyohara return (1);
238 1.1 kiyohara
239 1.1 kiyohara if (cold || sc->sc_poll)
240 1.1 kiyohara flags |= I2C_F_POLL;
241 1.1 kiyohara
242 1.22.4.1 rmind if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 ||
243 1.22.4.1 rmind (cmdlen == 0 && len > 1))
244 1.1 kiyohara return (1);
245 1.1 kiyohara
246 1.1 kiyohara /* Setup transfer */
247 1.1 kiyohara sc->sc_i2c_xfer.op = op;
248 1.1 kiyohara sc->sc_i2c_xfer.buf = buf;
249 1.1 kiyohara sc->sc_i2c_xfer.len = len;
250 1.1 kiyohara sc->sc_i2c_xfer.flags = flags;
251 1.1 kiyohara sc->sc_i2c_xfer.error = 0;
252 1.1 kiyohara
253 1.1 kiyohara /* Set slave address and transfer direction */
254 1.5 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA,
255 1.5 xtraeme LPCIB_SMB_TXSLVA_ADDR(addr) |
256 1.5 xtraeme (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0));
257 1.1 kiyohara
258 1.1 kiyohara b = (const uint8_t *)cmdbuf;
259 1.1 kiyohara if (cmdlen > 0)
260 1.1 kiyohara /* Set command byte */
261 1.5 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]);
262 1.1 kiyohara
263 1.1 kiyohara if (I2C_OP_WRITE_P(op)) {
264 1.1 kiyohara /* Write data */
265 1.1 kiyohara b = buf;
266 1.22.4.1 rmind if (cmdlen == 0 && len == 1)
267 1.22.4.1 rmind bus_space_write_1(sc->sc_iot, sc->sc_ioh,
268 1.22.4.1 rmind LPCIB_SMB_HCMD, b[0]);
269 1.22.4.1 rmind else if (len > 0)
270 1.1 kiyohara bus_space_write_1(sc->sc_iot, sc->sc_ioh,
271 1.5 xtraeme LPCIB_SMB_HD0, b[0]);
272 1.1 kiyohara if (len > 1)
273 1.1 kiyohara bus_space_write_1(sc->sc_iot, sc->sc_ioh,
274 1.5 xtraeme LPCIB_SMB_HD1, b[1]);
275 1.1 kiyohara }
276 1.1 kiyohara
277 1.1 kiyohara /* Set SMBus command */
278 1.22.4.1 rmind if (cmdlen == 0) {
279 1.22.4.1 rmind if (len == 0)
280 1.19 pgoyette ctl = LPCIB_SMB_HC_CMD_QUICK;
281 1.19 pgoyette else
282 1.19 pgoyette ctl = LPCIB_SMB_HC_CMD_BYTE;
283 1.19 pgoyette } else if (len == 1)
284 1.5 xtraeme ctl = LPCIB_SMB_HC_CMD_BDATA;
285 1.1 kiyohara else if (len == 2)
286 1.5 xtraeme ctl = LPCIB_SMB_HC_CMD_WDATA;
287 1.1 kiyohara
288 1.1 kiyohara if ((flags & I2C_F_POLL) == 0)
289 1.5 xtraeme ctl |= LPCIB_SMB_HC_INTREN;
290 1.1 kiyohara
291 1.1 kiyohara /* Start transaction */
292 1.5 xtraeme ctl |= LPCIB_SMB_HC_START;
293 1.5 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl);
294 1.1 kiyohara
295 1.1 kiyohara if (flags & I2C_F_POLL) {
296 1.1 kiyohara /* Poll for completion */
297 1.1 kiyohara DELAY(ICHIIC_DELAY);
298 1.1 kiyohara for (retries = 1000; retries > 0; retries--) {
299 1.1 kiyohara st = bus_space_read_1(sc->sc_iot, sc->sc_ioh,
300 1.5 xtraeme LPCIB_SMB_HS);
301 1.5 xtraeme if ((st & LPCIB_SMB_HS_BUSY) == 0)
302 1.1 kiyohara break;
303 1.1 kiyohara DELAY(ICHIIC_DELAY);
304 1.1 kiyohara }
305 1.5 xtraeme if (st & LPCIB_SMB_HS_BUSY)
306 1.1 kiyohara goto timeout;
307 1.1 kiyohara ichsmb_intr(sc);
308 1.1 kiyohara } else {
309 1.1 kiyohara /* Wait for interrupt */
310 1.1 kiyohara if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz))
311 1.1 kiyohara goto timeout;
312 1.1 kiyohara }
313 1.1 kiyohara
314 1.1 kiyohara if (sc->sc_i2c_xfer.error)
315 1.1 kiyohara return (1);
316 1.1 kiyohara
317 1.1 kiyohara return (0);
318 1.1 kiyohara
319 1.1 kiyohara timeout:
320 1.1 kiyohara /*
321 1.1 kiyohara * Transfer timeout. Kill the transaction and clear status bits.
322 1.1 kiyohara */
323 1.18 christos snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st);
324 1.12 kiyohara aprint_error_dev(sc->sc_dev,
325 1.12 kiyohara "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, "
326 1.4 kiyohara "flags 0x%02x: timeout, status 0x%s\n",
327 1.12 kiyohara op, addr, cmdlen, len, flags, fbuf);
328 1.5 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC,
329 1.5 xtraeme LPCIB_SMB_HC_KILL);
330 1.1 kiyohara DELAY(ICHIIC_DELAY);
331 1.5 xtraeme st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS);
332 1.5 xtraeme if ((st & LPCIB_SMB_HS_FAILED) == 0) {
333 1.18 christos snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st);
334 1.12 kiyohara aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n",
335 1.12 kiyohara fbuf);
336 1.4 kiyohara }
337 1.5 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st);
338 1.1 kiyohara return (1);
339 1.1 kiyohara }
340 1.1 kiyohara
341 1.1 kiyohara static int
342 1.1 kiyohara ichsmb_intr(void *arg)
343 1.1 kiyohara {
344 1.1 kiyohara struct ichsmb_softc *sc = arg;
345 1.1 kiyohara uint8_t st;
346 1.1 kiyohara uint8_t *b;
347 1.1 kiyohara size_t len;
348 1.4 kiyohara #ifdef ICHIIC_DEBUG
349 1.4 kiyohara char fbuf[64];
350 1.4 kiyohara #endif
351 1.1 kiyohara
352 1.1 kiyohara /* Read status */
353 1.5 xtraeme st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS);
354 1.5 xtraeme if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR |
355 1.5 xtraeme LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED |
356 1.5 xtraeme LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0)
357 1.1 kiyohara /* Interrupt was not for us */
358 1.1 kiyohara return (0);
359 1.1 kiyohara
360 1.4 kiyohara #ifdef ICHIIC_DEBUG
361 1.18 christos snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st);
362 1.12 kiyohara printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf);
363 1.4 kiyohara #endif
364 1.1 kiyohara
365 1.1 kiyohara /* Clear status bits */
366 1.5 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st);
367 1.1 kiyohara
368 1.1 kiyohara /* Check for errors */
369 1.5 xtraeme if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) {
370 1.1 kiyohara sc->sc_i2c_xfer.error = 1;
371 1.1 kiyohara goto done;
372 1.1 kiyohara }
373 1.1 kiyohara
374 1.5 xtraeme if (st & LPCIB_SMB_HS_INTR) {
375 1.1 kiyohara if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op))
376 1.1 kiyohara goto done;
377 1.1 kiyohara
378 1.1 kiyohara /* Read data */
379 1.1 kiyohara b = sc->sc_i2c_xfer.buf;
380 1.1 kiyohara len = sc->sc_i2c_xfer.len;
381 1.1 kiyohara if (len > 0)
382 1.1 kiyohara b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh,
383 1.5 xtraeme LPCIB_SMB_HD0);
384 1.1 kiyohara if (len > 1)
385 1.1 kiyohara b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh,
386 1.5 xtraeme LPCIB_SMB_HD1);
387 1.1 kiyohara }
388 1.1 kiyohara
389 1.1 kiyohara done:
390 1.1 kiyohara if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0)
391 1.1 kiyohara wakeup(sc);
392 1.1 kiyohara return (1);
393 1.1 kiyohara }
394