ichsmb.c revision 1.3.2.2
1 1.3.2.2 xtraeme /* $NetBSD: ichsmb.c,v 1.3.2.2 2007/08/05 23:05:03 xtraeme Exp $ */ 2 1.3.2.2 xtraeme /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 1.3.2.2 xtraeme 4 1.3.2.2 xtraeme /* 5 1.3.2.2 xtraeme * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 1.3.2.2 xtraeme * 7 1.3.2.2 xtraeme * Permission to use, copy, modify, and distribute this software for any 8 1.3.2.2 xtraeme * purpose with or without fee is hereby granted, provided that the above 9 1.3.2.2 xtraeme * copyright notice and this permission notice appear in all copies. 10 1.3.2.2 xtraeme * 11 1.3.2.2 xtraeme * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 1.3.2.2 xtraeme * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 1.3.2.2 xtraeme * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 1.3.2.2 xtraeme * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 1.3.2.2 xtraeme * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 1.3.2.2 xtraeme * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 1.3.2.2 xtraeme * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 1.3.2.2 xtraeme */ 19 1.3.2.2 xtraeme 20 1.3.2.2 xtraeme /* 21 1.3.2.2 xtraeme * Intel ICH SMBus controller driver. 22 1.3.2.2 xtraeme */ 23 1.3.2.2 xtraeme 24 1.3.2.2 xtraeme #include <sys/param.h> 25 1.3.2.2 xtraeme #include <sys/device.h> 26 1.3.2.2 xtraeme #include <sys/errno.h> 27 1.3.2.2 xtraeme #include <sys/kernel.h> 28 1.3.2.2 xtraeme #include <sys/lock.h> 29 1.3.2.2 xtraeme #include <sys/proc.h> 30 1.3.2.2 xtraeme 31 1.3.2.2 xtraeme #include <machine/bus.h> 32 1.3.2.2 xtraeme 33 1.3.2.2 xtraeme #include <dev/pci/pcidevs.h> 34 1.3.2.2 xtraeme #include <dev/pci/pcireg.h> 35 1.3.2.2 xtraeme #include <dev/pci/pcivar.h> 36 1.3.2.2 xtraeme 37 1.3.2.2 xtraeme #include <dev/pci/ichreg.h> 38 1.3.2.2 xtraeme 39 1.3.2.2 xtraeme #include <dev/i2c/i2cvar.h> 40 1.3.2.2 xtraeme 41 1.3.2.2 xtraeme #ifdef ICHIIC_DEBUG 42 1.3.2.2 xtraeme #define DPRINTF(x) printf x 43 1.3.2.2 xtraeme #else 44 1.3.2.2 xtraeme #define DPRINTF(x) 45 1.3.2.2 xtraeme #endif 46 1.3.2.2 xtraeme 47 1.3.2.2 xtraeme #define ICHIIC_DELAY 100 48 1.3.2.2 xtraeme #define ICHIIC_TIMEOUT 1 49 1.3.2.2 xtraeme 50 1.3.2.2 xtraeme struct ichsmb_softc { 51 1.3.2.2 xtraeme struct device sc_dev; 52 1.3.2.2 xtraeme 53 1.3.2.2 xtraeme bus_space_tag_t sc_iot; 54 1.3.2.2 xtraeme bus_space_handle_t sc_ioh; 55 1.3.2.2 xtraeme void * sc_ih; 56 1.3.2.2 xtraeme int sc_poll; 57 1.3.2.2 xtraeme 58 1.3.2.2 xtraeme struct i2c_controller sc_i2c_tag; 59 1.3.2.2 xtraeme struct lock sc_i2c_lock; 60 1.3.2.2 xtraeme struct { 61 1.3.2.2 xtraeme i2c_op_t op; 62 1.3.2.2 xtraeme void * buf; 63 1.3.2.2 xtraeme size_t len; 64 1.3.2.2 xtraeme int flags; 65 1.3.2.2 xtraeme volatile int error; 66 1.3.2.2 xtraeme } sc_i2c_xfer; 67 1.3.2.2 xtraeme }; 68 1.3.2.2 xtraeme 69 1.3.2.2 xtraeme static int ichsmb_match(struct device *, struct cfdata *, void *); 70 1.3.2.2 xtraeme static void ichsmb_attach(struct device *, struct device *, void *); 71 1.3.2.2 xtraeme 72 1.3.2.2 xtraeme static int ichsmb_i2c_acquire_bus(void *, int); 73 1.3.2.2 xtraeme static void ichsmb_i2c_release_bus(void *, int); 74 1.3.2.2 xtraeme static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 75 1.3.2.2 xtraeme size_t, void *, size_t, int); 76 1.3.2.2 xtraeme 77 1.3.2.2 xtraeme static int ichsmb_intr(void *); 78 1.3.2.2 xtraeme 79 1.3.2.2 xtraeme 80 1.3.2.2 xtraeme CFATTACH_DECL(ichsmb, sizeof(struct ichsmb_softc), 81 1.3.2.2 xtraeme ichsmb_match, ichsmb_attach, NULL, NULL); 82 1.3.2.2 xtraeme 83 1.3.2.2 xtraeme 84 1.3.2.2 xtraeme static int 85 1.3.2.2 xtraeme ichsmb_match(struct device *parent, struct cfdata *match, void *aux) 86 1.3.2.2 xtraeme { 87 1.3.2.2 xtraeme struct pci_attach_args *pa = aux; 88 1.3.2.2 xtraeme 89 1.3.2.2 xtraeme if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 90 1.3.2.2 xtraeme switch (PCI_PRODUCT(pa->pa_id)) { 91 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_6300ESB_SMB: 92 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_63XXESB_SMB: 93 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801AA_SMB: 94 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801AB_SMB: 95 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801BA_SMB: 96 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801CA_SMB: 97 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801DB_SMB: 98 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801E_SMB: 99 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801EB_SMB: 100 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801FB_SMB: 101 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801G_SMB: 102 1.3.2.2 xtraeme case PCI_PRODUCT_INTEL_82801H_SMB: 103 1.3.2.2 xtraeme return 1; 104 1.3.2.2 xtraeme } 105 1.3.2.2 xtraeme } 106 1.3.2.2 xtraeme return 0; 107 1.3.2.2 xtraeme } 108 1.3.2.2 xtraeme 109 1.3.2.2 xtraeme static void 110 1.3.2.2 xtraeme ichsmb_attach(struct device *parent, struct device *self, void *aux) 111 1.3.2.2 xtraeme { 112 1.3.2.2 xtraeme struct ichsmb_softc *sc = (struct ichsmb_softc *)self; 113 1.3.2.2 xtraeme struct pci_attach_args *pa = aux; 114 1.3.2.2 xtraeme struct i2cbus_attach_args iba; 115 1.3.2.2 xtraeme pcireg_t conf; 116 1.3.2.2 xtraeme bus_size_t iosize; 117 1.3.2.2 xtraeme pci_intr_handle_t ih; 118 1.3.2.2 xtraeme const char *intrstr = NULL; 119 1.3.2.2 xtraeme char devinfo[256]; 120 1.3.2.2 xtraeme 121 1.3.2.2 xtraeme aprint_naive("\n"); 122 1.3.2.2 xtraeme pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 123 1.3.2.2 xtraeme aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 124 1.3.2.2 xtraeme PCI_REVISION(pa->pa_class)); 125 1.3.2.2 xtraeme 126 1.3.2.2 xtraeme /* Read configuration */ 127 1.3.2.2 xtraeme conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 128 1.3.2.2 xtraeme DPRINTF(("%s: conf 0x%08x", sc->sc_dev.dv_xname, conf)); 129 1.3.2.2 xtraeme 130 1.3.2.2 xtraeme if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 131 1.3.2.2 xtraeme aprint_error("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 132 1.3.2.2 xtraeme return; 133 1.3.2.2 xtraeme } 134 1.3.2.2 xtraeme 135 1.3.2.2 xtraeme /* Map I/O space */ 136 1.3.2.2 xtraeme if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 137 1.3.2.2 xtraeme &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 138 1.3.2.2 xtraeme aprint_error("%s: can't map I/O space\n", sc->sc_dev.dv_xname); 139 1.3.2.2 xtraeme return; 140 1.3.2.2 xtraeme } 141 1.3.2.2 xtraeme 142 1.3.2.2 xtraeme sc->sc_poll = 1; 143 1.3.2.2 xtraeme if (conf & ICH_SMB_HOSTC_SMIEN) { 144 1.3.2.2 xtraeme /* No PCI IRQ */ 145 1.3.2.2 xtraeme aprint_normal("%s: SMI\n", sc->sc_dev.dv_xname); 146 1.3.2.2 xtraeme } else { 147 1.3.2.2 xtraeme /* Install interrupt handler */ 148 1.3.2.2 xtraeme if (pci_intr_map(pa, &ih) == 0) { 149 1.3.2.2 xtraeme intrstr = pci_intr_string(pa->pa_pc, ih); 150 1.3.2.2 xtraeme sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 151 1.3.2.2 xtraeme ichsmb_intr, sc); 152 1.3.2.2 xtraeme if (sc->sc_ih != NULL) { 153 1.3.2.2 xtraeme aprint_normal("%s: interrupting at %s\n", 154 1.3.2.2 xtraeme sc->sc_dev.dv_xname, intrstr); 155 1.3.2.2 xtraeme sc->sc_poll = 0; 156 1.3.2.2 xtraeme } 157 1.3.2.2 xtraeme } 158 1.3.2.2 xtraeme if (sc->sc_poll) 159 1.3.2.2 xtraeme aprint_normal("%s: polling\n", sc->sc_dev.dv_xname); 160 1.3.2.2 xtraeme } 161 1.3.2.2 xtraeme 162 1.3.2.2 xtraeme /* Attach I2C bus */ 163 1.3.2.2 xtraeme lockinit(&sc->sc_i2c_lock, PZERO, "smblk", 0, 0); 164 1.3.2.2 xtraeme sc->sc_i2c_tag.ic_cookie = sc; 165 1.3.2.2 xtraeme sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 166 1.3.2.2 xtraeme sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 167 1.3.2.2 xtraeme sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 168 1.3.2.2 xtraeme 169 1.3.2.2 xtraeme bzero(&iba, sizeof(iba)); 170 1.3.2.2 xtraeme iba.iba_tag = &sc->sc_i2c_tag; 171 1.3.2.2 xtraeme config_found(self, &iba, iicbus_print); 172 1.3.2.2 xtraeme 173 1.3.2.2 xtraeme return; 174 1.3.2.2 xtraeme } 175 1.3.2.2 xtraeme 176 1.3.2.2 xtraeme static int 177 1.3.2.2 xtraeme ichsmb_i2c_acquire_bus(void *cookie, int flags) 178 1.3.2.2 xtraeme { 179 1.3.2.2 xtraeme struct ichsmb_softc *sc = cookie; 180 1.3.2.2 xtraeme 181 1.3.2.2 xtraeme if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 182 1.3.2.2 xtraeme return (0); 183 1.3.2.2 xtraeme 184 1.3.2.2 xtraeme return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 185 1.3.2.2 xtraeme } 186 1.3.2.2 xtraeme 187 1.3.2.2 xtraeme static void 188 1.3.2.2 xtraeme ichsmb_i2c_release_bus(void *cookie, int flags) 189 1.3.2.2 xtraeme { 190 1.3.2.2 xtraeme struct ichsmb_softc *sc = cookie; 191 1.3.2.2 xtraeme 192 1.3.2.2 xtraeme if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 193 1.3.2.2 xtraeme return; 194 1.3.2.2 xtraeme 195 1.3.2.2 xtraeme lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 196 1.3.2.2 xtraeme } 197 1.3.2.2 xtraeme 198 1.3.2.2 xtraeme static int 199 1.3.2.2 xtraeme ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 200 1.3.2.2 xtraeme const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 201 1.3.2.2 xtraeme { 202 1.3.2.2 xtraeme struct ichsmb_softc *sc = cookie; 203 1.3.2.2 xtraeme const uint8_t *b; 204 1.3.2.2 xtraeme uint8_t ctl = 0, st; 205 1.3.2.2 xtraeme int retries; 206 1.3.2.2 xtraeme 207 1.3.2.2 xtraeme DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %d, " 208 1.3.2.2 xtraeme "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 209 1.3.2.2 xtraeme len, flags)); 210 1.3.2.2 xtraeme 211 1.3.2.2 xtraeme /* Wait for bus to be idle */ 212 1.3.2.2 xtraeme for (retries = 100; retries > 0; retries--) { 213 1.3.2.2 xtraeme st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 214 1.3.2.2 xtraeme if (!(st & ICH_SMB_HS_BUSY)) 215 1.3.2.2 xtraeme break; 216 1.3.2.2 xtraeme DELAY(ICHIIC_DELAY); 217 1.3.2.2 xtraeme } 218 1.3.2.2 xtraeme DPRINTF(("%s: exec: st 0x%02x\n", sc->sc_dev.dv_xname, st)); 219 1.3.2.2 xtraeme if (st & ICH_SMB_HS_BUSY) 220 1.3.2.2 xtraeme return (1); 221 1.3.2.2 xtraeme 222 1.3.2.2 xtraeme if (cold || sc->sc_poll) 223 1.3.2.2 xtraeme flags |= I2C_F_POLL; 224 1.3.2.2 xtraeme 225 1.3.2.2 xtraeme if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 226 1.3.2.2 xtraeme return (1); 227 1.3.2.2 xtraeme 228 1.3.2.2 xtraeme /* Setup transfer */ 229 1.3.2.2 xtraeme sc->sc_i2c_xfer.op = op; 230 1.3.2.2 xtraeme sc->sc_i2c_xfer.buf = buf; 231 1.3.2.2 xtraeme sc->sc_i2c_xfer.len = len; 232 1.3.2.2 xtraeme sc->sc_i2c_xfer.flags = flags; 233 1.3.2.2 xtraeme sc->sc_i2c_xfer.error = 0; 234 1.3.2.2 xtraeme 235 1.3.2.2 xtraeme /* Set slave address and transfer direction */ 236 1.3.2.2 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 237 1.3.2.2 xtraeme ICH_SMB_TXSLVA_ADDR(addr) | 238 1.3.2.2 xtraeme (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 239 1.3.2.2 xtraeme 240 1.3.2.2 xtraeme b = (const uint8_t *)cmdbuf; 241 1.3.2.2 xtraeme if (cmdlen > 0) 242 1.3.2.2 xtraeme /* Set command byte */ 243 1.3.2.2 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 244 1.3.2.2 xtraeme 245 1.3.2.2 xtraeme if (I2C_OP_WRITE_P(op)) { 246 1.3.2.2 xtraeme /* Write data */ 247 1.3.2.2 xtraeme b = buf; 248 1.3.2.2 xtraeme if (len > 0) 249 1.3.2.2 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, 250 1.3.2.2 xtraeme ICH_SMB_HD0, b[0]); 251 1.3.2.2 xtraeme if (len > 1) 252 1.3.2.2 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, 253 1.3.2.2 xtraeme ICH_SMB_HD1, b[1]); 254 1.3.2.2 xtraeme } 255 1.3.2.2 xtraeme 256 1.3.2.2 xtraeme /* Set SMBus command */ 257 1.3.2.2 xtraeme if (len == 0) 258 1.3.2.2 xtraeme ctl = ICH_SMB_HC_CMD_BYTE; 259 1.3.2.2 xtraeme else if (len == 1) 260 1.3.2.2 xtraeme ctl = ICH_SMB_HC_CMD_BDATA; 261 1.3.2.2 xtraeme else if (len == 2) 262 1.3.2.2 xtraeme ctl = ICH_SMB_HC_CMD_WDATA; 263 1.3.2.2 xtraeme 264 1.3.2.2 xtraeme if ((flags & I2C_F_POLL) == 0) 265 1.3.2.2 xtraeme ctl |= ICH_SMB_HC_INTREN; 266 1.3.2.2 xtraeme 267 1.3.2.2 xtraeme /* Start transaction */ 268 1.3.2.2 xtraeme ctl |= ICH_SMB_HC_START; 269 1.3.2.2 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 270 1.3.2.2 xtraeme 271 1.3.2.2 xtraeme if (flags & I2C_F_POLL) { 272 1.3.2.2 xtraeme /* Poll for completion */ 273 1.3.2.2 xtraeme DELAY(ICHIIC_DELAY); 274 1.3.2.2 xtraeme for (retries = 1000; retries > 0; retries--) { 275 1.3.2.2 xtraeme st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 276 1.3.2.2 xtraeme ICH_SMB_HS); 277 1.3.2.2 xtraeme if ((st & ICH_SMB_HS_BUSY) == 0) 278 1.3.2.2 xtraeme break; 279 1.3.2.2 xtraeme DELAY(ICHIIC_DELAY); 280 1.3.2.2 xtraeme } 281 1.3.2.2 xtraeme if (st & ICH_SMB_HS_BUSY) 282 1.3.2.2 xtraeme goto timeout; 283 1.3.2.2 xtraeme ichsmb_intr(sc); 284 1.3.2.2 xtraeme } else { 285 1.3.2.2 xtraeme /* Wait for interrupt */ 286 1.3.2.2 xtraeme if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 287 1.3.2.2 xtraeme goto timeout; 288 1.3.2.2 xtraeme } 289 1.3.2.2 xtraeme 290 1.3.2.2 xtraeme if (sc->sc_i2c_xfer.error) 291 1.3.2.2 xtraeme return (1); 292 1.3.2.2 xtraeme 293 1.3.2.2 xtraeme return (0); 294 1.3.2.2 xtraeme 295 1.3.2.2 xtraeme timeout: 296 1.3.2.2 xtraeme /* 297 1.3.2.2 xtraeme * Transfer timeout. Kill the transaction and clear status bits. 298 1.3.2.2 xtraeme */ 299 1.3.2.2 xtraeme printf("%s: exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 300 1.3.2.2 xtraeme "flags 0x%02x: timeout, status 0x%02x\n", 301 1.3.2.2 xtraeme sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags, 302 1.3.2.2 xtraeme st); 303 1.3.2.2 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 304 1.3.2.2 xtraeme ICH_SMB_HC_KILL); 305 1.3.2.2 xtraeme DELAY(ICHIIC_DELAY); 306 1.3.2.2 xtraeme st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 307 1.3.2.2 xtraeme if ((st & ICH_SMB_HS_FAILED) == 0) 308 1.3.2.2 xtraeme printf("%s: abort failed, status 0x%02x\n", 309 1.3.2.2 xtraeme sc->sc_dev.dv_xname, st); 310 1.3.2.2 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 311 1.3.2.2 xtraeme return (1); 312 1.3.2.2 xtraeme } 313 1.3.2.2 xtraeme 314 1.3.2.2 xtraeme static int 315 1.3.2.2 xtraeme ichsmb_intr(void *arg) 316 1.3.2.2 xtraeme { 317 1.3.2.2 xtraeme struct ichsmb_softc *sc = arg; 318 1.3.2.2 xtraeme uint8_t st; 319 1.3.2.2 xtraeme uint8_t *b; 320 1.3.2.2 xtraeme size_t len; 321 1.3.2.2 xtraeme 322 1.3.2.2 xtraeme /* Read status */ 323 1.3.2.2 xtraeme st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 324 1.3.2.2 xtraeme if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 325 1.3.2.2 xtraeme ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 326 1.3.2.2 xtraeme ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0) 327 1.3.2.2 xtraeme /* Interrupt was not for us */ 328 1.3.2.2 xtraeme return (0); 329 1.3.2.2 xtraeme 330 1.3.2.2 xtraeme DPRINTF(("%s: intr st 0x%02x\n", sc->sc_dev.dv_xname, st)); 331 1.3.2.2 xtraeme 332 1.3.2.2 xtraeme /* Clear status bits */ 333 1.3.2.2 xtraeme bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 334 1.3.2.2 xtraeme 335 1.3.2.2 xtraeme /* Check for errors */ 336 1.3.2.2 xtraeme if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 337 1.3.2.2 xtraeme sc->sc_i2c_xfer.error = 1; 338 1.3.2.2 xtraeme goto done; 339 1.3.2.2 xtraeme } 340 1.3.2.2 xtraeme 341 1.3.2.2 xtraeme if (st & ICH_SMB_HS_INTR) { 342 1.3.2.2 xtraeme if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 343 1.3.2.2 xtraeme goto done; 344 1.3.2.2 xtraeme 345 1.3.2.2 xtraeme /* Read data */ 346 1.3.2.2 xtraeme b = sc->sc_i2c_xfer.buf; 347 1.3.2.2 xtraeme len = sc->sc_i2c_xfer.len; 348 1.3.2.2 xtraeme if (len > 0) 349 1.3.2.2 xtraeme b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 350 1.3.2.2 xtraeme ICH_SMB_HD0); 351 1.3.2.2 xtraeme if (len > 1) 352 1.3.2.2 xtraeme b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 353 1.3.2.2 xtraeme ICH_SMB_HD1); 354 1.3.2.2 xtraeme } 355 1.3.2.2 xtraeme 356 1.3.2.2 xtraeme done: 357 1.3.2.2 xtraeme if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 358 1.3.2.2 xtraeme wakeup(sc); 359 1.3.2.2 xtraeme return (1); 360 1.3.2.2 xtraeme } 361
Indexes created Fri Oct 03 02:09:57 GMT 2025