ichsmb.c revision 1.1.4.1
1 /* $NetBSD: ichsmb.c,v 1.1.4.1 2007/08/09 02:37:10 jmcneill Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/errno.h> 27 #include <sys/kernel.h> 28 #include <sys/lock.h> 29 #include <sys/proc.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcidevs.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 37 #include <dev/pci/ichreg.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #ifdef ICHIIC_DEBUG 42 #define DPRINTF(x) printf x 43 #else 44 #define DPRINTF(x) 45 #endif 46 47 #define ICHIIC_DELAY 100 48 #define ICHIIC_TIMEOUT 1 49 50 struct ichsmb_softc { 51 struct device sc_dev; 52 53 bus_space_tag_t sc_iot; 54 bus_space_handle_t sc_ioh; 55 void * sc_ih; 56 int sc_poll; 57 58 struct i2c_controller sc_i2c_tag; 59 struct lock sc_i2c_lock; 60 struct { 61 i2c_op_t op; 62 void * buf; 63 size_t len; 64 int flags; 65 volatile int error; 66 } sc_i2c_xfer; 67 }; 68 69 static int ichsmb_match(struct device *, struct cfdata *, void *); 70 static void ichsmb_attach(struct device *, struct device *, void *); 71 72 static int ichsmb_i2c_acquire_bus(void *, int); 73 static void ichsmb_i2c_release_bus(void *, int); 74 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 75 size_t, void *, size_t, int); 76 77 static int ichsmb_intr(void *); 78 79 80 CFATTACH_DECL(ichsmb, sizeof(struct ichsmb_softc), 81 ichsmb_match, ichsmb_attach, NULL, NULL); 82 83 84 static int 85 ichsmb_match(struct device *parent, struct cfdata *match, void *aux) 86 { 87 struct pci_attach_args *pa = aux; 88 89 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 90 switch (PCI_PRODUCT(pa->pa_id)) { 91 case PCI_PRODUCT_INTEL_6300ESB_SMB: 92 case PCI_PRODUCT_INTEL_63XXESB_SMB: 93 case PCI_PRODUCT_INTEL_82801AA_SMB: 94 case PCI_PRODUCT_INTEL_82801AB_SMB: 95 case PCI_PRODUCT_INTEL_82801BA_SMB: 96 case PCI_PRODUCT_INTEL_82801CA_SMB: 97 case PCI_PRODUCT_INTEL_82801DB_SMB: 98 case PCI_PRODUCT_INTEL_82801E_SMB: 99 case PCI_PRODUCT_INTEL_82801EB_SMB: 100 case PCI_PRODUCT_INTEL_82801FB_SMB: 101 case PCI_PRODUCT_INTEL_82801G_SMB: 102 case PCI_PRODUCT_INTEL_82801H_SMB: 103 return 1; 104 } 105 } 106 return 0; 107 } 108 109 static void 110 ichsmb_attach(struct device *parent, struct device *self, void *aux) 111 { 112 struct ichsmb_softc *sc = (struct ichsmb_softc *)self; 113 struct pci_attach_args *pa = aux; 114 struct i2cbus_attach_args iba; 115 pcireg_t conf; 116 bus_size_t iosize; 117 pci_intr_handle_t ih; 118 const char *intrstr = NULL; 119 char devinfo[256]; 120 121 aprint_naive("\n"); 122 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 123 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 124 PCI_REVISION(pa->pa_class)); 125 126 /* Read configuration */ 127 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 128 DPRINTF(("%s: conf 0x%08x", sc->sc_dev.dv_xname, conf)); 129 130 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 131 aprint_error("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 132 return; 133 } 134 135 /* Map I/O space */ 136 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 137 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 138 aprint_error("%s: can't map I/O space\n", sc->sc_dev.dv_xname); 139 return; 140 } 141 142 sc->sc_poll = 1; 143 if (conf & ICH_SMB_HOSTC_SMIEN) { 144 /* No PCI IRQ */ 145 aprint_normal("%s: SMI\n", sc->sc_dev.dv_xname); 146 } else { 147 /* Install interrupt handler */ 148 if (pci_intr_map(pa, &ih) == 0) { 149 intrstr = pci_intr_string(pa->pa_pc, ih); 150 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 151 ichsmb_intr, sc); 152 if (sc->sc_ih != NULL) { 153 aprint_normal("%s: interrupting at %s\n", 154 sc->sc_dev.dv_xname, intrstr); 155 sc->sc_poll = 0; 156 } 157 } 158 if (sc->sc_poll) 159 aprint_normal("%s: polling\n", sc->sc_dev.dv_xname); 160 } 161 162 /* Attach I2C bus */ 163 lockinit(&sc->sc_i2c_lock, PZERO, "smblk", 0, 0); 164 sc->sc_i2c_tag.ic_cookie = sc; 165 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 166 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 167 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 168 169 bzero(&iba, sizeof(iba)); 170 iba.iba_tag = &sc->sc_i2c_tag; 171 config_found(self, &iba, iicbus_print); 172 173 return; 174 } 175 176 static int 177 ichsmb_i2c_acquire_bus(void *cookie, int flags) 178 { 179 struct ichsmb_softc *sc = cookie; 180 181 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 182 return (0); 183 184 return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 185 } 186 187 static void 188 ichsmb_i2c_release_bus(void *cookie, int flags) 189 { 190 struct ichsmb_softc *sc = cookie; 191 192 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 193 return; 194 195 lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 196 } 197 198 static int 199 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 200 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 201 { 202 struct ichsmb_softc *sc = cookie; 203 const uint8_t *b; 204 uint8_t ctl = 0, st; 205 int retries; 206 207 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %d, " 208 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 209 len, flags)); 210 211 /* Wait for bus to be idle */ 212 for (retries = 100; retries > 0; retries--) { 213 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 214 if (!(st & ICH_SMB_HS_BUSY)) 215 break; 216 DELAY(ICHIIC_DELAY); 217 } 218 DPRINTF(("%s: exec: st 0x%02x\n", sc->sc_dev.dv_xname, st)); 219 if (st & ICH_SMB_HS_BUSY) 220 return (1); 221 222 if (cold || sc->sc_poll) 223 flags |= I2C_F_POLL; 224 225 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 226 return (1); 227 228 /* Setup transfer */ 229 sc->sc_i2c_xfer.op = op; 230 sc->sc_i2c_xfer.buf = buf; 231 sc->sc_i2c_xfer.len = len; 232 sc->sc_i2c_xfer.flags = flags; 233 sc->sc_i2c_xfer.error = 0; 234 235 /* Set slave address and transfer direction */ 236 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 237 ICH_SMB_TXSLVA_ADDR(addr) | 238 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 239 240 b = (const uint8_t *)cmdbuf; 241 if (cmdlen > 0) 242 /* Set command byte */ 243 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 244 245 if (I2C_OP_WRITE_P(op)) { 246 /* Write data */ 247 b = buf; 248 if (len > 0) 249 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 250 ICH_SMB_HD0, b[0]); 251 if (len > 1) 252 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 253 ICH_SMB_HD1, b[1]); 254 } 255 256 /* Set SMBus command */ 257 if (len == 0) 258 ctl = ICH_SMB_HC_CMD_BYTE; 259 else if (len == 1) 260 ctl = ICH_SMB_HC_CMD_BDATA; 261 else if (len == 2) 262 ctl = ICH_SMB_HC_CMD_WDATA; 263 264 if ((flags & I2C_F_POLL) == 0) 265 ctl |= ICH_SMB_HC_INTREN; 266 267 /* Start transaction */ 268 ctl |= ICH_SMB_HC_START; 269 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 270 271 if (flags & I2C_F_POLL) { 272 /* Poll for completion */ 273 DELAY(ICHIIC_DELAY); 274 for (retries = 1000; retries > 0; retries--) { 275 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 276 ICH_SMB_HS); 277 if ((st & ICH_SMB_HS_BUSY) == 0) 278 break; 279 DELAY(ICHIIC_DELAY); 280 } 281 if (st & ICH_SMB_HS_BUSY) 282 goto timeout; 283 ichsmb_intr(sc); 284 } else { 285 /* Wait for interrupt */ 286 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 287 goto timeout; 288 } 289 290 if (sc->sc_i2c_xfer.error) 291 return (1); 292 293 return (0); 294 295 timeout: 296 /* 297 * Transfer timeout. Kill the transaction and clear status bits. 298 */ 299 printf("%s: exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 300 "flags 0x%02x: timeout, status 0x%02x\n", 301 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags, 302 st); 303 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 304 ICH_SMB_HC_KILL); 305 DELAY(ICHIIC_DELAY); 306 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 307 if ((st & ICH_SMB_HS_FAILED) == 0) 308 printf("%s: abort failed, status 0x%02x\n", 309 sc->sc_dev.dv_xname, st); 310 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 311 return (1); 312 } 313 314 static int 315 ichsmb_intr(void *arg) 316 { 317 struct ichsmb_softc *sc = arg; 318 uint8_t st; 319 uint8_t *b; 320 size_t len; 321 322 /* Read status */ 323 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 324 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 325 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 326 ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0) 327 /* Interrupt was not for us */ 328 return (0); 329 330 DPRINTF(("%s: intr st 0x%02x\n", sc->sc_dev.dv_xname, st)); 331 332 /* Clear status bits */ 333 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 334 335 /* Check for errors */ 336 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 337 sc->sc_i2c_xfer.error = 1; 338 goto done; 339 } 340 341 if (st & ICH_SMB_HS_INTR) { 342 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 343 goto done; 344 345 /* Read data */ 346 b = sc->sc_i2c_xfer.buf; 347 len = sc->sc_i2c_xfer.len; 348 if (len > 0) 349 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 350 ICH_SMB_HD0); 351 if (len > 1) 352 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 353 ICH_SMB_HD1); 354 } 355 356 done: 357 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 358 wakeup(sc); 359 return (1); 360 } 361
Indexes created Thu Oct 02 14:10:14 GMT 2025