ichsmb.c revision 1.1.4.4
1 /* $NetBSD: ichsmb.c,v 1.1.4.4 2007/10/26 15:46:01 joerg Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.1.4.4 2007/10/26 15:46:01 joerg Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/rwlock.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 struct device sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 krwlock_t sc_i2c_rwlock; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(struct device *, struct cfdata *, void *); 73 static void ichsmb_attach(struct device *, struct device *, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(struct device *parent, struct cfdata *match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 return 1; 108 } 109 } 110 return 0; 111 } 112 113 static void 114 ichsmb_attach(struct device *parent, struct device *self, void *aux) 115 { 116 struct ichsmb_softc *sc = (struct ichsmb_softc *)self; 117 struct pci_attach_args *pa = aux; 118 struct i2cbus_attach_args iba; 119 pcireg_t conf; 120 bus_size_t iosize; 121 pci_intr_handle_t ih; 122 const char *intrstr = NULL; 123 char devinfo[256]; 124 125 aprint_naive("\n"); 126 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 127 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 128 PCI_REVISION(pa->pa_class)); 129 130 /* Read configuration */ 131 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 132 DPRINTF(("%s: conf 0x%08x", sc->sc_dev.dv_xname, conf)); 133 134 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 135 aprint_error("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 136 return; 137 } 138 139 /* Map I/O space */ 140 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 141 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 142 aprint_error("%s: can't map I/O space\n", sc->sc_dev.dv_xname); 143 return; 144 } 145 146 sc->sc_poll = 1; 147 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 148 /* No PCI IRQ */ 149 aprint_normal("%s: SMI\n", sc->sc_dev.dv_xname); 150 } else { 151 /* Install interrupt handler */ 152 if (pci_intr_map(pa, &ih) == 0) { 153 intrstr = pci_intr_string(pa->pa_pc, ih); 154 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 155 ichsmb_intr, sc); 156 if (sc->sc_ih != NULL) { 157 aprint_normal("%s: interrupting at %s\n", 158 sc->sc_dev.dv_xname, intrstr); 159 sc->sc_poll = 0; 160 } 161 } 162 if (sc->sc_poll) 163 aprint_normal("%s: polling\n", sc->sc_dev.dv_xname); 164 } 165 166 /* Attach I2C bus */ 167 rw_init(&sc->sc_i2c_rwlock); 168 sc->sc_i2c_tag.ic_cookie = sc; 169 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 170 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 171 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 172 173 bzero(&iba, sizeof(iba)); 174 iba.iba_type = I2C_TYPE_SMBUS; 175 iba.iba_tag = &sc->sc_i2c_tag; 176 config_found(self, &iba, iicbus_print); 177 178 return; 179 } 180 181 static int 182 ichsmb_i2c_acquire_bus(void *cookie, int flags) 183 { 184 struct ichsmb_softc *sc = cookie; 185 186 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 187 return 0; 188 189 rw_enter(&sc->sc_i2c_rwlock, RW_WRITER); 190 return 0; 191 } 192 193 static void 194 ichsmb_i2c_release_bus(void *cookie, int flags) 195 { 196 struct ichsmb_softc *sc = cookie; 197 198 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 199 return; 200 201 rw_exit(&sc->sc_i2c_rwlock); 202 } 203 204 static int 205 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 206 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 207 { 208 struct ichsmb_softc *sc = cookie; 209 const uint8_t *b; 210 uint8_t ctl = 0, st; 211 int retries; 212 char fbuf[64]; 213 214 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %d, " 215 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 216 len, flags)); 217 218 /* Wait for bus to be idle */ 219 for (retries = 100; retries > 0; retries--) { 220 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 221 if (!(st & LPCIB_SMB_HS_BUSY)) 222 break; 223 DELAY(ICHIIC_DELAY); 224 } 225 #ifdef ICHIIC_DEBUG 226 bitmask_snprintf(st, LPCIB_SMB_HS_BITS, fbuf, sizeof(fbuf)); 227 printf("%s: exec: st 0x%s\n", sc->sc_dev.dv_xname, fbuf); 228 #endif 229 if (st & LPCIB_SMB_HS_BUSY) 230 return (1); 231 232 if (cold || sc->sc_poll) 233 flags |= I2C_F_POLL; 234 235 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 236 return (1); 237 238 /* Setup transfer */ 239 sc->sc_i2c_xfer.op = op; 240 sc->sc_i2c_xfer.buf = buf; 241 sc->sc_i2c_xfer.len = len; 242 sc->sc_i2c_xfer.flags = flags; 243 sc->sc_i2c_xfer.error = 0; 244 245 /* Set slave address and transfer direction */ 246 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 247 LPCIB_SMB_TXSLVA_ADDR(addr) | 248 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 249 250 b = (const uint8_t *)cmdbuf; 251 if (cmdlen > 0) 252 /* Set command byte */ 253 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 254 255 if (I2C_OP_WRITE_P(op)) { 256 /* Write data */ 257 b = buf; 258 if (len > 0) 259 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 260 LPCIB_SMB_HD0, b[0]); 261 if (len > 1) 262 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 263 LPCIB_SMB_HD1, b[1]); 264 } 265 266 /* Set SMBus command */ 267 if (len == 0) 268 ctl = LPCIB_SMB_HC_CMD_BYTE; 269 else if (len == 1) 270 ctl = LPCIB_SMB_HC_CMD_BDATA; 271 else if (len == 2) 272 ctl = LPCIB_SMB_HC_CMD_WDATA; 273 274 if ((flags & I2C_F_POLL) == 0) 275 ctl |= LPCIB_SMB_HC_INTREN; 276 277 /* Start transaction */ 278 ctl |= LPCIB_SMB_HC_START; 279 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 280 281 if (flags & I2C_F_POLL) { 282 /* Poll for completion */ 283 DELAY(ICHIIC_DELAY); 284 for (retries = 1000; retries > 0; retries--) { 285 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 286 LPCIB_SMB_HS); 287 if ((st & LPCIB_SMB_HS_BUSY) == 0) 288 break; 289 DELAY(ICHIIC_DELAY); 290 } 291 if (st & LPCIB_SMB_HS_BUSY) 292 goto timeout; 293 ichsmb_intr(sc); 294 } else { 295 /* Wait for interrupt */ 296 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 297 goto timeout; 298 } 299 300 if (sc->sc_i2c_xfer.error) 301 return (1); 302 303 return (0); 304 305 timeout: 306 /* 307 * Transfer timeout. Kill the transaction and clear status bits. 308 */ 309 bitmask_snprintf(st, LPCIB_SMB_HS_BITS, fbuf, sizeof(fbuf)); 310 printf("%s: exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 311 "flags 0x%02x: timeout, status 0x%s\n", 312 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags, fbuf); 313 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 314 LPCIB_SMB_HC_KILL); 315 DELAY(ICHIIC_DELAY); 316 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 317 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 318 bitmask_snprintf(st, LPCIB_SMB_HS_BITS, fbuf, sizeof(fbuf)); 319 printf("%s: abort failed, status 0x%s\n", 320 sc->sc_dev.dv_xname, fbuf); 321 } 322 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 323 return (1); 324 } 325 326 static int 327 ichsmb_intr(void *arg) 328 { 329 struct ichsmb_softc *sc = arg; 330 uint8_t st; 331 uint8_t *b; 332 size_t len; 333 #ifdef ICHIIC_DEBUG 334 char fbuf[64]; 335 #endif 336 337 /* Read status */ 338 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 339 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 340 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 341 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 342 /* Interrupt was not for us */ 343 return (0); 344 345 #ifdef ICHIIC_DEBUG 346 bitmask_snprintf(st, LPCIB_SMB_HS_BITS, fbuf, sizeof(fbuf)); 347 printf("%s: intr st 0x%s\n", sc->sc_dev.dv_xname, fbuf); 348 #endif 349 350 /* Clear status bits */ 351 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 352 353 /* Check for errors */ 354 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 355 sc->sc_i2c_xfer.error = 1; 356 goto done; 357 } 358 359 if (st & LPCIB_SMB_HS_INTR) { 360 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 361 goto done; 362 363 /* Read data */ 364 b = sc->sc_i2c_xfer.buf; 365 len = sc->sc_i2c_xfer.len; 366 if (len > 0) 367 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 368 LPCIB_SMB_HD0); 369 if (len > 1) 370 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 371 LPCIB_SMB_HD1); 372 } 373 374 done: 375 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 376 wakeup(sc); 377 return (1); 378 } 379
Indexes created Thu Oct 02 14:10:14 GMT 2025