ichsmb.c revision 1.22.4.1
1 /* $NetBSD: ichsmb.c,v 1.22.4.1 2011/03/05 20:53:37 rmind Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.22.4.1 2011/03/05 20:53:37 rmind Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/rwlock.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 krwlock_t sc_i2c_rwlock; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 return 1; 111 } 112 } 113 return 0; 114 } 115 116 static void 117 ichsmb_attach(device_t parent, device_t self, void *aux) 118 { 119 struct ichsmb_softc *sc = device_private(self); 120 struct pci_attach_args *pa = aux; 121 struct i2cbus_attach_args iba; 122 pcireg_t conf; 123 bus_size_t iosize; 124 pci_intr_handle_t ih; 125 const char *intrstr = NULL; 126 char devinfo[256]; 127 128 sc->sc_dev = self; 129 130 aprint_naive("\n"); 131 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 132 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 133 PCI_REVISION(pa->pa_class)); 134 135 /* Read configuration */ 136 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 137 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 138 139 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 140 aprint_error_dev(self, "SMBus disabled\n"); 141 return; 142 } 143 144 /* Map I/O space */ 145 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 146 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 147 aprint_error_dev(self, "can't map I/O space\n"); 148 return; 149 } 150 151 sc->sc_poll = 1; 152 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 153 /* No PCI IRQ */ 154 aprint_normal_dev(self, "interrupting at SMI\n"); 155 } else { 156 /* Install interrupt handler */ 157 if (pci_intr_map(pa, &ih) == 0) { 158 intrstr = pci_intr_string(pa->pa_pc, ih); 159 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 160 ichsmb_intr, sc); 161 if (sc->sc_ih != NULL) { 162 aprint_normal_dev(self, "interrupting at %s\n", 163 intrstr); 164 sc->sc_poll = 0; 165 } 166 } 167 if (sc->sc_poll) 168 aprint_normal_dev(self, "polling\n"); 169 } 170 171 /* Attach I2C bus */ 172 rw_init(&sc->sc_i2c_rwlock); 173 sc->sc_i2c_tag.ic_cookie = sc; 174 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 175 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 176 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 177 178 memset(&iba, 0, sizeof(iba)); 179 iba.iba_type = I2C_TYPE_SMBUS; 180 iba.iba_tag = &sc->sc_i2c_tag; 181 config_found(self, &iba, iicbus_print); 182 183 if (!pmf_device_register(self, NULL, NULL)) 184 aprint_error_dev(self, "couldn't establish power handler\n"); 185 } 186 187 static int 188 ichsmb_i2c_acquire_bus(void *cookie, int flags) 189 { 190 struct ichsmb_softc *sc = cookie; 191 192 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 193 return 0; 194 195 rw_enter(&sc->sc_i2c_rwlock, RW_WRITER); 196 return 0; 197 } 198 199 static void 200 ichsmb_i2c_release_bus(void *cookie, int flags) 201 { 202 struct ichsmb_softc *sc = cookie; 203 204 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 205 return; 206 207 rw_exit(&sc->sc_i2c_rwlock); 208 } 209 210 static int 211 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 212 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 213 { 214 struct ichsmb_softc *sc = cookie; 215 const uint8_t *b; 216 uint8_t ctl = 0, st; 217 int retries; 218 char fbuf[64]; 219 220 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 221 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 222 len, flags)); 223 224 /* Wait for bus to be idle */ 225 for (retries = 100; retries > 0; retries--) { 226 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 227 if (!(st & LPCIB_SMB_HS_BUSY)) 228 break; 229 DELAY(ICHIIC_DELAY); 230 } 231 #ifdef ICHIIC_DEBUG 232 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 233 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 234 #endif 235 if (st & LPCIB_SMB_HS_BUSY) 236 return (1); 237 238 if (cold || sc->sc_poll) 239 flags |= I2C_F_POLL; 240 241 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 242 (cmdlen == 0 && len > 1)) 243 return (1); 244 245 /* Setup transfer */ 246 sc->sc_i2c_xfer.op = op; 247 sc->sc_i2c_xfer.buf = buf; 248 sc->sc_i2c_xfer.len = len; 249 sc->sc_i2c_xfer.flags = flags; 250 sc->sc_i2c_xfer.error = 0; 251 252 /* Set slave address and transfer direction */ 253 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 254 LPCIB_SMB_TXSLVA_ADDR(addr) | 255 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 256 257 b = (const uint8_t *)cmdbuf; 258 if (cmdlen > 0) 259 /* Set command byte */ 260 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 261 262 if (I2C_OP_WRITE_P(op)) { 263 /* Write data */ 264 b = buf; 265 if (cmdlen == 0 && len == 1) 266 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 267 LPCIB_SMB_HCMD, b[0]); 268 else if (len > 0) 269 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 270 LPCIB_SMB_HD0, b[0]); 271 if (len > 1) 272 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 273 LPCIB_SMB_HD1, b[1]); 274 } 275 276 /* Set SMBus command */ 277 if (cmdlen == 0) { 278 if (len == 0) 279 ctl = LPCIB_SMB_HC_CMD_QUICK; 280 else 281 ctl = LPCIB_SMB_HC_CMD_BYTE; 282 } else if (len == 1) 283 ctl = LPCIB_SMB_HC_CMD_BDATA; 284 else if (len == 2) 285 ctl = LPCIB_SMB_HC_CMD_WDATA; 286 287 if ((flags & I2C_F_POLL) == 0) 288 ctl |= LPCIB_SMB_HC_INTREN; 289 290 /* Start transaction */ 291 ctl |= LPCIB_SMB_HC_START; 292 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 293 294 if (flags & I2C_F_POLL) { 295 /* Poll for completion */ 296 DELAY(ICHIIC_DELAY); 297 for (retries = 1000; retries > 0; retries--) { 298 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 299 LPCIB_SMB_HS); 300 if ((st & LPCIB_SMB_HS_BUSY) == 0) 301 break; 302 DELAY(ICHIIC_DELAY); 303 } 304 if (st & LPCIB_SMB_HS_BUSY) 305 goto timeout; 306 ichsmb_intr(sc); 307 } else { 308 /* Wait for interrupt */ 309 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 310 goto timeout; 311 } 312 313 if (sc->sc_i2c_xfer.error) 314 return (1); 315 316 return (0); 317 318 timeout: 319 /* 320 * Transfer timeout. Kill the transaction and clear status bits. 321 */ 322 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 323 aprint_error_dev(sc->sc_dev, 324 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 325 "flags 0x%02x: timeout, status 0x%s\n", 326 op, addr, cmdlen, len, flags, fbuf); 327 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 328 LPCIB_SMB_HC_KILL); 329 DELAY(ICHIIC_DELAY); 330 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 331 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 332 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 333 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 334 fbuf); 335 } 336 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 337 return (1); 338 } 339 340 static int 341 ichsmb_intr(void *arg) 342 { 343 struct ichsmb_softc *sc = arg; 344 uint8_t st; 345 uint8_t *b; 346 size_t len; 347 #ifdef ICHIIC_DEBUG 348 char fbuf[64]; 349 #endif 350 351 /* Read status */ 352 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 353 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 354 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 355 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 356 /* Interrupt was not for us */ 357 return (0); 358 359 #ifdef ICHIIC_DEBUG 360 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 361 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 362 #endif 363 364 /* Clear status bits */ 365 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 366 367 /* Check for errors */ 368 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 369 sc->sc_i2c_xfer.error = 1; 370 goto done; 371 } 372 373 if (st & LPCIB_SMB_HS_INTR) { 374 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 375 goto done; 376 377 /* Read data */ 378 b = sc->sc_i2c_xfer.buf; 379 len = sc->sc_i2c_xfer.len; 380 if (len > 0) 381 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 382 LPCIB_SMB_HD0); 383 if (len > 1) 384 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 385 LPCIB_SMB_HD1); 386 } 387 388 done: 389 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 390 wakeup(sc); 391 return (1); 392 } 393
Indexes created Thu Oct 02 14:10:14 GMT 2025