ichsmb.c revision 1.25.8.1
1 /* $NetBSD: ichsmb.c,v 1.25.8.1 2012/02/18 07:34:38 mrg Exp $ */ 2 /* $OpenBSD: ichiic.c,v 1.18 2007/05/03 09:36:26 dlg Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel ICH SMBus controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.25.8.1 2012/02/18 07:34:38 mrg Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/errno.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/ic/i82801lpcreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #ifdef ICHIIC_DEBUG 45 #define DPRINTF(x) printf x 46 #else 47 #define DPRINTF(x) 48 #endif 49 50 #define ICHIIC_DELAY 100 51 #define ICHIIC_TIMEOUT 1 52 53 struct ichsmb_softc { 54 device_t sc_dev; 55 56 bus_space_tag_t sc_iot; 57 bus_space_handle_t sc_ioh; 58 void * sc_ih; 59 int sc_poll; 60 61 struct i2c_controller sc_i2c_tag; 62 kmutex_t sc_i2c_mutex; 63 struct { 64 i2c_op_t op; 65 void * buf; 66 size_t len; 67 int flags; 68 volatile int error; 69 } sc_i2c_xfer; 70 }; 71 72 static int ichsmb_match(device_t, cfdata_t, void *); 73 static void ichsmb_attach(device_t, device_t, void *); 74 75 static int ichsmb_i2c_acquire_bus(void *, int); 76 static void ichsmb_i2c_release_bus(void *, int); 77 static int ichsmb_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 78 size_t, void *, size_t, int); 79 80 static int ichsmb_intr(void *); 81 82 83 CFATTACH_DECL_NEW(ichsmb, sizeof(struct ichsmb_softc), 84 ichsmb_match, ichsmb_attach, NULL, NULL); 85 86 87 static int 88 ichsmb_match(device_t parent, cfdata_t match, void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 93 switch (PCI_PRODUCT(pa->pa_id)) { 94 case PCI_PRODUCT_INTEL_6300ESB_SMB: 95 case PCI_PRODUCT_INTEL_63XXESB_SMB: 96 case PCI_PRODUCT_INTEL_82801AA_SMB: 97 case PCI_PRODUCT_INTEL_82801AB_SMB: 98 case PCI_PRODUCT_INTEL_82801BA_SMB: 99 case PCI_PRODUCT_INTEL_82801CA_SMB: 100 case PCI_PRODUCT_INTEL_82801DB_SMB: 101 case PCI_PRODUCT_INTEL_82801E_SMB: 102 case PCI_PRODUCT_INTEL_82801EB_SMB: 103 case PCI_PRODUCT_INTEL_82801FB_SMB: 104 case PCI_PRODUCT_INTEL_82801G_SMB: 105 case PCI_PRODUCT_INTEL_82801H_SMB: 106 case PCI_PRODUCT_INTEL_82801I_SMB: 107 case PCI_PRODUCT_INTEL_82801JD_SMB: 108 case PCI_PRODUCT_INTEL_82801JI_SMB: 109 case PCI_PRODUCT_INTEL_3400_SMB: 110 case PCI_PRODUCT_INTEL_6SERIES_SMB: 111 return 1; 112 } 113 } 114 return 0; 115 } 116 117 static void 118 ichsmb_attach(device_t parent, device_t self, void *aux) 119 { 120 struct ichsmb_softc *sc = device_private(self); 121 struct pci_attach_args *pa = aux; 122 struct i2cbus_attach_args iba; 123 pcireg_t conf; 124 bus_size_t iosize; 125 pci_intr_handle_t ih; 126 const char *intrstr = NULL; 127 128 sc->sc_dev = self; 129 130 pci_aprint_devinfo(pa, NULL); 131 132 /* Read configuration */ 133 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC); 134 DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf)); 135 136 if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) { 137 aprint_error_dev(self, "SMBus disabled\n"); 138 return; 139 } 140 141 /* Map I/O space */ 142 if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 143 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize)) { 144 aprint_error_dev(self, "can't map I/O space\n"); 145 return; 146 } 147 148 sc->sc_poll = 1; 149 if (conf & LPCIB_SMB_HOSTC_SMIEN) { 150 /* No PCI IRQ */ 151 aprint_normal_dev(self, "interrupting at SMI\n"); 152 } else { 153 /* Install interrupt handler */ 154 if (pci_intr_map(pa, &ih) == 0) { 155 intrstr = pci_intr_string(pa->pa_pc, ih); 156 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 157 ichsmb_intr, sc); 158 if (sc->sc_ih != NULL) { 159 aprint_normal_dev(self, "interrupting at %s\n", 160 intrstr); 161 sc->sc_poll = 0; 162 } 163 } 164 if (sc->sc_poll) 165 aprint_normal_dev(self, "polling\n"); 166 } 167 168 /* Attach I2C bus */ 169 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 170 sc->sc_i2c_tag.ic_cookie = sc; 171 sc->sc_i2c_tag.ic_acquire_bus = ichsmb_i2c_acquire_bus; 172 sc->sc_i2c_tag.ic_release_bus = ichsmb_i2c_release_bus; 173 sc->sc_i2c_tag.ic_exec = ichsmb_i2c_exec; 174 175 memset(&iba, 0, sizeof(iba)); 176 iba.iba_type = I2C_TYPE_SMBUS; 177 iba.iba_tag = &sc->sc_i2c_tag; 178 config_found(self, &iba, iicbus_print); 179 180 if (!pmf_device_register(self, NULL, NULL)) 181 aprint_error_dev(self, "couldn't establish power handler\n"); 182 } 183 184 static int 185 ichsmb_i2c_acquire_bus(void *cookie, int flags) 186 { 187 struct ichsmb_softc *sc = cookie; 188 189 if (cold) 190 return 0; 191 192 mutex_enter(&sc->sc_i2c_mutex); 193 return 0; 194 } 195 196 static void 197 ichsmb_i2c_release_bus(void *cookie, int flags) 198 { 199 struct ichsmb_softc *sc = cookie; 200 201 if (cold) 202 return; 203 204 mutex_exit(&sc->sc_i2c_mutex); 205 } 206 207 static int 208 ichsmb_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 209 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 210 { 211 struct ichsmb_softc *sc = cookie; 212 const uint8_t *b; 213 uint8_t ctl = 0, st; 214 int retries; 215 char fbuf[64]; 216 217 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 218 "flags 0x%02x\n", device_xname(sc->sc_dev), op, addr, cmdlen, 219 len, flags)); 220 221 /* Wait for bus to be idle */ 222 for (retries = 100; retries > 0; retries--) { 223 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 224 if (!(st & LPCIB_SMB_HS_BUSY)) 225 break; 226 DELAY(ICHIIC_DELAY); 227 } 228 #ifdef ICHIIC_DEBUG 229 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 230 printf("%s: exec: st 0x%s\n", device_xname(sc->sc_dev), fbuf); 231 #endif 232 if (st & LPCIB_SMB_HS_BUSY) 233 return (1); 234 235 if (cold || sc->sc_poll) 236 flags |= I2C_F_POLL; 237 238 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 239 (cmdlen == 0 && len > 1)) 240 return (1); 241 242 /* Setup transfer */ 243 sc->sc_i2c_xfer.op = op; 244 sc->sc_i2c_xfer.buf = buf; 245 sc->sc_i2c_xfer.len = len; 246 sc->sc_i2c_xfer.flags = flags; 247 sc->sc_i2c_xfer.error = 0; 248 249 /* Set slave address and transfer direction */ 250 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA, 251 LPCIB_SMB_TXSLVA_ADDR(addr) | 252 (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0)); 253 254 b = (const uint8_t *)cmdbuf; 255 if (cmdlen > 0) 256 /* Set command byte */ 257 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]); 258 259 if (I2C_OP_WRITE_P(op)) { 260 /* Write data */ 261 b = buf; 262 if (cmdlen == 0 && len == 1) 263 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 264 LPCIB_SMB_HCMD, b[0]); 265 else if (len > 0) 266 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 267 LPCIB_SMB_HD0, b[0]); 268 if (len > 1) 269 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 270 LPCIB_SMB_HD1, b[1]); 271 } 272 273 /* Set SMBus command */ 274 if (cmdlen == 0) { 275 if (len == 0) 276 ctl = LPCIB_SMB_HC_CMD_QUICK; 277 else 278 ctl = LPCIB_SMB_HC_CMD_BYTE; 279 } else if (len == 1) 280 ctl = LPCIB_SMB_HC_CMD_BDATA; 281 else if (len == 2) 282 ctl = LPCIB_SMB_HC_CMD_WDATA; 283 284 if ((flags & I2C_F_POLL) == 0) 285 ctl |= LPCIB_SMB_HC_INTREN; 286 287 /* Start transaction */ 288 ctl |= LPCIB_SMB_HC_START; 289 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl); 290 291 if (flags & I2C_F_POLL) { 292 /* Poll for completion */ 293 DELAY(ICHIIC_DELAY); 294 for (retries = 1000; retries > 0; retries--) { 295 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 296 LPCIB_SMB_HS); 297 if ((st & LPCIB_SMB_HS_BUSY) == 0) 298 break; 299 DELAY(ICHIIC_DELAY); 300 } 301 if (st & LPCIB_SMB_HS_BUSY) 302 goto timeout; 303 ichsmb_intr(sc); 304 } else { 305 /* Wait for interrupt */ 306 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 307 goto timeout; 308 } 309 310 if (sc->sc_i2c_xfer.error) 311 return (1); 312 313 return (0); 314 315 timeout: 316 /* 317 * Transfer timeout. Kill the transaction and clear status bits. 318 */ 319 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 320 aprint_error_dev(sc->sc_dev, 321 "exec: op %d, addr 0x%02x, cmdlen %zd, len %zd, " 322 "flags 0x%02x: timeout, status 0x%s\n", 323 op, addr, cmdlen, len, flags, fbuf); 324 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, 325 LPCIB_SMB_HC_KILL); 326 DELAY(ICHIIC_DELAY); 327 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 328 if ((st & LPCIB_SMB_HS_FAILED) == 0) { 329 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 330 aprint_error_dev(sc->sc_dev, "abort failed, status 0x%s\n", 331 fbuf); 332 } 333 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 334 return (1); 335 } 336 337 static int 338 ichsmb_intr(void *arg) 339 { 340 struct ichsmb_softc *sc = arg; 341 uint8_t st; 342 uint8_t *b; 343 size_t len; 344 #ifdef ICHIIC_DEBUG 345 char fbuf[64]; 346 #endif 347 348 /* Read status */ 349 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS); 350 if ((st & LPCIB_SMB_HS_BUSY) != 0 || (st & (LPCIB_SMB_HS_INTR | 351 LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED | 352 LPCIB_SMB_HS_SMBAL | LPCIB_SMB_HS_BDONE)) == 0) 353 /* Interrupt was not for us */ 354 return (0); 355 356 #ifdef ICHIIC_DEBUG 357 snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st); 358 printf("%s: intr st 0x%s\n", device_xname(sc->sc_dev), fbuf); 359 #endif 360 361 /* Clear status bits */ 362 bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, st); 363 364 /* Check for errors */ 365 if (st & (LPCIB_SMB_HS_DEVERR | LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED)) { 366 sc->sc_i2c_xfer.error = 1; 367 goto done; 368 } 369 370 if (st & LPCIB_SMB_HS_INTR) { 371 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 372 goto done; 373 374 /* Read data */ 375 b = sc->sc_i2c_xfer.buf; 376 len = sc->sc_i2c_xfer.len; 377 if (len > 0) 378 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 379 LPCIB_SMB_HD0); 380 if (len > 1) 381 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 382 LPCIB_SMB_HD1); 383 } 384 385 done: 386 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 387 wakeup(sc); 388 return (1); 389 } 390
Indexes created Thu Oct 02 14:10:14 GMT 2025